CN1230750C - 临时指令与非临时指令共享的高速缓存结构 - Google Patents

临时指令与非临时指令共享的高速缓存结构 Download PDF

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Publication number
CN1230750C
CN1230750C CNB998047333A CN99804733A CN1230750C CN 1230750 C CN1230750 C CN 1230750C CN B998047333 A CNB998047333 A CN B998047333A CN 99804733 A CN99804733 A CN 99804733A CN 1230750 C CN1230750 C CN 1230750C
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data
cache
ephemeral
processor
cache memory
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CN1295687A (zh
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S·帕兰卡
N·L·科雷
A·纳朗
V·彭特科夫斯基
S·蔡
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Intel Corp
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Intel Corp
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • G06F12/121Replacement control using replacement algorithms
    • G06F12/126Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CNB998047333A 1998-03-31 1999-03-24 临时指令与非临时指令共享的高速缓存结构 Expired - Lifetime CN1230750C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/053,386 1998-03-31
US09/053386 1998-03-31
US09/053,386 US6202129B1 (en) 1998-03-31 1998-03-31 Shared cache structure for temporal and non-temporal information using indicative bits

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CN1295687A CN1295687A (zh) 2001-05-16
CN1230750C true CN1230750C (zh) 2005-12-07

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CNB998047333A Expired - Lifetime CN1230750C (zh) 1998-03-31 1999-03-24 临时指令与非临时指令共享的高速缓存结构

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US (2) US6202129B1 (enExample)
EP (1) EP1066566B1 (enExample)
JP (1) JP4486750B2 (enExample)
KR (1) KR100389549B1 (enExample)
CN (1) CN1230750C (enExample)
AU (1) AU3364599A (enExample)
BR (1) BR9909295A (enExample)
RU (1) RU2212704C2 (enExample)
TW (1) TW573252B (enExample)
WO (1) WO1999050752A1 (enExample)

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US9342453B2 (en) 2011-09-30 2016-05-17 Intel Corporation Memory channel that supports near memory and far memory access
US9378142B2 (en) 2011-09-30 2016-06-28 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
US9600416B2 (en) 2011-09-30 2017-03-21 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy

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US9317429B2 (en) 2011-09-30 2016-04-19 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy over common memory channels
US9342453B2 (en) 2011-09-30 2016-05-17 Intel Corporation Memory channel that supports near memory and far memory access
US9378142B2 (en) 2011-09-30 2016-06-28 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
US9600416B2 (en) 2011-09-30 2017-03-21 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy
US9619408B2 (en) 2011-09-30 2017-04-11 Intel Corporation Memory channel that supports near memory and far memory access
US10102126B2 (en) 2011-09-30 2018-10-16 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
US10241912B2 (en) 2011-09-30 2019-03-26 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy
US10241943B2 (en) 2011-09-30 2019-03-26 Intel Corporation Memory channel that supports near memory and far memory access
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US11132298B2 (en) 2011-09-30 2021-09-28 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy having different operating modes

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WO1999050752A1 (en) 1999-10-07
AU3364599A (en) 1999-10-18
WO1999050752A9 (en) 2000-05-25
EP1066566A4 (en) 2002-10-23
US6584547B2 (en) 2003-06-24
EP1066566A1 (en) 2001-01-10
US20020007441A1 (en) 2002-01-17
RU2212704C2 (ru) 2003-09-20
TW573252B (en) 2004-01-21
EP1066566B1 (en) 2006-11-02
JP4486750B2 (ja) 2010-06-23
BR9909295A (pt) 2000-12-05
KR100389549B1 (ko) 2003-06-27
KR20010042262A (ko) 2001-05-25
US6202129B1 (en) 2001-03-13
CN1295687A (zh) 2001-05-16
JP2002510085A (ja) 2002-04-02

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