KR100384079B1 - 반도체 패키지 - Google Patents
반도체 패키지 Download PDFInfo
- Publication number
- KR100384079B1 KR100384079B1 KR10-1999-0048008A KR19990048008A KR100384079B1 KR 100384079 B1 KR100384079 B1 KR 100384079B1 KR 19990048008 A KR19990048008 A KR 19990048008A KR 100384079 B1 KR100384079 B1 KR 100384079B1
- Authority
- KR
- South Korea
- Prior art keywords
- chip
- mounting plate
- chip mounting
- semiconductor package
- area
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
Claims (3)
- 칩 탑재판과 리드(24)를 포함하는 리드프레임과, 상기 리드프레임의 칩 탑재판에 접착수단(22)에 의하여 실장된 칩(16)과, 칩(16)의 본딩패드와 리드(24)간을 연결하는 와이어(18)와, 상기 칩(16)과 와이어(18)와 칩 탑재판등을 몰딩하고 있는 수지(20)로 이루어진 구조의 반도체 패키지에 있어서,상기 리드프레임의 사이드 레일(30)과 타이바(26)로 연결 고정되어 있는 칩탑재판을 상기 타이바가 연결되는 연결틀(28)과, 이 연결틀(28)의 안쪽으로 돌출되며 일체 성형된 다수의 바(bar)형 칩탑재판(14a)으로 구성하여 칩탑재 면적을 감소시킨 것을 특징으로 하는 반도체 패키지.
- 제 1 항에 있어서, 상기 반도체 패키지(10)의 칩탑재판(14a)은 폭보다 길이가 긴 형상으로서, 상기 연결틀(28)의 안쪽으로 좌우대칭의 방사형을 이루며 돌출 성형된 것을 특징으로 하는 반도체 패키지.
- 제 1 항 또는 제 2 항에 있어서, 상기 칩탑재판(14a)의 끝단에는 칩탑재판(14a)의 폭보다 큰 면적을 갖도록 성형시킨 것을 특징으로 하는 반도체 패키지.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-1999-0048008A KR100384079B1 (ko) | 1999-11-01 | 1999-11-01 | 반도체 패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-1999-0048008A KR100384079B1 (ko) | 1999-11-01 | 1999-11-01 | 반도체 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010044947A KR20010044947A (ko) | 2001-06-05 |
KR100384079B1 true KR100384079B1 (ko) | 2003-05-14 |
Family
ID=19618059
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-1999-0048008A KR100384079B1 (ko) | 1999-11-01 | 1999-11-01 | 반도체 패키지 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100384079B1 (ko) |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0496261A (ja) * | 1990-08-03 | 1992-03-27 | Yamada Seisakusho Co Ltd | リードフレーム及びモールド金型 |
KR920008908A (ko) * | 1990-10-11 | 1992-05-28 | 김광호 | 멀티-패드 리이드 프레임 |
KR960026691A (ko) * | 1994-12-16 | 1996-07-22 | 황인길 | 반도체 패키지 제조용 리드프레임 패드구조 |
KR960043142A (ko) * | 1995-05-16 | 1996-12-23 | 이대원 | 반도체 리드프레임 |
US5661338A (en) * | 1994-12-14 | 1997-08-26 | Anam Industrial Co., Ltd. | Chip mounting plate construction of lead frame for semiconductor package |
KR19980033773A (ko) * | 1996-11-01 | 1998-08-05 | 황인길 | 반도체 패키지용 리드 프레임 |
JPH10326857A (ja) * | 1998-06-26 | 1998-12-08 | Matsushita Electron Corp | リードフレームとそれを用いた半導体装置およびその製造方法 |
KR200245730Y1 (ko) * | 1995-12-29 | 2001-12-17 | 마이클 디. 오브라이언 | 반도체패키지의리드프레임구조 |
-
1999
- 1999-11-01 KR KR10-1999-0048008A patent/KR100384079B1/ko active IP Right Grant
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0496261A (ja) * | 1990-08-03 | 1992-03-27 | Yamada Seisakusho Co Ltd | リードフレーム及びモールド金型 |
KR920008908A (ko) * | 1990-10-11 | 1992-05-28 | 김광호 | 멀티-패드 리이드 프레임 |
US5661338A (en) * | 1994-12-14 | 1997-08-26 | Anam Industrial Co., Ltd. | Chip mounting plate construction of lead frame for semiconductor package |
KR960026691A (ko) * | 1994-12-16 | 1996-07-22 | 황인길 | 반도체 패키지 제조용 리드프레임 패드구조 |
KR960043142A (ko) * | 1995-05-16 | 1996-12-23 | 이대원 | 반도체 리드프레임 |
KR200245730Y1 (ko) * | 1995-12-29 | 2001-12-17 | 마이클 디. 오브라이언 | 반도체패키지의리드프레임구조 |
KR19980033773A (ko) * | 1996-11-01 | 1998-08-05 | 황인길 | 반도체 패키지용 리드 프레임 |
JPH10326857A (ja) * | 1998-06-26 | 1998-12-08 | Matsushita Electron Corp | リードフレームとそれを用いた半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20010044947A (ko) | 2001-06-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5545922A (en) | Dual sided integrated circuit chip package with offset wire bonds and support block cavities | |
KR970072358A (ko) | 반도체패키지의 제조방법 및 구조 | |
JPH10284525A (ja) | 半導体装置の製造方法 | |
KR0141952B1 (ko) | 반도체 패키지 및 그 제조방법 | |
KR100781149B1 (ko) | 리드프레임 스트립 및 이를 이용한 반도체 패키지 제조 방법 | |
KR19980020296A (ko) | 반도체 칩 패키지 | |
US6686652B1 (en) | Locking lead tips and die attach pad for a leadless package apparatus and method | |
KR100384079B1 (ko) | 반도체 패키지 | |
KR20020093250A (ko) | 리드 노출형 리드 프레임 및 그를 이용한 리드 노출형반도체 패키지 | |
KR100632256B1 (ko) | 더미리드들을 포함하는 리드 온 칩형 리드 프레임 | |
KR100575859B1 (ko) | 볼 그리드 어레이 패키지 | |
KR0147638B1 (ko) | 반도체 리드 프레임 | |
KR100440789B1 (ko) | 반도체 패키지와 이것의 제조방법 | |
KR100199829B1 (ko) | 반도체패키지용 리드프레임 | |
KR200141125Y1 (ko) | 리드프레임의 구조 | |
KR950000101Y1 (ko) | 반도체 패키지용 리드 프레임 | |
KR0152902B1 (ko) | 버텀리드형 반도체 패키지의 구조 및 그 제조방법 | |
KR200292790Y1 (ko) | 반도체 패키지용 리드프레임의 탑재판 구조 | |
KR970006222Y1 (ko) | 리드프레임 | |
KR200170634Y1 (ko) | 반도체 패키지 | |
KR100290783B1 (ko) | 반도체 패키지 | |
KR0137067B1 (ko) | 히트싱크 내장형 패키지 제조방법 | |
KR100374135B1 (ko) | 반도체 패키지 제조용 리드프레임 및 이것의 제조방법 | |
KR950007769Y1 (ko) | 반도체 패키지 | |
KR100499606B1 (ko) | 반도체 패키지 제조용 부재 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
N231 | Notification of change of applicant | ||
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20130502 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20140430 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20150430 Year of fee payment: 13 |
|
FPAY | Annual fee payment |
Payment date: 20160503 Year of fee payment: 14 |
|
FPAY | Annual fee payment |
Payment date: 20170502 Year of fee payment: 15 |
|
FPAY | Annual fee payment |
Payment date: 20180502 Year of fee payment: 16 |
|
FPAY | Annual fee payment |
Payment date: 20190502 Year of fee payment: 17 |