KR100367394B1 - 반도체장치의cmos논리게이트및그제조방법 - Google Patents
반도체장치의cmos논리게이트및그제조방법 Download PDFInfo
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- KR100367394B1 KR100367394B1 KR10-1998-0045844A KR19980045844A KR100367394B1 KR 100367394 B1 KR100367394 B1 KR 100367394B1 KR 19980045844 A KR19980045844 A KR 19980045844A KR 100367394 B1 KR100367394 B1 KR 100367394B1
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- nmos transistor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 239000012535 impurity Substances 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 238000010292 electrical insulation Methods 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 230000001681 protective effect Effects 0.000 abstract description 18
- 230000000694 effects Effects 0.000 abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 239000010410 layer Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000005527 interface trap Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- High Energy & Nuclear Physics (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (3)
- 반도체기판에 소자간 분리를 위한 필드 산화막을 형성하는 단계;상기 기판 내에 제 1N형 웰을 형성하며 이 웰에 매몰 채널형 PMOS 트랜지스터의 문턱 전압을 조절하기 위한 p형 불순물을 주입하는 단계;상기 제 1N형 웰에 인접하도록 제 2N형 웰을 형성하며 이 웰에 표면 채널용 PMOS 트랜지스터의 문턱 전압을 조절하기 위한 n형 분순물을 주입하는 단계;상기 필드 산화막에 의해 분리되는 기판에 제 1N형 웰과 인접하도록 제 1P형 웰을 형성하며 매몰 채널용 NMOS 트랜지스터의 문턱 전압을 조절하기 위한 n형 불순물을 주입하는 단계; 및상기 제 1P형 웰에 인접하도록 제 2P형을 웰을 형성하며 이 웰에 표면 채널용 NMOS 트랜지스터의 문턱 전압을 조정하기 위한 n형 불순물을 주입하는 단계와,상기 트랜지스터들이 형성된 결과물 상에 전기적 절연을 위한 층간 절연막을 증착하는 단계와,상기 표면 채널용 PMOS 트랜지스터의 게이트와 상기 표면 채널용 NMOS 트랜지스터의 게이트에 입력 전압(Vin)과, 상기 메몰 채널용 PMOS 트랜지스터의 소오스와 상기 메몰 채널용 NMOS 트랜지스터의 드레인에 출력 전압(Vout)과, 상기 표면 채널용 PMOS 트랜지스터의 드레인과 상기 메몰 채널용 NMOS 트랜지스터의 게이트에 전원 전압(Vdd) 및 상기 메몰 채널용 PMOS 트랜지스터의 게이트와 상기 표면 채널용 NMOS 트랜지스터의 소오스에 접지 전압(GND)이 인가되도록 배선하는 단계를포함하여 이루어지는 것을 특징으로 하는 반도체장치의 CMOS 논리게이트의 제조방법.
- 제 1항에 있어서, 상기 제 1N형 웰에 p형 불순물을 주입한 후에 n형 불순물을 주입하는 단계를 더 포함하는 것을 특징으로 하는 반도체장치의 CMOS 논리게이트의 제조방법.
- 제 1항에 있어서, 상기 제 1P형 웰에 n형 불순물을 주입한 후에 p형 불순물을 주입하는 단계를 더 포함하는 것을 특징으로 하는 반도체장치의 CMOS 논리게이트의 제조방법.
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Application Number | Priority Date | Filing Date | Title |
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KR10-1998-0045844A KR100367394B1 (ko) | 1998-10-29 | 1998-10-29 | 반도체장치의cmos논리게이트및그제조방법 |
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KR10-1998-0045844A KR100367394B1 (ko) | 1998-10-29 | 1998-10-29 | 반도체장치의cmos논리게이트및그제조방법 |
Publications (2)
Publication Number | Publication Date |
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KR20010008402A KR20010008402A (ko) | 2001-02-05 |
KR100367394B1 true KR100367394B1 (ko) | 2003-03-26 |
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KR10-1998-0045844A KR100367394B1 (ko) | 1998-10-29 | 1998-10-29 | 반도체장치의cmos논리게이트및그제조방법 |
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Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100568451B1 (ko) * | 2004-09-14 | 2006-04-07 | 삼성전자주식회사 | 듀얼 게이트를 갖는 시모스 반도체소자의 제조방법 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS589290A (ja) * | 1981-07-10 | 1983-01-19 | Toshiba Corp | 半導体記憶装置 |
JPS639961A (ja) * | 1986-06-30 | 1988-01-16 | Nec Corp | 半導体集積回路 |
JPS6447064A (en) * | 1987-08-18 | 1989-02-21 | Seiko Epson Corp | Semiconductor device |
JPH09107281A (ja) * | 1995-10-11 | 1997-04-22 | Toshiba Microelectron Corp | Cmos入力回路装置 |
-
1998
- 1998-10-29 KR KR10-1998-0045844A patent/KR100367394B1/ko not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS589290A (ja) * | 1981-07-10 | 1983-01-19 | Toshiba Corp | 半導体記憶装置 |
JPS639961A (ja) * | 1986-06-30 | 1988-01-16 | Nec Corp | 半導体集積回路 |
JPS6447064A (en) * | 1987-08-18 | 1989-02-21 | Seiko Epson Corp | Semiconductor device |
JPH09107281A (ja) * | 1995-10-11 | 1997-04-22 | Toshiba Microelectron Corp | Cmos入力回路装置 |
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KR20010008402A (ko) | 2001-02-05 |
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