KR100364923B1 - Schottky Barrier Diode and its manufacturing method - Google Patents

Abstract

The present invention discloses a schottky barrier diode and a method of manufacturing the same. According to this, the outermost guard ring is formed on the epitaxial layer on the silicon substrate, and at least one inner guard ring is spaced apart from the innermost guard ring, and the barrier metal layer is formed on the outermost guard ring and all parts thereof. It laminates and forms a metal layer for wiring on it. Therefore, the present invention can form a plurality of guard rings without causing the size of the device, so that the entire planar junction formed at the interface between the guard rings and the epi layer is enlarged. Furthermore, when the width W1 of the guard rings and the spacing W2 of the schottky junction formed at the interface between the epi layer and the barrier metal layer between the guard rings are determined at a ratio of 1: 9, the reverse current I _R characteristic and the forward direction are determined. Both the voltage V _F characteristics become good.

Description

Schottky Barrier Diode and its manufacturing method {Schottky Barrier Diode and its manufacturing method}

The present invention relates to a Schottky Barrier Diode. More specifically, the present invention provides a short circuit for improving the forward voltage (V _F ) and reverse current (I _R ) characteristics without increasing the size of the device. A key barrier diode and a method for manufacturing the same.

In general, Schottky barrier diodes are semiconductor devices that use Schottky junctions between silicon substrates and metal layers, unlike PN junction diodes that use PN junctions on silicon substrates. In addition, the device is driven by the tunneling method using the Schottky junction between the silicon substrate and the metal layer, which shows a significantly lower on-state voltage drop characteristic than the PN junction diode. Therefore, Schottky Barrier Diode is mainly used as a core device such as power switch in the field of applications requiring low loss characteristics, that is, communication. Direction is being developed.

In the conventional Schottky barrier diode, as shown in FIG. 1, a low concentration N-type epitaxial layer 11 is grown on an N-type single crystal silicon substrate 10 having a high concentration of the first conductivity type, and the epitaxial layer 11 is formed. The P-type guard ring 13, which is a second conductivity type of high concentration, is diffused in a portion, and has an opening that exposes the epi layer 11 and the guard ring 13 inside the guard ring 13 and the outside of the guard ring 13. The oxide film 15 is formed on the epitaxial layer 11, the pattern of the barrier metal layer 17 is formed on the exposed guard ring 13 and the epitaxial layer 11 and a part of the oxide film 15, and molybdenum is formed. The pattern of the wiring metal layer 19 of aluminum (Al) material is formed on the pattern of the barrier metal layer 17 of (Mo) material. Here, a planar junction 14 is formed at the interface between the junction of the guard ring 13 and the epi layer 11 around it, and the schottky junction 18 is formed inside the guard ring 13. It is formed at the interface between the epi layer 11 and the barrier metal layer 15.

A conventional method for manufacturing a Schottky barrier diode configured as described above will be described with reference to FIGS. 2 to 4. First, as shown in FIG. 2, a first conductive type having a high concentration, for example, an N-type single crystal silicon substrate. A low concentration N-type epitaxial layer 11 is grown on (10), and then an insulating film, for example, an oxide film 12, is laminated on the epitaxial layer 11 by a thermal oxidation process. Subsequently, by using a photolithography process, the oxide film 12 positioned on the epi layer 11 of the portion where the guard ring 13 of FIG. 3 is to be formed is etched until the epi layer 11 below it is exposed. An opening of the oxide film 12 for defining (13) is formed. Then, the oxide film 12a is formed to a thickness thinner than the oxide film 12 on the exposed epitaxial layer 11 in the opening by using a thermal oxidation process. This is to suppress the generation of defects in the epi layer 11 in which the guard ring is to be formed when the ion implantation process for the guard ring is performed.

As shown in FIG. 3, after formation of the oxide film 12a is completed, a P-type impurity, for example, boron, which is a second conductivity type for forming the guard ring 13 using the oxide film 12 as a mask layer. Is implanted into the epitaxial layer 11 and then diffused by heat treatment to form a guard ring 13 on the epitaxial layer 11 under the oxide film 12a. At this time, the planar junction 14 is formed at the interface between the epi layer 11 and the guard ring 13. On the other hand, since the heat treatment process is performed in an oxidizing atmosphere, an oxide film is laminated on the oxide film 12 and the oxide film 12a to form the oxide film 15 as a whole.

As shown in FIG. 4, after the formation of the guard ring 13 is completed, the epitaxial layer 11 inside the guard ring 13, that is, the portion to form the schottky junction part 18 using a photolithography process. ) And the oxide film 15 positioned on the guard ring 13 by etching until the epi layer 11 and the guard ring 13 inside the guard ring 13 below it are exposed. Openings of the oxide film 15 for defining

Subsequently, a barrier metal layer 17 made of molybdenum (Mo) is stacked on the epi layer 11, the guard ring 13, and the oxide film 15 inside the exposed guard ring 13, and on the barrier metal layer 17 thereon. The wiring metal layer 19 of aluminum (Al) material is laminated on it. Accordingly, the schottky junction 18 is formed at the interface between the epi layer 11 inside the guard ring 13, the portion of the guard ring 13, and the barrier metal layer 17. Therefore, the planar junction 14 and the schottky junction 18 constitute the entire junction and determine the reverse current (I _R ) characteristics of the schottky barrier diode.

Finally, by using a photolithography process, the Schottky barrier diode as shown in FIG. 1 is completed by forming a pattern in which only the desired portions of the metal layer 19 and the barrier metal layer 17 are removed and the remaining unnecessary portions are removed.

However, in the case of the conventional Schottky barrier diode, the barrier metal layer 17 is made of a material capable of minimizing the height of the barrier or maximizes the area of the entire junction where the planar junction 14 and the schottky junction 18 are combined. Therefore, the characteristics of the forward voltage V _F have been improved by increasing the current density per unit area of the junction.

However, the former method because it uses the material considering only drop in the nature of the forward voltage (V _F) of the barrier metal layer 17, which minimizes the barrier height to reduce the forward voltage (V _F) but the reverse current (I _R Increases the electrical properties). In the latter method, since the guard ring 13 is disposed only outside the schottky junction 18, the area of the device increases as the size of the guard ring 13 increases, and furthermore, the integration of the device is reduced. As a result, the conventional Schottky barrier diode using these methods has a limit in improving the electrical characteristics reflecting the forward voltage (V _F ) characteristics and the reverse current (I _R ) characteristics.

Accordingly, an object of the present invention is to provide a schottky barrier diode and a method of manufacturing the same, which improves the characteristics of the reverse current I _R together with the forward voltage V _F without causing a decrease in the degree of integration of the device.

1 is a cross-sectional view showing a Schottky barrier diode according to the prior art.

2 to 4 is a process chart showing a method for manufacturing a schottky diode according to the prior art.

5 is a cross-sectional view showing a Schottky barrier diode according to the present invention.

6 to 8 is a process chart showing a method of manufacturing a schottky barrier diode according to the present invention.

Schottky barrier diode according to the present invention for achieving the above object

A high concentration of the first conductivity type single crystal silicon substrate;

A first conductive epitaxial layer having a low concentration formed on the silicon substrate;

Guard rings spaced apart from each other at predetermined intervals on the epi layer;

A barrier metal layer formed on the guard rings and an epi layer between them; And

It characterized in that it comprises a metal layer for wiring formed on the barrier metal layer.

Preferably, the width of each of the guard rings and the width between the guard rings may be in a ratio of 1: 9. It is preferable that the said width is 40 micrometers, and the space | interval is 36040 micrometers.

In addition, the production method of the schottky barrier diode according to the present invention

Forming a low concentration of the first conductivity type epi layer on the high concentration of the first conductivity type single crystal silicon substrate;

Forming guard rings having a planar junction portion spaced apart from each other at a predetermined interval on the epi layer;

Stacking a barrier metal layer on the epitaxial layer between the guard rings and the guard rings to form a schottky cushion; And

And laminating a wiring metal layer on the barrier metal layer.

Preferably, the width of each of the guard rings and the width between the guard rings may be formed in a ratio of 1: 9. It is preferable that the said width is 40 micrometers, and the space | interval is 360 micrometers.

Therefore, according to the present invention, the entire plate formed at the interface between all the guard rings and the epi layer by constituting the guard rings with the outermost guard ring and at least one inner guard ring spaced apart from the innermost of the outermost guard ring. The unjunction portion can be enlarged without causing an increase in the size of the device. In addition, the schottky junction formed at the interface between the epi layer and the barrier metal layer between the guard rings is formed in the same manner as in the prior art. As a result, the electrical characteristics showing the relationship between the reverse current I _R and the reverse voltage V _R can be improved while maintaining the characteristics of the forward voltage V _F as it is.

Hereinafter, the Schottky barrier diode and its manufacturing method according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part of the same structure and the same action as the conventional part.

5 is a cross-sectional view illustrating a schottky barrier diode according to the present invention, and FIGS. 6 to 8 are process charts illustrating a method of manufacturing a schottky barrier diode according to the present invention.

Referring to FIG. 5, in the Schottky barrier diode of the present invention, a low concentration N-type epitaxial layer 11 is grown on an N-type single crystal silicon substrate 10 which is a high concentration first conductivity type, and is defined in the epi layer 11. P-type guard rings 30, the second conductive type having a high concentration, are diffused at intervals, and the outermost guard ring 31 has an opening that exposes the guard rings 30 and the epi layer 11 inside thereof. An oxide film 25 is formed on the outer epitaxial layer 11, and a barrier metal layer made of molybdenum (Mo) is formed on the exposed guard rings 30, the epitaxial layer 11, and a part of the oxide layer 25. The pattern of 40 is formed, and the pattern of the wiring metal layer 50 of aluminum (Al) material is formed on the pattern of the barrier metal layer 40. Here, the planar junction 32, (at the interface between the outermost guard ring 31 and the inner guard rings 33, 35 of the guard rings 30, and the epi layer 11 around it (( 34 and 36 are formed respectively. A schottky junction 48 is formed on the surfaces of the guard rings 31, 33, 35 and the epi layer 11 and the barrier metal layer 15. The width of the guard rings 31, 33, 35 is W1, and the spacing between the guard rings 31, 33, 35 is W2. On the other hand, for convenience of description it is shown that there are only two inner guard rings, but may be one or three or more. There is a method for manufacturing a Schottky barrier diode according to the present invention configured as described above with reference to FIGS. This will be described with reference.

Referring to FIG. 6, first, a low concentration N-type epitaxial layer 11 is grown to a thickness of, for example, 5 μm on a first concentration of a first conductivity type, for example, an N-type single crystal silicon substrate 10. Then, an insulating film, for example, an oxide film 21 is laminated on the epi layer 11 by a thermal oxidation process, and the guard rings 31, 33, 35 of FIG. 7 are formed by a photolithography process. Defining the guard rings 31, 33, 35 by etching the oxide film 21 positioned on the epi layer 11 of the portion to be formed until the epi layer 11 below it is exposed. The openings of the oxide film 12 are formed to be spaced apart from each other. Here, the width of the opening and the gap between the openings are the widths W1 of the guard rings 31, 33, 35 of FIG. 7 to be formed in a subsequent process, and the guard rings 31, 33, An interval W2 between 35 is determined, which determines the size of the planar junction of the guard rings and the size of the schottky junction between the guard rings.

Then, an oxide film 22 is formed on the exposed epitaxial layer 11 in the opening to have a thickness thinner than that of the oxide film 21 using a thermal oxidation process. This is to suppress the generation of defects in the epi layer 11 in which the guard rings are to be formed when the ion implantation process for the formation of the guard rings is performed. Here, the oxide film 21 preferably has a thickness of 7000 to 8000 Å sufficient to serve as a mask layer when performing the ion implantation process for the guard rings 31, 33, 35.

After the formation of the oxide film 22 is completed, the P-type impurity, which is the second conductivity type for using the oxide film 21 as a mask layer and forming the guard rings 31, 33, and 35 of FIG. For example, boron is implanted into the epi layer 11.

Referring to FIG. 7, when the ion implantation process of boron is completed, the ion implanted boron is diffused by a heat treatment process so that the respective guard rings 31 and 33 are formed on the epi layer 11 under the oxide film 22. , 35 are formed to be spaced apart from the width (W1) and the interval (W2). Accordingly, the inner guard ring 33 is disposed at the inner side of the outermost guard ring 31 at a gap W2, and the inner guard ring 35 is disposed at the inner side of the inner guard ring 33 at an interval W2. To place. Planar junctions 32, 34 and 36 are formed at the interface between the guard rings 31, 33, 35 and the epi layer 11, respectively. The total planar junction is determined by the sum of the planar junctions 32, 34 and 36. On the other hand, since the heat treatment process is performed in an oxidizing atmosphere, an oxide film is laminated on the oxide film 21 and the oxide film 22 to form the oxide film 25 as a whole.

Referring to FIG. 8, once formation of the guard rings 31, 33, and 35 is completed, a portion of the schottky junction 48 is formed using a photolithography process, that is, the guard ring 31. ) And the oxide film 25 located on the inner portion thereof are etched until the guard rings 31, 33, 35 and the epi layer 11 below them are exposed. An opening of the oxide film 25 is defined to define.

Subsequently, a barrier metal layer 40 made of molybdenum (Mo) is laminated on the exposed guard rings 31, 33, 35, and the epi layer 11 and the oxide layer 25 in the opening, and the aluminum material is formed thereon. The wiring metal layer 50 is laminated. Accordingly, a schottky junction 48 is formed at the interface between the guard rings 31, 33, 35 and the epi layer 11 and the barrier metal layer 40, and each schottky junction section ( The width of 48) is determined as W2.

Accordingly, the reverse current I _R characteristics of the schottky barrier diode are determined by the planar junction 32 and the schottky junction 48. That is, if the width W1 of the guard rings 31, 33, 35 is 40 μm, the width W2 of the schottky junction 48 is preferably 360 μm, which is spaced from the width W1. (W2) ratio of 1: 9 days when a reverse current (I _R) characteristic and the forward voltage (V _F) are all good, but the reverse current when the ratio of 1:10 in the width (W1) and distance (W2) (I _R This is because the forward voltage (V _F ) characteristic becomes poor when the characteristic is poor and the ratio of the width W1 and the interval W2 is 2: 9.

Finally, by using the photolithography process, the Schottky barrier diode as shown in FIG. 5 is completed by forming a pattern in which only the desired portions of the metal layer 50 and the barrier metal layer 40 are removed and the remaining unnecessary portions are removed.

As described above, according to the present invention, the outermost guard ring is formed on the epitaxial layer on the silicon substrate, and at least one inner guard ring is formed on the inner side of the outermost guard ring, and the outermost guard ring and the innermost guard ring are formed. The barrier metal layer is laminated on all parts and the wiring metal layer is formed thereon. Therefore, the present invention can form a plurality of guard rings without causing the size of the device, so that the entire planar junction formed at the interface between the guard rings and the epi layer is enlarged. Furthermore, when the width W1 of the guard rings and the spacing W2 of the schottky junction formed at the interface between the epi layer and the barrier metal layer between the guard rings are determined at a ratio of 1: 9, the reverse current I _R characteristic and the forward direction are determined. Both the voltage V _F characteristics become good.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

Claims (6)

(Corrected) high concentration first conductivity type single crystal silicon substrate; A first conductive epitaxial layer having a low concentration formed on the silicon substrate; A plurality of guard rings spaced apart from each other at predetermined intervals on the epi layer; An oxide film formed on the outermost guard ring and the outer epitaxial layer and having an opening exposing the plurality of guard rings and the inner epitaxial layer together; A barrier metal layer formed on the plurality of guard rings and an epi layer therebetween; And A plurality of planar junction portions formed at an interface between the plurality of guard rings and the epi layer; A schottky barrier diode comprising a wiring metal layer formed on the barrier metal layer. (Correction) The method of claim 1, wherein the width W1 of each of the plurality of guard rings and the distance W2 between the guard rings are in a ratio of 1: 9 so that the reverse current I _R characteristic and the forward voltage are adjusted. (V _F ) Schottky barrier diode characterized by improving the characteristics. (Correction) The Schottky barrier diode according to claim 2, wherein the width W1 of the plurality of guard rings is 40 m and the gap W2 is 360 m. (Correction) forming a first concentration epitaxial layer having a low concentration on the first conductivity type single crystal silicon substrate at a high concentration; Forming a plurality of guard rings having a planar junction portion spaced apart from each other at a predetermined interval on the epi layer; Stacking a barrier metal layer for forming a schottky cushion on an epitaxial layer between the plurality of guard rings and the plurality of guard rings; And And stacking a wiring metal layer on the barrier metal layer. 5. The Schottky barrier diode of claim 4, wherein the width W1 of each of the plurality of guard rings and the spacing W2 between the guard rings are formed in a ratio of 1: 9. Manufacturing method. (Correction) The method according to claim 5, wherein the width W1 of the plurality of guard rings is 40 µm and the interval W2 is 360 µm.