JPH07263716A - Semiconductor device - Google Patents

Abstract

PURPOSE:To attenuate a reverse current by suppressing the increase of forward rise voltage by a method wherein a low impurity density semiconductor region of one conductivity type is arranged between semiconductor regions of another conductivity type which are in close vicinity with each other. CONSTITUTION:The title semiconductor device is formed in three-layer structure by arranging a p<+> region 1 adjacent to the Schottky junction which is formed by the barrier metal provided on an n-region 3 and a semiconductor, an n-type semiconductor substrate is formed on an n<+> region 3, and a thin n-region 2 is formed thereon. The thin n<-> region 2 functions as an electric field alleviation layer, and an n<+> region 4 is used for formation of a cathode electrode. By arranging the thin n<-> region 2, which functions as an electric field allevia-tion layer, directly under the Schottky junction, the depletion layer of width W2 spreads from the p<+> region 1 to the n- -region 3 and at the same time, the depletion layer of width W1 quickly spreads from the p<+> region 1 to the n<-> region 2 located directly under the Schottky junction when inverted bias is applied to diode, and the effect of electric field can be alleviated efficiently.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a diode having low loss and high speed response.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor integrated circuits,
A low voltage power supply with a low operating voltage is required. Also,
With the spread of portable electronic devices such as mobile phones, there is an increasing demand for compact and low-loss DC power supplies. Such a power supply circuit requires a rectifier diode which has a low loss and can respond at high speed. A Schottky diode is known as a rectifying diode that satisfies this requirement. A Schottky diode is a diode obtained by contact between a metal and a semiconductor, and majority carriers dominate the rectification characteristics. Therefore, the rectification time is short and it is excellent as a high frequency rectifier.

FIG. 7 shows a sectional view of a general Schottky diode. In such a Schottky diode, for example, after the n-type layer 3 having an appropriate impurity concentration (medium impurity concentration) is deposited by epitaxial growth on the low-resistance (high impurity concentration) n-type semiconductor substrate 4 in consideration of the breakdown voltage, After the high impurity concentration p-type diffusion layer 1 and the insulating layer 9 are formed, the barrier metal 6 having an appropriate barrier height is brought into contact with it. In addition, 8 is an ohmic metal electrode. Since such a Schottky diode is a majority carrier device having a lower forward rise voltage than a pn junction diode, it has an advantage that it has no effect of accumulating carriers due to minority carriers and has a high speed response.
However, on the other hand, there are drawbacks such as large forward loss and large reverse current, low withstand voltage, and poor temperature characteristics.
It could only be used in the relatively low voltage range.

Generally, in order to reduce the forward loss of the Schottky diode, a barrier metal having a low barrier height may be used. However, when a barrier metal having a low barrier height is used, the reverse current becomes large and the reverse loss increases. As described above, since there is a trade-off relationship between the forward characteristic and the reverse characteristic of the Schottky diode, there is a limit to the method of controlling the barrier height to improve the characteristic. As another method of reducing the forward voltage, there is a method of increasing the impurity concentration of the n-type epitaxial layer. However, increasing the impurity concentration increases the electric field strength at the Schottky interface and causes the Schottky effect. Schottky barrier height is lowered,
As a result, there is a drawback that the reverse current is increased. Therefore, in order to improve the characteristics of the Schottky diode, a barrier metal with a small barrier height is used, and even if the n-type epitaxial layer is highly concentrated, the reverse current does not increase so that the Schottky junction interface does not increase. It was necessary to relax the electric field strength.
In recent years, as a method for improving the drawbacks of the conventional technique, a pn junction is arranged around a Schottky diode, and when a reverse bias is applied to the diode, a depletion layer is extended from the pn junction just below the Schottky junction. Many methods have been proposed in which the electric field strength at the Schottky junction interface is relaxed and the reverse current is reduced.

FIG. 8 shows a sectional view of a Schottky diode proposed in Japanese Patent Laid-Open No. 5-136015, and its structure and operation will be described. After the n-type layer 3 having an appropriate impurity concentration considering the breakdown voltage is grown on the low-resistance n-type semiconductor substrate 4 by epitaxial growth, an appropriate interval Ws is provided between them.
The high impurity concentration p-type semiconductor region 1 is formed so as to have Schottky barrier metal 6 on the semiconductor surface
Is adhered to the entire surface, and a Schottky junction is formed by joining the n-type layer 3 and the barrier metal 6. Also, high concentration p
The type semiconductor region 1 and the Schottky junction are electrically connected. The interval Ws is designed so that the depletion layer 5 from the high-concentration p-type semiconductor region 1 is sufficiently pinched off when a reverse bias is applied to the Schottky electrode.

When a reverse bias is applied to the Schottky diode having such a structure, the depletion layer 5 extending from the pn junction formed by the high-concentration p-type region 1 and the n-type layer 3 eliminates carriers just below the Schottky junction. As a result, the electric field strength at the Schottky junction interface is relaxed. In addition, the electric current at the Schottky interface is relaxed, so that the reverse current is reduced. In such a Schottky diode, by limiting the forward current, it is possible to reduce the current flowing through the pn junction, suppress the effect of accumulating minority carriers, and operate at high speed.
The high-concentration p-type region 1 also has an effect as a guard ring. Furthermore, in this Schottky diode, by further shortening or deepening the high-concentration p-type region interval Ws, a further electric field relaxation effect can be expected.

However, in the above-mentioned conventional diode, the effective Schottky area of the device is reduced by shortening or deepening the high-concentration p-type region interval Ws. That is, there is a problem that the forward current density is lowered, the series resistance is further increased, and as a result, the forward rising voltage is increased. That is, if the impurity concentration of the n-type epitaxial layer 3 is increased in order to reduce the forward voltage, it is necessary to narrow the high-concentration p-type region spacing Ws in order to obtain the same electric field relaxation effect. ,
For the above reason, there is a drawback in that the rise voltage is increased. Further, in a diode used in a power supply circuit with a small output voltage, only a low reverse voltage is applied to the pn junction, so that the depletion layer does not sufficiently spread immediately below the Schottky junction and an electric field relaxation effect cannot be expected. Further, if the high-concentration p-type region interval Ws is narrowed to obtain the electric field relaxation effect, there is a problem that the forward-direction rising voltage is also increased.

[0008]

As described above, the conventional diode has a limitation in improving the characteristics because of the problems of the decrease of the current density and the increase of the series resistance. Furthermore, a sufficient electric field relaxation effect cannot be expected for a rectifying diode compatible with a low output power source, and it is difficult to obtain a low loss diode.

The present invention has been made in view of the above-mentioned drawbacks of the prior art, and suppresses an increase in forward-direction rising voltage,
An object of the present invention is to provide a high-speed rectifier diode that reduces reverse current and has little power loss.

[0010]

The most important means of solving the problems of the present invention is to reduce the impurity concentration directly under the Schottky junction in order to reduce the electric field at the Schottky junction interface sensitively at a low voltage as compared with the prior art. This is because an electric field relaxation layer made of a concentrated semiconductor is provided. That is, the present invention provides a semiconductor substrate having a medium conductivity type one conductivity type semiconductor region formed on a high impurity concentration one conductivity type semiconductor region, and at least two semiconductor layers formed on the surface of this middle impurity concentration one conductivity type semiconductor region. In a semiconductor device having two other conductivity type semiconductor regions and a metal formed on the surface of a semiconductor substrate including the other conductivity type semiconductor regions, one conductivity type low region is provided between adjacent other conductivity type semiconductor regions. The main feature is that an impurity concentration semiconductor region is provided.

[0011]

According to the present invention, a low impurity concentration semiconductor having an impurity concentration, a thickness and a width appropriately set as necessary as an electric field relaxation layer immediately below a Schottky junction surrounded by a high impurity concentration p-type semiconductor region. By forming the layer, a sufficient electric field relaxation effect can be obtained even at a low voltage, and a rectifying diode with low loss can be obtained.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. Figure 1
A sectional view of a semiconductor device according to the present invention is shown in FIG. Reference numeral 1 is a high impurity concentration p-type semiconductor region (hereinafter referred to as p + region, where p + is a plus (+) mark at the upper right of p), and 2 is a low impurity concentration n-type semiconductor region (hereinafter referred to as n− region. n− represents n at the upper right of −, 3 is a medium impurity concentration n-type semiconductor region (hereinafter referred to as n region), 4 is a high impurity concentration n-type semiconductor region (hereinafter referred to as n + region, where n + Represents the thing with + attached to the upper right of n). Similar to the conventional diode, the diode of the present invention has a structure in which the p + region 1 is arranged adjacent to the Schottky junction formed by the n region 3 and a barrier metal (not shown) formed on these semiconductors. However, it is characteristic that the n-type semiconductor substrate has a three-layer structure in which an n region 3 is stacked on an n + region 4, and a thin n− region 2 is further stacked thereon. The thin n− region 2 functions as an electric field relaxation layer, and the n + region 4 is used as a cathode electrode. The basic principle of the present invention was made by paying attention to the fact that the depletion layer spreads wider as the impurity concentration in the region where the depletion layer spreads is lower. That is,
A thin n- layer that acts as an electric field relaxation layer just below the Schottky junction.
By arranging the region 2, when a reverse bias is applied to the diode according to the present invention, a depletion layer having a width W ₂ spreads from the p + region 1 to the n region 3 and at the same time, immediately under the Schottky junction from the p + region 1. The depletion layer of W ₁ also spreads to the n − region 2 and the electric field can be efficiently relaxed. Note that Wp shown in FIG. 1 is the width of the p + region in the lateral direction, Ws is the distance between adjacent ends of adjacent p + regions 1 (Schottky junction width), Ln ₁ is the junction depth of the n− region 2, and Ln ₂ is the junction depth of the n region 3, and XX ′ is a straight line that passes through the Schottky junction and is perpendicular to the surface of the semiconductor substrate, and is defined because it is necessary in the subsequent description. In addition, what is indicated by the same number in the drawings,
They are the same.

Next, embodiments of the present invention based on the above technical idea will be described in detail. FIG. 2 shows a Schottky diode manufactured using the semiconductor device of the present invention. The semiconductor substrate in this example has a specific resistance of 0.002 Ω-cm, a specific resistance of 0.3 Ω-cm, and an impurity concentration of 2 × 10 ¹⁶ / c by epitaxial growth on the n + Si substrate 4 having a thickness of 280 μm.
The thickness of the n region 3 which is an epitaxial layer of m ³ is 6.0 μm.
It was grown to m. An n-region 2 having a specific resistance of 1 Ω-cm and an impurity concentration of 5 × 10 ¹⁵ / cm ³ was further formed on the surface of the Si epitaxial substrate as an electric field relaxation layer in an amount of 0.5 μm.
Epitaxially grown to a thickness of. Next, p + region 1 is formed on the surface of the epitaxial layer and the impurity concentration of the surface is 1 × 1.
Stripes were formed by selective diffusion so as to have a density of 0 ²⁰ / cm ³ . The width Wp of the p + region 1 was about 2 μm, the junction depth Lp was about 2 μm, and the Schottky junction width Ws was about 2 μm. Al is vapor-deposited on the back surface of the substrate as the ohmic electrode 8 by about 1 μm and subjected to sintering treatment. A Ti film having a barrier height φ (B0) = 0.49 eV was deposited as a barrier metal 6 on the entire upper surfaces of the p + region 1 and the n− region 2 by electron beam evaporation to about 2000 Å. Evaporated T
The i film was heat-treated in vacuum at 350 ° C. for 15 minutes.
Finally, for protection of the barrier metal, an Al film as the protective metal 7 was deposited by about 1 μm.

As a result of evaluating the electrical characteristics of the Schottky diode formed as described above, the forward current density 60
The forward voltage was 0.25 V at A / cm ² , and the reverse current at 0.1 V was 0.11 A / cm ² . As a result, the power loss per unit area of the diode was 16.1 W / cm ² at room temperature.

As a structure in which the above-described embodiment is improved, a low impurity concentration region is surrounded by a medium impurity concentration region so as to be isolated to limit the spread of the depletion layer at zero bias. The density can be increased. For example, as shown in FIG. 1, when the p + region 1 and the n− region 2 as the electric field relaxation layer are in contact with each other, the width of the depletion layer 5 extending to the n-type semiconductor region at zero bias is as shown by the dotted line in the figure. In the n-region 2, it is wide and W _1, and in the n region 3, it is short and W ₂ . Therefore, the width of the current path flowing under the forward bias is narrowed to (Ws−2 × W ₁ ). Such a reduction in the effective Schottky area results in an increase in the forward voltage rise. Therefore, in order to further reduce the forward rising voltage, it is effective to surround the electric field relaxation layer with the n region and isolate it from the p + region in order to limit the depletion layer that spreads to the electric field relaxation layer side at the time of zero bias. Become. In this case, the distance between the end of the p + region and the electric field relaxation layer which are adjacent to each other is set to be n as the p + region and the electric field relaxation layer.
The width of the current path in the forward direction is (Ws-2 ×) by setting the width of the depletion layer that spreads in the n region at zero bias when the regions are in contact with each other to about W ₂ or more.
W ₂ ) or more. However, when the distance between the end of the p + region and the electric field relaxation layer is W ₂ or more, it is necessary to appropriately adjust the distance so as not to deviate from the gist of the present invention. As a result, the forward current increases and the forward rising voltage can be lowered.

Another embodiment of the present invention based on the above technical idea will be described. FIG. 3 shows a Schottky diode which is another embodiment of the present invention. The semiconductor substrate in this example has a specific resistance of 0.002 Ω-cm and a thickness of 280 μm of n +.
A specific resistance of 0.3 is obtained by epitaxial growth on the Si substrate 4.
The n region 3 which is an epitaxial layer having an Ω-cm and an impurity concentration of 2 × 10 ¹⁶ / cm ³ is grown to a thickness of 6.5 μm. On the surface of this epitaxial substrate, p + regions 1 were formed by stripe-shaped selective diffusion so that the surface concentration was 1 × 10 ²⁰ / cm ³ . The width Wp of the p + region 1 is 2μ
m, the junction depth Lp was 2 μm, and the Schottky junction width Ws was 2 μm. Thereafter, a SiO ₂ film (not shown) is formed by patterning by projecting 0.25 μm laterally on the upper portion of the p + region 1 by plasma CVD and photolithography, and using this as a mask, ion implantation of phosphorus is performed on the exposed n region surface. By doing so, n − region 2 was formed. That is, W ₀ = 0.25 μm in FIG.
The impurity concentration of the n-region 2 is 5 × 10 ¹⁵ / cm ³ , the junction depth is 0.5 μm, and the width (width of the n-region 2 on the left and right in FIG. 3) is 1.5 μm. Al was vapor-deposited on the back surface as an ohmic electrode 8 by 1 μm and sintered.
After that, the SiO ₂ film is removed and the barrier metal 6 is formed on the entire surface.
As a result, a Ti film having a barrier height φ (B0) = 0.49 eV was deposited by 2000 Å by electron beam evaporation. The vapor-deposited Ti film was heat-treated at 350 ° C. for 15 minutes in vacuum. Finally, an Al film as a protective metal 7 was vapor-deposited in a thickness of 1 μm to protect the barrier metal. In the diode of the present embodiment, the n − region 2 for relaxing the electric field is isolated without making contact with the p + region 1, and its interval is determined by the impurity concentration of the p + region 1 and the impurity concentration of the n region 3. Since the thickness of the depletion layer is zero bias, the depletion layer extending to the electric field relaxation layer can be controlled.

As a result of evaluating the electrical characteristics of the Schottky diode of this example, the forward current density was 60 A / cm ^2.
The forward rising voltage was 0.22 V, and the reverse current at a reverse bias of 10 V was 0.18 A / cm ² . As a result, the power loss per unit area of the diode at room temperature was 15.0 W / cm ² . The reverse current density is higher than that of the above-described embodiment because the effective Schottky junction area is increased by controlling the depletion layer extending to the electric field relaxation layer.

In any of the above-described two embodiments, if a plurality of p + regions 1 and n- regions 2 are formed and arranged alternately, the depletion layer has n- regions on both left and right sides of the p + region 1. Considering the fact that it spreads in the direction of the region 2, it is effective in space efficiency at the time of integration. In addition, the thickness of the n− region 2 should be smaller than that of the p + region 1, and n
-The width of the region 2 is set to n when the bias is zero.
It is effective to make the depletion width spread from the + region 1 more than twice as large as the current path in the forward direction and reduce the forward rising voltage.

Next, in order to more clearly describe the characteristics of the diode of the present invention, the results of simulating the characteristics of the diode of the prior art and the diode of the present invention will be described. As conditions for comparison with conventional technology,
A diode for a low voltage power supply with 3.3 V output was prepared and used. If the output voltage in the power supply circuit is 3.3V,
Since the voltage applied to the diode at the time of reverse bias is considered to be about three times the output voltage, the reverse bias voltage Vr is 1
Set to 0V. Further, the breakdown voltage of the diode is set to 30 V, which is three times Vr in consideration of safety. The output current (forward current) was set to a current density Jr = 60 A / cm ⁻² so that no current would flow from the pn junction. The impurity concentration of the medium concentration layer was set to 2 × 10 ¹⁶ cm ⁻³ because the withstand voltage was 30V. The Schottky barrier height was 0.5 eV. Further, the junction depth Lp of the p + region is 2 μm, the junction width W
p was 2 μm. In the diode of the present invention, the impurity concentration of the low-concentration layer was 5 × 10 ¹⁵ cm ⁻³ , the thickness was 0.5 μm, and the simulation was performed using the Schottky junction width Ws as a parameter. Note that all these calculations were performed at room temperature.

FIG. 4 shows the prior art diode shown in FIG. 8 and the diode of the present invention shown in FIG. 1 with Ws = 2 μm.
2 is a result of simulating the electric field strength between the anode / cathode at the center of the Schottky junction in the case of, and the distance from the upper surface of the semiconductor device in the portion where the low concentration layer is formed on the horizontal axis (direction XX ′ in FIG. 1). (Distance from the upper surface of), and the vertical axis represents the electric field strength. The electric field strength of the Schottky interface under the same condition of the Schottky diode as shown in FIG. 7 is found to be 2.4 V / cm, but it is not shown in the figure. As can be seen from FIG. 4, in the conventional technique, the electric field strength at the interface is changed from 2.4 V / cm to 1.9 V / cm.
In the present invention, 1.
It was found that it could be drastically reduced to 1 V / cm.

Further, the forward rising voltage Vf and the reverse current Jr are obtained in a simulation considering the increase in series resistance due to the arrangement of the low concentration layer in FIG.
The abscissa and the ordinate are taken respectively, and the result of comparing the diode of the prior art and the diode of the present invention is shown. In the figure, the Schottky junction width Ws of the conventional diode of FIG.
Is a result of simulating the diode of the present invention similarly with Ws as a parameter. It can be seen that the diode of the present invention obtains a lower reverse current than the conventional diode.

FIG. 6 shows a plot of the Schottky junction width Ws obtained from the results shown in FIG. 5 on the horizontal axis and the power loss P _{1 of the} diode on the vertical axis. In addition, in the figure, the minimum power loss of a general Schottky diode under the same conditions is shown by a chain line. As a result, in the conventional diode shown in FIG. 8, the Schottky junction width Ws is 1 μm.
While the minimum power loss is given at about m, the diode of the present invention gives the minimum loss at about 2 μm, and it is clear that the amount of power loss is smaller than that of the conventional technique. Further, it can be seen from FIG. 6 that the dimensional range of Ws giving the minimum value of the diode loss P ₁ is narrow in the prior art, whereas that of the diode of the present invention is wide. This is
It shows that the diode of the present invention has a very high process margin.

From the above results, it can be seen that the diode of the present invention can be manufactured with less variation in its characteristics and with a design rule looser than the conventional technique.

The above-mentioned ones are p + semiconductor regions and n
-While the diode is in contact with the electric field relaxation layer, it is clear that the same effect is achieved when the electric field relaxation layer is isolated.

In this embodiment, the substrate is an n-type semiconductor, but it can be applied to a substrate which is a p-type semiconductor by appropriately setting the conditions as in the present embodiment. There is no end.

[0026]

As described above, in the diode of the present invention, in the diode having the Schottky junction and the pn junction, the low low concentration layer is formed immediately below the Schottky junction as an electric field relaxation layer, so that the low Even in the reverse bias, the expansion of the depletion layer from the pn junction and the Schottky junction is promoted, and as a result, the electric field strength at the Schottky junction interface can be effectively relaxed. Also, by enclosing and isolating the low-concentration layer with the medium-concentration layer, a more effective Schottky junction area can be secured, a high forward current density can be obtained, and an increase in the forward-direction rising voltage can be suppressed while the reverse-direction is increased. The current can be reduced. Therefore, a rectifying diode with lower loss can be provided. further,
By providing the low-concentration electric field relaxation layer, it becomes possible to operate with a low reverse bias, and the Schottky junction area can be increased. Therefore, the design rule is relaxed, the process margin is high, and the low-loss diode with high performance at low cost can be provided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is a Schottky diode manufactured using the semiconductor device of the present invention.

FIG. 3 is a Schottky diode which is another embodiment of the present invention.

FIG. 4 is a diagram showing the electric field strength between the anode / cathode at the center of the Schottky junction between the diode of the prior art and the diode of the present invention.

FIG. 5 is a diagram showing a relationship between a forward-direction rising voltage Vf and a reverse-direction current Jr of a conventional diode and a diode of the present invention.

6 is a diagram showing the relationship between the Schottky junction width Ws obtained from the results shown in FIG. 5 and the power loss P of the diode.

FIG. 7 is a cross-sectional view of a general Schottky diode.

FIG. 8 is a sectional view of a conventional Schottky diode.

[Explanation of symbols]

 1 high impurity concentration p-type semiconductor region 2 low impurity concentration n-type semiconductor region 3 medium impurity concentration n-type semiconductor region 4 high impurity concentration n-type semiconductor region 5 depletion layer 6 barrier metal 7 protective metal 8 ohmic electrode

Claims (7)

[Claims] 1. A semiconductor substrate having a medium conductivity type one conductivity type semiconductor region formed on a high impurity concentration one conductivity type semiconductor region, and at least two semiconductor substrates formed on the surface of the middle impurity concentration one conductivity type semiconductor region. In a semiconductor device having a semiconductor region of another conductivity type and a metal formed on the surface of the semiconductor substrate including the semiconductor region of the other conductivity type, a semiconductor device of one conductivity type is provided between the semiconductor regions of the other conductivity type adjacent to each other. A semiconductor device having a low impurity concentration semiconductor region. 2. The low impurity concentration semiconductor region is separated from the other conductivity type semiconductor region.
The semiconductor device described. 3. A semiconductor substrate having a one-conductivity type semiconductor region having a medium impurity concentration formed on a one-conductivity type semiconductor region having a high impurity concentration, and a plurality of other substrates formed on the surface of the one conductivity type semiconductor region having a medium impurity concentration. A conductive type semiconductor region, a plurality of one conductive type low impurity concentration semiconductor regions formed on the surface of the one conductive type semiconductor region of the medium impurity concentration, the other conductive type semiconductor region and one conductive type low impurity concentration A metal formed on the surface of the semiconductor substrate including a semiconductor region, wherein the plurality of other conductivity type semiconductor regions and the plurality of one conductivity type low impurity concentration semiconductor regions are alternately arranged. Semiconductor device. 4. The low impurity concentration semiconductor region is separated from the other conductivity type semiconductor region.
The semiconductor device described. 5. The medium impurity is formed by contact between the low conductivity semiconductor region and the other conductivity type semiconductor region when the other conductivity type semiconductor region is in contact with the medium impurity concentration one conductivity type semiconductor region when the bias is zero bias. 5. The semiconductor device according to claim 2, wherein the concentration is equal to or larger than the thickness of the depletion layer formed in the one conductivity type semiconductor region. 6. The semiconductor device according to claim 1, wherein the thickness of the low impurity concentration semiconductor region is smaller than the thickness of the other conductivity type semiconductor region. 7. The width of the low-impurity concentration semiconductor region is set to be at least twice the width of a depletion layer extending from the other-conductivity-type semiconductor region adjacent to the low-impurity concentration semiconductor region at zero bias. 7. The semiconductor device according to items 1 to 6.