CN116169157A - Gallium oxide device and preparation method thereof - Google Patents

Gallium oxide device and preparation method thereof Download PDF

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Publication number
CN116169157A
CN116169157A CN202111407950.2A CN202111407950A CN116169157A CN 116169157 A CN116169157 A CN 116169157A CN 202111407950 A CN202111407950 A CN 202111407950A CN 116169157 A CN116169157 A CN 116169157A
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substrate
laminated structure
layer
gallium oxide
single crystal
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请求不公布姓名
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Guangzhou Huarui Shengyang Investment Co ltd
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Guangzhou Huarui Shengyang Investment Co ltd
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Priority to CN202111407950.2A priority Critical patent/CN116169157A/en
Priority to PCT/CN2022/122471 priority patent/WO2023093294A1/en
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Abstract

The invention provides a gallium oxide device and a preparation method thereof. In one embodiment of the invention, a heterogeneous substrate such as a silicon (111) surface substrate is adopted to prepare a laminated structure with excellent crystallinity and containing a gallium oxide semiconductor layer, then the laminated structure and the substrate are subjected to etching treatment by photoetching, etching and other technologies to form a through-substrate effect, and an electrode layer is deposited in a through-substrate area, so that the lower surface of the laminated structure containing the gallium oxide layer is directly electrically connected with the electrode layer, and a vertical gallium oxide device can be prepared. The device structure is designed without heterogeneous buffer layers, so that lattice mismatch and thermal mismatch during lamination of different materials can be reduced, device loss is reduced, and the electrical performance and reliability of the device are improved.

Description

Gallium oxide device and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor devices and manufacturing, and particularly relates to a gallium oxide device and a preparation method thereof.
Background
Gallium oxide (Ga) 2 O 3 ) As a semiconductor material with ultra-wide forbidden band, the forbidden band width is between 4.7 and 5.3eV, and the advantages in the aspects of breakdown field intensity, on-resistance, bargain figure of merit, cost and the like are outstanding. Can be used for manufacturing high-performance power electronic devices, ultraviolet sensors and the like, and has wide and expected application prospect.
Gallium oxide (Ga) 2 O 3 ) Has five phases of alpha, beta, gamma, delta and epsilon, and is mainly researched around the alpha phase, the epsilon phase and the beta phase in the field of semiconductor application, wherein beta-Ga 2 O 3 The single inclined crystal structure is the most stable, and the forbidden bandwidth is about 4.8eV; alpha-Ga 2 O 3 The crystal structure is hexagonal, the stability is inferior, and the forbidden band width is about 5.3eV; in addition, according to the data, alpha-Ga 2 O 3 Having a specific beta-Ga 2 O 3 Higher carrier mobility. Based on these characteristics, alpha-Ga 2 O 3 Is more suitable for being applied to semiconductor devices.
Currently, beta-Ga 2 O 3 beta-Ga requiring monoclinic system 2 O 3 The substrate is homoepitaxial to prepare high-quality beta-Ga 2 O 3 A single crystal thin film; however, currently beta-Ga 2 O 3 The substrate is small in size and high in cost, and beta-Ga 2 O 3 The thermal conductivity of the material is low, and the factors severely restrict the beta-Ga 2 O 3 Is a commercial process of (a).
α-Ga 2 O 3 With hexagonal symmetry, can be grown on a substrate with hexagonal symmetry structure, and patent application document CN106415845A discloses a crystal excellent alpha-Ga 2 O 3 Laminated structure and corresponding semiconductor device using sapphire as alpha-Ga 2 O 3 A substrate for growth. While sapphire substrates also have hexagonal symmetry, sapphire materials are insulators and are inferior to silicon material substrates in price, size, thermal conductivity.
Patent application CN110085658A discloses a laminated structure for realizing high quality gallium oxide semiconductor thin film on a silicon substrate and a corresponding preparation method. The laminated structure is formed by sequentially superposing a silicon substrate, a nitride insertion layer and a gallium oxide semiconductor layer. An α -Ga2O3 or epsilon-Ga 2O3 layered structure having excellent crystallinity is produced on a silicon (111) plane substrate by a nitride insertion layer (also referred to as a buffer layer). However, for a stacked structure in which a silicon substrate, a nitride insertion layer, and a gallium oxide semiconductor layer are stacked in this order, although they all have a hexagonal symmetrical structure, they are stacked between different materials (i.e., stacked by heteroepitaxy), lattice mismatch and thermal mismatch still exist, which affects the electrical performance and reliability of a semiconductor device fabricated based on the stacked structure.
Disclosure of Invention
In view of the above, the invention provides a gallium oxide device and a preparation method thereof, which solve the problems of lattice mismatch and thermal mismatch of the gallium oxide device prepared by heteroepitaxy.
According to the first aspect of the invention, the technical scheme of the gallium oxide device is as follows:
a gallium oxide device, comprising:
The substrate is a monocrystalline substrate with a hexagonal symmetrical structure, and is provided with a through hole;
the laminated structure is positioned on the surface of the upper surface of the substrate, at least comprises a gallium oxide semiconductor layer, and the cross section shape of the laminated structure is within the cross section shape of the through hole at the position of the surface of the lower surface of the laminated structure;
a first electrode layer located on the upper surface of the laminated structure;
a second electrode layer located in the through hole and contacting with the lower surface of the laminated structure;
and the insulating protection layer is covered on the surface of the substrate, the second electrode, the laminated structure and the first electrode layer, which is positioned on one side of the upper surface of the substrate, and a partial area is left on the upper surface of the first electrode layer to be in an exposed state.
Preferably, the single crystal substrate having a hexagonal symmetry structure is a silicon (111) plane substrate, a silicon carbide substrate, a sapphire substrate, or an aluminum nitride substrate.
Preferably, the gallium oxide is alpha-Ga 2 O 3 、ε-Ga 2 O 3 Or beta-Ga 2 O 3 。
Preferably, the gallium oxide device is a schottky barrier diode, a pn junction diode, a metal oxide semiconductor field effect transistor, an insulated gate bipolar transistor, a thyristor, an electrostatic induction transistor, a junction field effect transistor, a metal semiconductor field effect transistor, or a light emitting diode.
According to a second aspect of the invention, a technical scheme of a preparation method of a gallium oxide device is provided as follows:
a method of fabricating a gallium oxide device, comprising the steps of:
s101, providing a single crystal substrate with a hexagonal symmetrical structure;
s102, forming a nitride single crystal film on the upper surface of the substrate;
s103, forming a laminated structure on the upper surface of the nitride single crystal film layer, wherein the laminated structure at least comprises a gallium oxide semiconductor layer;
s104, removing part of the nitride single crystal film and the laminated structure;
s105, forming an insulating protective layer on the substrate, the nitride single crystal film and the surface of the laminated structure on one side of the upper surface of the substrate;
s106, forming a through hole on the lower surface of the substrate along the thickness direction of the substrate, wherein the through hole extends to expose the lower surface of the laminated structure, and the cross section shape of the laminated structure is within the cross section shape of the through hole at the position of the surface of the lower surface of the laminated structure;
s107, forming a second electrode layer in the through hole, wherein the second electrode layer is contacted with the lower surface of the laminated structure;
After any of steps S105 to S107, the insulating protective layer is removed from a part or all of the upper surface of the laminated structure, and a first electrode layer is formed over the exposed laminated structure.
As an equivalent replacement for the preparation method of the gallium oxide device, the technical scheme is as follows:
a method of fabricating a gallium oxide device, comprising the steps of:
s101, providing a single crystal substrate with a hexagonal symmetrical structure;
s102, forming a nitride single crystal film on the upper surface of the substrate;
s103, sequentially forming a laminated structure and a first electrode layer on the upper surface of the nitride single crystal film layer, wherein the laminated structure at least comprises a gallium oxide semiconductor layer;
s104, removing part of the nitride single crystal film, the laminated structure and the first electrode layer;
s105, forming an insulating protective layer on the substrate, the nitride single crystal film, the laminated structure and the surface of the first electrode layer on one side of the upper surface of the substrate;
s106, forming a through hole on the lower surface of the substrate along the thickness direction of the substrate, wherein the through hole extends to expose the lower surface of the laminated structure, and the cross section shape of the laminated structure is within the cross section shape of the through hole at the position of the surface of the lower surface of the laminated structure;
S107, forming a second electrode layer in the through hole, wherein the second electrode layer is contacted with the lower surface of the laminated structure;
after any step S104 to S107, the insulating protection layer in the partial area of the upper surface of the first electrode layer is removed, and part or all of the first electrode layer is exposed.
Preferably, the nitride lattice structure is a hexagonal symmetrical structure.
Preferably, the nitride is an alloy formed by one or more of aluminum nitride, gallium nitride and indium nitride.
Compared with the prior art, the invention has the following beneficial effects:
(1) The invention can prepare the nitride single crystal film layer and the gallium oxide semiconductor layer with excellent crystallinity by utilizing a heterogeneous substrate such as a silicon (111) surface substrate, then completely removes the nitride single crystal film layer (namely the nitride insertion layer mentioned in the background art) by photoetching, etching and other technologies, and locally removes the substrate to form a substrate through hole effect, so that the lower surface of the gallium oxide semiconductor layer is directly electrically connected with the electrode layer without establishing electrical connection between the substrate and the nitride single crystal film layer. Compared with the laminated structure of a silicon substrate layer, a nitride single crystal film layer and a gallium oxide semiconductor layer which are sequentially arranged in the prior art, the scheme of the invention can reduce lattice mismatch and thermal mismatch among different materials, thereby reducing device loss and improving the electrical performance and reliability of a gallium oxide device.
(2) Compared with the laminated structure of a silicon substrate layer, a nitride single crystal film layer and a gallium oxide semiconductor layer which are sequentially arranged in the prior art, the gallium oxide semiconductor layer can be directly connected with an electrode layer, so that the thermal resistance can be reduced, and the radiating effect can be greatly improved.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the following description will be given by way of brief introduction to the drawings used in the examples or the description of the prior art, it being apparent that the drawings in the following description are only some examples of the present invention, and the scope of protection claimed by the present invention is not limited to the examples. Other figures may be derived from these figures without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of one suitable example of a Schottky Barrier Diode (SBD) of the present invention;
fig. 2 is a schematic diagram of one suitable example of a pn junction diode of the present invention;
FIG. 3 is a schematic diagram of one suitable example of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) of the present invention;
fig. 4 is a schematic diagram of one suitable example of an Insulated Gate Bipolar Transistor (IGBT) of the invention;
Fig. 5 is a schematic diagram of another suitable example of a Schottky Barrier Diode (SBD) of the present invention;
fig. 6 is a schematic diagram of one suitable example of a pin diode of the present invention;
fig. 7-1 through 7-11 are flow charts of a portion of the process for fabricating the Schottky Barrier Diode (SBD) of fig. 1 in accordance with the present invention;
FIGS. 8-1 through 8-11 are flow charts of a portion of the process for fabricating the Schottky Barrier Diode (SBD) of FIG. 5 in accordance with the present invention;
the technical characteristics corresponding to the marks in the drawings are as follows:
101. monocrystalline silicon substrate
102a lightly doped n-type alpha-Ga 2 O 3 Semiconductor layer
102b heavily doped n+ alpha-Ga 2 O 3 Semiconductor layer
102b1 first heavily doped n+ alpha-Ga 2 O 3 Semiconductor layer
102b2 second heavily doped n+ alpha-Ga 2 O 3 Semiconductor layer
102 n-type alpha-Ga 2 O 3 Semiconductor layer
103a lightly doped p-type alpha-Ga 2 O 3 Semiconductor layer
103b heavily doped p+ alpha-Ga 2 O 3 Semiconductor layer
1031. First p-type alpha-Ga 2 O 3 Semiconductor layer
1032. Second p-type alpha-Ga 2 O 3 Semiconductor layer
104. Gate insulating layer
105a anode metal layer
105b cathode metal layer
107. Insulating protective layer
108. Polysilicon layer
109a source electrode
109b drain electrode
109c gate electrode
110a gate electrode
110b collector
110c emitter
112a n-beta-Ga 2 O 3 Semiconductor layer
112b n + beta-Ga 2 O 3 Semiconductor layer
106a GaN single crystal film layer
106b β-Ga 2 O 3 Film layer (GaN oxidation conversion)
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
First embodiment
The present embodiment provides a gallium oxide device including:
the substrate is a single crystal substrate with a hexagonal symmetrical structure and is provided with a through hole;
a laminated structure located above the surface of the upper surface of the substrate, the laminated structure including at least a gallium oxide semiconductor layer, the laminated structure having a cross-sectional shape within the cross-sectional shape of the through-hole at the surface of the lower surface of the laminated structure;
a first electrode layer located on the upper surface of the laminated structure;
a second electrode layer located in the through hole and contacting the lower surface of the laminated structure;
And the insulating protection layer is covered on the substrate, the second electrode, the laminated structure and the surface of the first electrode layer, which is positioned on one side of the upper surface of the substrate, wherein a partial area is left on the upper surface of the first electrode layer and is in an exposed state.
The substrate is a clean single crystal wafer for growing epitaxial layers having specific crystal planes and appropriate electrical, optical and mechanical properties, and the semiconductor devices of the prior art are generally fabricated by stacking a laminate structure on the surface of the substrate, which serves not only as an electrical property but also as a mechanical support.
The substrate of the invention is a monocrystal substrate with a hexagonal symmetry structure, the material has the characteristics that a monocrystal formed by the material has hexagonal symmetry or a certain section of the monocrystal formed by the material has hexagonal symmetry, and the reason that the substrate material of the type is selected is that the hexagonal symmetrical monocrystal substrate is used for extending a hexagonal symmetrical semiconductor layer, so that the lattice matching degree is high, and the quality of a monocrystal film is good.
Preferably, the single crystal substrate having a hexagonal symmetrical structure is a silicon (111) plane substrate, a silicon carbide substrate, a sapphire substrate, or an aluminum nitride substrate.
The laminated structure is a key component of device functions and can comprise multiple layers, the specific layer number can be designed according to the device type and performance requirements, and the laminated structure at least comprises a gallium oxide semiconductor layer, and the material has the characteristics of ultra-wide forbidden band of 4.7-5.35 eV and has remarkable advantages in indexes such as breakdown field strength, on-resistance, barre plus figure of merit and the like. The power device manufactured by the material of the type can be made thinner, the breakdown field intensity is higher, and the barre figure of merit is higher. The epitaxial gallium oxide film layer with the homogeneous substrate is adopted, so that the lattice mismatch and thermal mismatch phenomena are avoided, and the epitaxial layer with better film quality can be prepared. However, gallium oxide homosubstrates also suffer from a number of problems, α -Ga 2 O 3 Substrate and epsilon-Ga 2 O 3 The substrate is not prepared by the available technology at present. beta-Ga 2 O 3 The substrate can already be manufactured in such a way that,but the size of the substrate is small, the cost is high, and the beta-Ga 2 O 3 The thermal conductivity of the material is very low. Therefore, the gallium oxide thin film layer is prepared by epitaxy through the heterogeneous substrate, however, the lattice mismatch and the thermal mismatch of the gallium oxide device prepared by heteroepitaxy are solved, the substrate penetrating structure is skillfully utilized, and the nitride single crystal thin film layer serving as the buffer layer is completely removed, so that the lower surface of the gallium oxide semiconductor layer is not required to be electrically connected with the electrode layer through the nitride thin film layer and the substrate, but is directly electrically connected with the electrode layer, and the lattice mismatch and the thermal mismatch of the gallium oxide device prepared by heteroepitaxy are well solved.
Preferably, the gallium oxide is alpha-Ga 2 O 3 、ε-Ga 2 O 3 Or beta-Ga 2 O 3 Wherein alpha-Ga 2 O 3 、ε-Ga 2 O 3 Crystal structure with hexagonal symmetry, beta-Ga 2 O 3 A crystal structure having monoclinic symmetry.
It should be noted that the material of a certain cross-sectional area of the stacked structure in the thickness direction of the gallium oxide device is not required to be identical, for example, for a metal oxide semiconductor field effect transistor (MOS), the certain cross-sectional area of the stacked structure in the thickness direction of the semiconductor device may have a semiconductor material, a polysilicon material, and an insulating material at the same time.
The first electrode layer and the second electrode layer serve as electrodes of the semiconductor device and serve as electrodes for electrical connection with the outside, and it should be noted that the first electrode layer and the second electrode layer may be divided into a plurality of portions, for example, for a MOS transistor, the first electrode layer may be divided into a source electrode and two gate electrodes.
The purpose of the added insulating protective layer is to enhance the withstand voltage capability of the device, and in addition, the insulating protective layer in the present invention also serves to bridge the substrate and the laminated structure together.
The method adopted by the laminated structure on the surface where the upper surface of the substrate is located is that firstly, a nitride single crystal film layer is formed on the upper surface of the substrate, then a laminated structure containing a gallium oxide semiconductor layer is formed on the nitride single crystal film layer, the most preferred substrate is a silicon (111) plane single crystal substrate, because the laminated structure containing the gallium oxide semiconductor layer is prepared and formed, an oxygen environment is needed, however, silicon is extremely easy to oxidize and form silicon oxide in the oxygen environment, the quality of the gallium oxide film directly prepared by the silicon substrate is poor, therefore, the nitride film layer with a hexagonal symmetrical structure needs to be prepared on the surface of the silicon substrate before the gallium oxide is prepared, then the nitride single crystal film layer is used for preparing and forming the gallium oxide film layer, then part of the nitride single crystal film and the laminated structure are removed, a through hole is formed on the surface of the substrate, the nitride single crystal film and the surface of the laminated structure on one side of the upper surface of the substrate, then a through hole is formed on the lower surface of the substrate along the thickness direction, the through hole needs to extend to the second electrode exposed to the lower surface of the second electrode, and the second electrode is formed and finally, the through hole is contacted with the second electrode layer is formed on the lower surface of the semiconductor.
The nitride in the nitride single crystal film layer is preferably in a hexagonal symmetry structure, and further can be an alloy formed by one or more of aluminum nitride, gallium nitride and indium nitride, wherein the aluminum nitride, the gallium nitride and the indium nitride are all materials with hexagonal symmetry structures and are matched with alpha-Ga with hexagonal symmetry structures 2 O 3 ，ε-Ga 2 O 3 The lattice matching degree of (2) is good.
The generation of the first electrode includes two ways: firstly, after an insulating protective layer is generated, removing the insulating protective layer in part or all areas of the upper surface of the laminated structure, and forming a first electrode layer on the exposed laminated structure; the second is to form the first electrode immediately after the formation of the laminated structure, and then to cover the first electrode after the formation of the insulating protective layer, so that it is necessary to leak part or all of the first electrode on the exposed laminated structure by removing part of the insulating protective layer.
The cross-sectional shape of the laminated structure needs to be within the cross-sectional shape of the through-hole at the surface where the lower surface of the laminated structure is located, so that the laminated structure is isolated from the substrate.
In addition, the nitride single crystal thin film layer is entirely removed when the through hole extends to expose the lower surface of the stacked structure, and thus no nitride single crystal thin film layer appears in the gallium oxide device of the present invention.
As shown in fig. 1, a Schottky Barrier Diode (SBD) according to the present invention is a first example.
The schottky barrier diode of fig. 1 has a substrate of silicon 101, and a stacked structure comprising lightly doped n-type alpha-Ga 2 O 3 Semiconductor layer 102a and heavily doped n+ -type alpha-Ga 2 O 3 The semiconductor layer 102b, the first electrode layer is an anode metal layer 105a, the second electrode layer is a cathode metal layer 105b, and the insulating protection layer is an insulating protection layer 107; the silicon substrate 101 in fig. 1 has a through hole; lightly doped n-type alpha-Ga 2 O 3 Semiconductor layer 102a and heavily doped n+ -type alpha-Ga 2 O 3 The stacked structure of the semiconductor layers 102b is located above the surface of the upper surface of the silicon substrate 101, and the cross-sectional shape of the stacked structure is within the cross-sectional shape of the through hole at the surface of the lower surface of the stacked structure; the anode metal layer 105a is located on the upper surface of the laminated structure; the cathode metal layer 105b is located in the through hole and is in contact with the lower surface of the laminated structure; an insulating protective layer 107 covers the silicon substrate 101, the cathode metal layer 105b, and the lightly n-doped alpha-Ga 2 O 3 Semiconductor layer 102a, heavily doped n+ alpha-Ga 2 O 3 The semiconductor layer 102b and the anode metal layer 105a are located above the surface of the upper surface side of the silicon substrate 101, and wherein a partial area is left on the upper surface of the anode metal layer 105a in an exposed state.
In which n-type alpha-Ga is lightly doped 2 O 3 The semiconductor layer 102a plays a role in forward current transmission and reverse withstand voltage blocking; heavily doped n+ -type alpha-Ga 2 O 3 The semiconductor layer 102b plays a role in current transmission; the anode metal layer 105a and the cathode metal layer 105b function to be electrically connected to the outside.
In FIG. 1, the light weightN-doped alpha-Ga 2 O 3 Semiconductor layer 102a, heavily doped n+ -type α -Ga 2 O 3 The formation of the semiconductor layer 102b can be performed by a known method such as Metal Organic Chemical Vapor Deposition (MOCVD), halide Vapor Phase Epitaxy (HVPE), or Mist CVD (Mist-CVD);
in fig. 1, the anode metal layer 105a and the cathode metal layer 105b may be made of a known electrode material, for example: al, mo, co, zr, sn, nb, fe, cr, ta, ti, au, pt, V, mn, ni, cu, hf, W, ir, zn, in, pd, nd or Ag or other metals or their alloys; a metal oxide conductive film such as tin oxide, zinc oxide, indium tin oxide, and zinc indium oxide; organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures thereof;
in fig. 1, the anode metal layer 105a and the cathode metal layer 105b are formed by a known method such as a vacuum deposition method, a sputtering method, or a metal CVD method. More specifically, when forming the anode metal layer, a layer made of platinum (Pt) and a layer made of aluminum (Al) may be laminated;
The Schottky Barrier Diode (SBD) of fig. 1, in which the current is able to be conducted vertically, allows the cathode metal layer 105b to be directly connected to heavily doped n + type alpha-Ga by providing a via in the substrate 2 O 3 The semiconductor layer 102b forms an ohmic connection. Compared with the Schottky barrier diode prepared on the basis of a laminated structure of a silicon substrate, a nitride single crystal film layer and a gallium oxide layer which are sequentially arranged in the prior art, the structural design of the structure shown in the figure 1 can reduce lattice mismatch and thermal mismatch, reduce loss and improve the electrical performance and reliability of the diode; the insulating protection layer 107 with the surface covered can play a good role in insulating protection; meanwhile, heat generated during the working of the Schottky barrier diode can be directly conducted out from the metal electrode layers at the two ends of the top and the bottom of the device without passing through the substrate layer, so that the heat dissipation effect of the device is greatly improved.
Second embodiment
The present embodiment is different from the first embodiment in that an example of a pn junction diode according to the present invention is given, and as shown in fig. 2, an example of a pn junction diode according to the present invention is given.
The pn junction diode of fig. 2 differs from the schottky barrier diode of fig. 1 in that the p-type alpha-Ga will be lightly doped in fig. 2 2 O 3 Semiconductor layer 103a replaces the lightly doped n-type alpha-Ga of fig. 1 2 O 3 Semiconductor layer 102a, lightly doped p-type alpha-Ga 2 O 3 The semiconductor layer 103a is an essential component of a pn junction diode, and is heavily doped with n+ -type α -Ga 2 O 3 The semiconductor layer 102b constitutes a pn junction having a function of forward turn-on and reverse turn-off, so that the structure shown in fig. 2 is applicable to a pn junction diode.
Based on the foregoing description, one skilled in the art can readily derive that the pn junction diode of the present embodiment has many advantages, briefly summarized as: (1) Lattice mismatch and thermal mismatch can be reduced, loss is reduced, and the electrical performance and reliability of the diode are improved; (2) good insulation property; (3) good heat dissipation effect.
Third embodiment
This embodiment is different from the first embodiment in that an example of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) according to the present invention is given, and as shown in fig. 3, an example of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) according to the present invention is given.
The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) of fig. 3, the substrate being a silicon substrate 101, the stacked structure comprising a first heavily doped n + type alpha-Ga 2 O 3 Semiconductor layer 102b1, lightly doped p-type alpha-Ga 2 O 3 Semiconductor layer 103a, second heavily doped n+ -type α -Ga 2 O 3 The semiconductor layer 102b2, the polysilicon layer 108, and the gate insulating layer 104, the first electrode layer includes a source electrode 109a and two gate electrodes 109c, the second electrode layer is a drain electrode 109b, and the insulating protective layer is an insulating protective layer 107.
The silicon substrate 101 in fig. 3 has a through hole; first heavily doped n+ type alpha-Ga 2 O 3 Semiconductor layer 102b1, lightly doped p-type alpha-Ga 2 O 3 Semiconductor layer 103a, second heavy dopingn+ alpha-Ga 2 O 3 A stacked structure in which the semiconductor layer 102b2, the polysilicon layer 108, and the gate insulating layer 104 are stacked is located above the surface where the upper surface of the silicon substrate 101 is located, and the cross-sectional shape of the stacked structure is within the cross-sectional shape of the via hole at the surface where the lower surface of the stacked structure is located; a source electrode 109a and two gate electrodes 109c are located on the upper surface of the stacked structure; the drain electrode 109b is located in the through hole and is in contact with the lower surface of the laminated structure; the insulating protective layer 107 covers the silicon substrate 101, the drain electrode 109b, the stacked structure, the source electrode 109a, and the two gate electrodes 109c over the surface on the upper surface side of the silicon substrate 101, and wherein the upper surfaces of the source electrode 109a and the two gate electrodes 109c leave partial areas in an exposed state.
Wherein the stacking mode of the stacking structure is alpha-Ga of a first heavily doped n+ type 2 O 3 Semiconductor layer 102b1, lightly doped p-type alpha-Ga 2 O 3 Semiconductor layer 103a and second heavily doped n+ -type alpha-Ga 2 O 3 The semiconductor layer 102b2 is stacked from bottom to top to form a raised pattern, lightly doped p-type alpha-Ga 2 O 3 The shape of the lower surface of the semiconductor layer 103a and the first heavily doped n+ -Ga 2 O 3 The upper surface of the semiconductor layer 102b1 has the same shape and is lightly doped with p-type alpha-Ga 2 O 3 The shape of the upper surface of the semiconductor layer 103a and the second heavily doped n+ -Ga 2 O 3 The lower surface of the semiconductor layer 102b2 has the same shape, the polysilicon layer 108 is divided into left and right portions, recesses on the left and right sides of the "convex" are filled, and the gate insulating layer 104 is isolated from the surfaces of the polysilicon layers 108 in contact with the recesses.
Wherein the first heavily doped n+ type alpha-Ga 2 O 3 The semiconductor layer 102b1 functions to transmit current; lightly doped p-type alpha-Ga 2 O 3 The semiconductor layer 103a functions to form a channel and transmit current; second heavily doped n+ -type alpha-Ga 2 O 3 The semiconductor layer 102b2 functions to transmit current; the source electrode 109a, the two gate electrodes 109c, and the drain electrode 109b function to be electrically connected to the outside.
The polysilicon layer 108 functions to achieve heavy doping by ion implantation of polysilicon, making it a good conductor of electricity. And the effect of the threshold voltage of the MOS tube can be regulated by regulating the doping concentration of the MOS tube.
The gate insulating layer 104 functions to enable each polysilicon layer 108 to be doped with lightly p-type alpha-Ga 2 O 3 Semiconductor layer 103a and second heavily doped n+ -type alpha-Ga 2 O 3 The semiconductor layer 102b2 realizes isolation, thereby functioning as electrical insulation.
The mosfet of fig. 3 has drain electrode 109b directly connected to the first heavily doped n+ -Ga 2 O 3 The lower surface of the semiconductor layer 102b1 is electrically connected. Compared with the metal oxide semiconductor field effect transistor prepared based on the laminated structure of the silicon substrate, the nitride single crystal film layer and the gallium oxide layer which are sequentially arranged in the prior art, the structural design of the figure 3 can reduce lattice mismatch and thermal mismatch and improve the electrical performance and reliability of the metal oxide semiconductor field effect transistor; meanwhile, heat generated during the operation of the metal oxide semiconductor field effect transistor does not need to pass through the substrate layer, and can be directly conducted out of the metal electrode layers at the top and bottom ends of the device, so that the heat dissipation effect of the device is greatly improved.
Fourth embodiment
The present embodiment is different from the first embodiment in that an example of an Insulated Gate Bipolar Transistor (IGBT) according to the present invention is given, and as shown in fig. 4, an example of an Insulated Gate Bipolar Transistor (IGBT) according to the present invention is given.
Fig. 4 shows an Insulated Gate Bipolar Transistor (IGBT) having a silicon substrate 101, and a stacked structure including a first p-type α -Ga 2 O 3 Semiconductor layer 1031, n-type alpha-Ga 2 O 3 Semiconductor layer 102, lightly doped n-type alpha-Ga 2 O 3 Semiconductor layer 102a, heavily doped n+ alpha-Ga 2 O 3 Semiconductor layer 102b, second p-type alpha-Ga 2 O 3 A semiconductor layer 1032 and a gate insulating layer 104, the first electrode layer including a gate electrode 110a and two emitters 110c, the second electrode layer being a collector 110b, the insulating protective layer being an insulating protective layer107。
The silicon substrate 101 in fig. 4 has a through hole; first p-type alpha-Ga 2 O 3 Semiconductor layer 1031, n-type alpha-Ga 2 O 3 Semiconductor layer 102, lightly doped n-type alpha-Ga 2 O 3 Semiconductor layer 102a, heavily doped n+ alpha-Ga 2 O 3 Semiconductor layer 102b, second p-type alpha-Ga 2 O 3 A stacked structure in which the semiconductor layer 1032 and the gate insulating layer 104 are stacked is located above the surface where the upper surface of the silicon substrate 101 is located, and the cross-sectional shape of the stacked structure is within the cross-sectional shape of the through hole where the lower surface of the stacked structure is located; a gate electrode 110a and two emitters 110c are located on the upper surface of the stacked structure; the collector 110b is located in the through hole and is in contact with the lower surface of the stacked structure; the insulating protective layer 107 covers the silicon substrate 101, the collector 110b, the stacked structure, the gate electrode 110a, and the surfaces of the two emitters 110c on the upper surface side of the silicon substrate 101, and wherein the upper surfaces of the gate electrode 110a and the two emitters 110c leave partial areas in an exposed state.
Wherein the stacking mode of the stacked structure is a first p-type alpha-Ga 2 O 3 Semiconductor layer 1031, n-type alpha-Ga 2 O 3 Semiconductor layer 102, lightly doped n-type alpha-Ga 2 O 3 The semiconductor layer 102a is stacked from bottom to top to form a raised pattern, n-type alpha-Ga 2 O 3 The shape of the lower surface of the semiconductor layer 102 and the first p-type alpha-Ga 2 O 3 The upper surface of the semiconductor layer 1031 has the same shape, n-type alpha-Ga 2 O 3 The shape of the upper surface of the semiconductor layer 102 and lightly doped n-type alpha-Ga 2 O 3 The lower surface of the semiconductor layer 102a has the same shape and is heavily doped with n+ -type α -Ga 2 O 3 The semiconductor layer 102b is divided into left and right parts, the recesses on the left and right sides of the "convex" are filled with the semiconductor layer, and the gate insulating layer 104 is formed by heavily doping n+ -type α -Ga 2 O 3 The semiconductor layer 102b is isolated from the surface contacting each recess, and the second p-type alpha-Ga 2 O 3 The semiconductor layer 1032 is located on the upper surface of the "convex" shape, and the cross-sectional area shape falls between the cross-sectional area of the lower half and the cross-sectional area of the upper half of the "convex" shape, so that in the laminated structureRecesses are formed on the left and right sides, and a part of each of the two gate electrodes 109c is located in the recess.
Wherein the first p-type alpha-Ga 2 O 3 The semiconductor layer 1031 functions as a substrate, provides hole carriers, and functions to transport current; n-type alpha-Ga 2 O 3 The semiconductor layer 102 functions to provide electron carriers to transport current; lightly doped n-type alpha-Ga 2 O 3 The semiconductor layer 102a functions to supply electron carriers and transport current; heavily doped n+ -type alpha-Ga 2 O 3 The semiconductor layer 102b functions to supply electron carriers and transport current; second p-type alpha-Ga 2 O 3 The function of semiconductor layer 1032 is to provide hole carriers for transporting current; the gate insulating layer 104 functions to isolate the gate electrode 110a from the semiconductor layer under the gate insulating layer 104, achieving electrical insulation.
The IGBT of FIG. 4 has collector 110b directly connected to the first p-type alpha-Ga 2 O 3 The lower surface of the semiconductor layer 1031 is electrically connected. Compared with the IGBT prepared on the basis of the laminated structure of the silicon substrate, the nitride single crystal film layer and the gallium oxide layer which are sequentially arranged in the prior art, the structural design of the figure 4 can reduce lattice mismatch and thermal mismatch and improve the electrical performance and reliability of the IGBT; meanwhile, heat generated during the operation of the IGBT is not required to pass through the substrate layer and the nitride layer, and can be directly conducted out from the metal electrode layers at the two ends of the top and the bottom of the device, so that the heat dissipation effect of the device is greatly improved.
Fifth embodiment
This embodiment is different from the first embodiment in that a second example of the Schottky Barrier Diode (SBD) according to the present invention is given, and as shown in fig. 5, the second example of the Schottky Barrier Diode (SBD) according to the present invention is given.
The schottky barrier diode of fig. 5 differs from the schottky barrier diode shown in fig. 1 in that: in FIG. 5, lightly doped n-type beta-Ga is used 2 O 3 The semiconductor layer 112a replaces the lightly doped n-type alpha-Ga of fig. 1 2 O 3 A semiconductor layer 102a heavily doped with n+ -type beta-Ga 2 O 3 Semiconductor deviceLayer 112b replaces heavily doped n + type alpha-Ga of fig. 1 2 O 3 A semiconductor layer 102b.
The schottky barrier diode of fig. 5 is realized by preparing a GaN single crystal thin film layer by using a silicon (111) surface substrate, and then locally oxidizing the GaN thin film layer from top to bottom to convert into monoclinic beta-Ga 2 O 3 Thin film layer forming silicon substrate +GaN +beta-Ga 2 O 3 Is a laminated structure of (a) and (b). Then re-using the beta-Ga formed by oxidation 2 O 3 Thin films are subjected to homoepitaxy to prepare heavily doped n+ beta-Ga respectively 2 O 3 Semiconductor layer 112b and lightly doped n-type beta-Ga 2 O 3 A semiconductor layer 112a. Removing GaN film layer and beta-Ga converted from GaN oxidation at the same time of forming through hole on substrate 2 O 3 Thin film layer such that cathode metal layer 105b is directly aligned with homoepitaxially prepared n+ beta-Ga 2 O 3 The semiconductor layer 112b is in electrical contact.
Based on the foregoing description, one skilled in the art can readily derive that the schottky barrier diode of the present embodiment has many advantages, briefly summarized as: (1) Lattice mismatch and thermal mismatch can be reduced, loss is reduced, and the electrical performance and reliability of the diode are improved; (2) good insulation property; (3) good heat dissipation effect.
Sixth embodiment
This embodiment is different from the first embodiment in that an example of the pin junction diode according to the present invention is given, and as shown in fig. 6, an example of the pin junction diode according to the present invention is given.
The pin junction diode of fig. 6 differs from the structure shown in fig. 1 in that the stacked structure comprises 3 layers, i.e. in a lightly doped n-type alpha-Ga 2 O 3 The semiconductor layer 102a is also provided with a layer of heavily doped p+ -type alpha-Ga 2 O 3 A semiconductor layer 103b; in conventional pn junction diodes, one pole of the pn junction must be lightly doped to obtain a high blocking voltage, e.g., a pn junction formed by heavily doped p+ type semiconductor layer and lightly doped n-type semiconductor layer, i.e., by lightly doping one side of the n-type semiconductor, butAn important problem with this design is that the lightly doped n-type semiconductor layer and the metal connection create a large contact resistance, which is unacceptable in high current density power semiconductors. The solution adopted in this embodiment is to add a heavily doped n+ type semiconductor layer on the other side of the lightly doped n-type semiconductor layer of the pn junction to form a p+n-n+ structure, and realize low contact resistance when metal connection is performed by heavily doping the n+ type semiconductor layer, so that the structure shown in fig. 6 is suitable for a pin junction diode.
Seventh embodiment
The preparation method of the gallium oxide device in the embodiment comprises the following steps:
s101, providing a single crystal substrate with a hexagonal symmetrical structure;
s102, forming a nitride single crystal film on the upper surface of a substrate;
s103, forming a laminated structure on the upper surface of the nitride single crystal thin film layer, wherein the laminated structure at least comprises a gallium oxide semiconductor layer;
s104, removing part of the nitride single crystal film and the laminated structure;
s105, forming an insulating protective layer on the substrate, the nitride single crystal film and the surface of the laminated structure on one side of the upper surface of the substrate;
s106, forming a through hole on the lower surface of the substrate along the thickness direction of the substrate, wherein the through hole extends to expose the lower surface of the laminated structure, and the cross section shape of the laminated structure is within the cross section shape of the through hole at the position of the lower surface of the laminated structure;
s107, forming a second electrode layer in the through hole, wherein the second electrode layer is contacted with the lower surface of the laminated structure;
after any of steps S105 to S107, the insulating protective layer is removed in a part or the whole area of the upper surface of the laminated structure, and a first electrode layer is formed over the exposed laminated structure.
In the method for manufacturing the gallium oxide device, the first electrode is formed by removing the insulating protection layer in part or all of the upper surface of the laminated structure after the insulating protection layer is formed, and the first electrode layer is formed on the exposed laminated structure.
The first electrode may be formed by forming the stacked structure immediately after forming the insulating protective layer, where the first electrode is covered after forming the insulating protective layer, so that part or all of the first electrode needs to be leaked on the exposed stacked structure by removing part of the insulating protective layer.
S101, providing a single crystal substrate with a hexagonal symmetrical structure;
s102, forming a nitride single crystal film on the upper surface of a substrate;
s103, sequentially forming a laminated structure and a first electrode layer on the upper surface of the nitride single crystal film layer, wherein the laminated structure at least comprises a gallium oxide semiconductor layer;
s104, removing part of the nitride single crystal film, the laminated structure and the first electrode layer;
s105, forming an insulating protective layer on the substrate, the nitride single crystal film, the laminated structure and the surface of the first electrode layer on one side of the upper surface of the substrate;
s106, forming a through hole on the lower surface of the substrate along the thickness direction of the substrate, wherein the through hole extends to expose the lower surface of the laminated structure, and the cross section shape of the laminated structure is within the cross section shape of the through hole at the position of the lower surface of the laminated structure;
S107, forming a second electrode layer in the through hole, wherein the second electrode layer is contacted with the lower surface of the laminated structure;
after any of steps S104 to S107, the insulating protective layer in a partial region of the upper surface of the first electrode layer is removed, exposing part or all of the first electrode layer.
Hereinafter, a method of manufacturing the schottky barrier diode shown in fig. 1 will be described with reference to fig. 7-1 to 7-11.
Step 1: providing a silicon (111) plane single crystal substrate, as shown in fig. 7-1;
step 2: patterning the front surface of the silicon (111) surface substrate to divide the surface of the silicon substrate into a plurality of non-connected groove growth platforms, as shown in fig. 7-2;
step 3: depositing a gallium nitride monocrystal film on the front surface of the silicon substrate and the groove growth platform, as shown in fig. 7-3;
step 4: flattening the gallium nitride monocrystalline film layer, wherein the treatment effect is shown in figures 7-4;
step 5: on the gallium nitride single crystal film, heavily doped n+ alpha-Ga is epitaxially grown 2 O 3 Semiconductor layer 102b, as shown in fig. 7-5;
step 6: in heavily doped n+ type alpha-Ga 2 O 3 On the semiconductor film 102b, lightly n-type alpha-Ga is further epitaxially doped 2 O 3 Semiconductor layer 102a, as shown in fig. 7-6;
Step 7: the thin film stack structure of 102a and 102b is subjected to photolithography and etching processes, leaving an active region to be a schottky barrier diode, as shown in fig. 7-7;
step 8: deposition of SiO hundreds of nm thick on surfaces by CVD process 2 An insulating protective layer 107 as shown in fig. 7 to 8;
step 9: by photoetching and etching process, for SiO 2 The insulating protective layer 107 is partially etched to form a via hole, and an anode metal layer 105a is deposited, as shown in fig. 7 to 9;
step 10: etching the back surface of the substrate through photoetching and etching processes to form a through hole, and removing the substrate and the GaN film layer, wherein the through hole area of the substrate is larger than the active area of the Schottky barrier diode, as shown in figures 7-10;
in step 11, a cathode metal layer 105b is deposited in the through hole region of the substrate, wherein the cathode metal layer may be a single layer, or may be multiple layers, or may be a stacked combination of several metals, as shown in fig. 7-11.
Hereinafter, a method of manufacturing the schottky barrier diode shown in fig. 5 will be described with reference to fig. 8-1 to 8-11.
Step 1: providing a silicon (111) plane single crystal substrate as shown in fig. 8-1;
step 2: patterning the front surface of the silicon (111) surface substrate to divide the surface of the silicon substrate into a plurality of non-connected groove growth platforms, as shown in fig. 8-2;
Step 3: depositing a gallium nitride single crystal film 106a on the front surface of the silicon substrate and the groove growth platform, as shown in fig. 8-3;
step 4: the gallium nitride single crystal film layer is partially converted into beta-Ga from top to bottom through high-temperature oxidation 2 O 3 Film layer 106b, as shown in FIGS. 8-4;
step 5: flattening the film layer, wherein the treatment effect is shown in figures 8-5;
step 6: beta-Ga formed in oxidative conversion 2 O 3 On the film layer, respectively homoepitaxy heavily doped n+ beta-Ga 2 O 3 Semiconductor layer 112b and lightly doped n-type beta-Ga 2 O 3 Semiconductor layer 112a, as shown in fig. 8-6;
step 7: the thin film stack structure of 112a and 112b is subjected to photolithography and etching processes, leaving an active region to be a schottky barrier diode, as shown in fig. 8-7;
step 8: deposition of SiO hundreds of nm thick on surfaces by CVD process 2 An insulating protective layer 107 as shown in fig. 8 to 8;
step 9: by photoetching and etching process, for SiO 2 The insulating protective layer 107 is partially etched to form a via hole, and an anode metal layer 105a is deposited, as shown in fig. 8 to 9;
step 10: etching the back of the substrate by photoetching and etching processes to form a through hole, and removing the substrate, the GaN film layer and beta-Ga converted from GaN local oxidation 2 O 3 The thin film layer, the through hole area of the substrate is larger than the active area of the Schottky barrier diode, as shown in figures 8-10;
in step 11, a cathode metal layer 105b is deposited in the through hole region of the substrate, wherein the cathode metal layer may be a single layer, or may be multiple layers, or may be a stacked combination of several metals, as shown in fig. 8-11.
The above embodiments merely exemplify the structure of a semiconductor device such as a schottky barrier diode, a pn junction diode, a metal oxide semiconductor field effect transistor, or an insulated gate bipolar transistor, and the inventive concept of the present application can be applied to a semiconductor device such as a thyristor, an electrostatic induction transistor, a junction field effect transistor, a high electron mobility transistor, or a metal semiconductor field effect transistor.
In addition, the above embodiments only exemplify the preparation method of the Schottky Barrier Diode (SBD), and based on the inventive concept of the present application, the above method can be extended to pn junction diodes, metal oxide semiconductor field effect transistors, insulated gate bipolar transistors, thyristors, electrostatic induction transistors, junction field effect transistors, high electron mobility transistors or metal semiconductor field effect transistors according to the specific structures of different semiconductor devices.
It should be understood that the drawings of the embodiments described above are only for illustrating the technical aspects of the present invention and are not to be construed as limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.

Claims (8)

1. A gallium oxide device, comprising:
the substrate is a monocrystalline substrate with a hexagonal symmetrical structure, and is provided with a through hole;
the laminated structure is positioned on the surface of the upper surface of the substrate, at least comprises a gallium oxide semiconductor layer, and the cross section shape of the laminated structure is within the cross section shape of the through hole at the position of the surface of the lower surface of the laminated structure;
a first electrode layer located on the upper surface of the laminated structure;
a second electrode layer located in the through hole and contacting with the lower surface of the laminated structure;
And the insulating protection layer is covered on the surface of the substrate, the second electrode, the laminated structure and the first electrode layer, which is positioned on one side of the upper surface of the substrate, and a partial area is left on the upper surface of the first electrode layer to be in an exposed state.
2. A gallium oxide device according to claim 1, wherein: the single crystal substrate with the hexagonal symmetry structure is a silicon (111) face substrate, a silicon carbide substrate, a sapphire substrate or an aluminum nitride substrate.
3. A gallium oxide device according to claim 1, wherein: the gallium oxide is alpha-Ga 2 O 3 、ε-Ga 2 O 3 Or beta-Ga 2 O 3 。
4. A gallium oxide device according to claim 1, wherein: the gallium oxide device is a schottky barrier diode, a pn junction diode, a metal oxide semiconductor field effect transistor, an insulated gate bipolar transistor, a thyristor, an electrostatic induction transistor, a junction field effect transistor, a metal semiconductor field effect transistor or a light emitting diode.
5. A method for manufacturing a gallium oxide device, comprising the steps of:
s101, providing a single crystal substrate with a hexagonal symmetrical structure;
s102, forming a nitride single crystal film on the upper surface of the substrate;
S103, forming a laminated structure on the upper surface of the nitride single crystal film layer, wherein the laminated structure at least comprises a gallium oxide semiconductor layer;
s104, removing part of the nitride single crystal film and the laminated structure;
s105, forming an insulating protective layer on the substrate, the nitride single crystal film and the surface of the laminated structure on one side of the upper surface of the substrate;
s106, forming a through hole on the lower surface of the substrate along the thickness direction of the substrate, wherein the through hole extends to expose the lower surface of the laminated structure, and the cross section shape of the laminated structure is within the cross section shape of the through hole at the position of the surface of the lower surface of the laminated structure;
s107, forming a second electrode layer in the through hole, wherein the second electrode layer is contacted with the lower surface of the laminated structure;
after any of steps S105 to S107, the insulating protective layer is removed from a part or all of the upper surface of the laminated structure, and a first electrode layer is formed over the exposed laminated structure.
6. A method for manufacturing a gallium oxide device, comprising the steps of:
s101, providing a single crystal substrate with a hexagonal symmetrical structure;
S102, forming a nitride single crystal film on the upper surface of the substrate;
s103, sequentially forming a laminated structure and a first electrode layer on the upper surface of the nitride single crystal film layer, wherein the laminated structure at least comprises a gallium oxide semiconductor layer;
s104, removing part of the nitride single crystal film, the laminated structure and the first electrode layer;
s105, forming an insulating protective layer on the substrate, the nitride single crystal film, the laminated structure and the surface of the first electrode layer on one side of the upper surface of the substrate;
s106, forming a through hole on the lower surface of the substrate along the thickness direction of the substrate, wherein the through hole extends to expose the lower surface of the laminated structure, and the cross section shape of the laminated structure is within the cross section shape of the through hole at the position of the surface of the lower surface of the laminated structure;
s107, forming a second electrode layer in the through hole, wherein the second electrode layer is contacted with the lower surface of the laminated structure;
after any step S104 to S107, the insulating protection layer in the partial area of the upper surface of the first electrode layer is removed, and part or all of the first electrode layer is exposed.
7. The method for manufacturing a gallium oxide device according to claim 5 or 6, wherein: the nitride lattice structure is a hexagonal symmetrical structure.
8. The method for manufacturing a gallium oxide device according to claim 7, wherein: the nitride is an alloy formed by one or more of aluminum nitride, gallium nitride and indium nitride.
CN202111407950.2A 2021-11-25 2021-11-25 Gallium oxide device and preparation method thereof Pending CN116169157A (en)

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