JP5591151B2 - Silicon carbide junction barrier Schottky diode and method for manufacturing the same - Google Patents

Description

  The present invention relates to a junction barrier Schottky diode formed using silicon carbide and a method for manufacturing the same, and more particularly to a technique for reducing the resistance of connection between an anode electrode and a p-well.

  A semiconductor element using silicon carbide (SiC) is considered promising as a next-generation switching element capable of realizing high breakdown voltage, low loss, and high heat resistance, and is expected to be applied to various power semiconductor devices. In the manufacture of SiC semiconductor devices, it is an important issue to shorten the construction period and reduce the cost by reducing the number of manufacturing steps.

As a SiC semiconductor device, a Schottky diode including a metal electrode that is Schottky joined to an n-type SiC semiconductor layer is known. As a kind of Schottky diode, there is a junction barrier Schottky diode (hereinafter referred to as “JBS diode”) in which a p-type region (p-well) is partially disposed on a connection surface between an n-type SiC semiconductor layer and a metal electrode. (For example, Patent Document 1 below). In a JBS diode, a p-type region (p ⁺ region) having a higher impurity concentration is generally formed on the surface portion of the p-well in order to obtain a low-resistance ohmic contact between the p-well and the electrode. is there.

In order to form the p ⁺ region in silicon carbide, it is necessary to perform ion implantation (hereinafter referred to as “high temperature ion implantation”) in a state where the temperature of the semiconductor substrate is increased to about 200 ° C. Since a photoresist mask (resist mask) cannot be used at a high temperature at which high-temperature ion implantation is performed, it is necessary to use a hard mask having high heat resistance such as an oxide film as the implantation mask.

  The patterning of the hard mask is performed by forming a hard mask material film, forming a photoresist pattern (resist pattern) thereon, and performing etching using the resist pattern as a mask. For this reason, the number of manufacturing steps increases as compared with the case where a resist pattern is used for the implantation mask.

  Patent Document 1 discloses a silicon carbide JBS diode formed by the following manufacturing process. First, a p-type semiconductor layer is crystal-grown on the surface of the n-type semiconductor layer, and a first metal film that forms an ohmic junction is formed on the surface of the p-type semiconductor layer. Then, the first metal film and the p-type semiconductor layer are selectively etched using a resist mask to expose the n-type semiconductor layer, and a second metal film that forms a Schottky junction is formed on the exposed surface of the n-type semiconductor layer. .

JP 2009-224603 A

As described above, in the manufacture of the silicon carbide JBS diode, when forming a p-type region (p ⁺ region) having a high impurity concentration above the p-well, selective high-temperature ion implantation is performed. A hard mask was used. However, if a hard mask is used as an implantation mask, the number of manufacturing steps increases as compared with the case where a resist mask is used, which leads to an increase in the construction period and cost.

On the other hand, in Patent Document 1, since a silicon carbide JBS diode is formed without performing ion implantation and heat treatment at a high temperature, a hard mask is unnecessary. However, this method cannot provide a p-well below the p ⁺ region that is ohmic-connected to the metal electrode, and cannot provide a p-type termination region (guard ring) at the end of the metal electrode. The p-well works to alleviate the electric field concentration at the Schottky junction, and the termination region works to alleviate the electric field at the end of the JBS diode (below the end of the metal electrode). Is a very important component for increasing the withstand voltage of power semiconductor devices.

The present invention has been made to solve the above problems, and provides a method for manufacturing a silicon carbide JBS diode capable of selectively forming a p ⁺ region on a p-well without using a hard mask. This is the first purpose. A second object of the present invention is to provide a silicon carbide JBS diode which can be formed by the manufacturing method and has a low contact resistance with a metal electrode, ap ⁺ region.

  The method of manufacturing a silicon carbide JBS diode according to the present invention includes a step of forming a p-type region by ion implantation over the entire upper portion of a semiconductor layer made of n-type silicon carbide, and selectively etching the p-type region to forming a p-type semiconductor protrusion projecting upward from the upper surface of the n-type region by partially exposing the n-type region under the p-type region; and exposing the exposed portion of the n-type region and the p Forming a metal electrode that covers the convex portion of the mold semiconductor.

A silicon carbide JBS diode according to the present invention includes a semiconductor layer made of n-type silicon carbide, a p-well selectively formed in a main surface of the semiconductor layer, and the p-well of the semiconductor layer. An n-type region that is not present, and a p-type semiconductor protrusion that is formed on the main surface of the semiconductor layer corresponding to the p well so as to protrude upward from the main surface and has a higher impurity concentration than the p well. And a metal electrode that covers the n-type region, the p-well, and the p-type semiconductor convex portion, and a plurality of the p-type semiconductor convex portions are disposed on one p-well, On the p-well, the number and height of the plurality of p-type semiconductor protrusions are such that the contact area between the upper surface and side surfaces of the plurality of p-type semiconductor protrusions and the metal electrode is the p-type semiconductor protrusion. Multiple areas including the area between each other To be larger than the area of the formation region of the serial p-type semiconductor raised portion is set.

According to the present invention, a p-type semiconductor convex portion that is a p ⁺ region connected to a metal electrode can be formed without using a hard mask, so that the number of manufacturing steps can be reduced, and the construction period and cost can be reduced. . The p-type semiconductor protrusion protrudes upward from the upper surface of the n-type region, and can contact the metal electrode not only on the upper surface but also on the side surface. Therefore, the contact area between the metal electrode and the p-type semiconductor protrusion is increased, and the contact resistance therebetween can be reduced. In addition, by performing ion implantation before or after the formation of the p-type semiconductor convex portion, a termination region can be disposed under the p-well under the p-type semiconductor convex portion or the end portion of the metal electrode. Can greatly contribute to higher withstand voltage.

2 is a configuration diagram of a JBS diode according to Embodiment 1. FIG. It is a figure which shows the example of a layout of p ⁺ semiconductor convex part. FIG. 6 is a manufacturing process diagram for the JBS diode according to the first embodiment. 5 is a diagram showing a p-well formation procedure in the first embodiment. FIG. It shows a comparison of the p ⁺ regions (p ⁺ semiconductor raised portion) and the conventional p ⁺ region of the configuration of the first embodiment. 6 is a configuration diagram of a JBS diode according to Embodiment 2. FIG. FIG. 11 is a diagram showing a procedure for forming a p-well in the second embodiment. It shows a comparison of the structure of a conventional p ⁺ region and the p ⁺ region of the Embodiment 2 (p ⁺ semiconductor raised portion). FIG. 10 is a manufacturing process diagram for a JBS diode according to the third embodiment. FIG. 10 is a diagram showing a p-well formation procedure in the third embodiment. It is a figure which shows the breadth D1 of the spreading | diffusion of the impurity ion-implanted. It is a figure which shows the shortest distance D2 from the arbitrary points on the p ⁺ semiconductor convex part to the edge. FIG. 11 is a diagram showing a procedure for forming a p-well in a fourth embodiment. It is a simulation result of the spreading | diffusion of the impurity ion-implanted. FIG. 9 is a configuration diagram of a JBS diode according to a fifth embodiment.

<Embodiment 1>
FIG. 1 is a configuration diagram of a JBS diode according to Embodiment 1 of the present invention. The JBS diode is a silicon carbide semiconductor device formed using an epitaxial substrate composed of n-type SiC substrate 1 and n-type epitaxial layer 2 (semiconductor layer) grown thereon.

A p-well 3 is selectively formed in the main surface of the epitaxial layer 2. A plurality of p-type (p ⁺ -type) semiconductor regions 4 having an impurity concentration higher than that of the p-well 3 are arranged on the main surface of the epitaxial layer 2 corresponding to the p-well 3. Hereinafter, the semiconductor region 4 is referred to as “p ⁺ semiconductor convex portion”.

The anode electrode 6 (metal electrode) covers the epitaxial layer 2 and the p ⁺ semiconductor protrusion 4 and is Schottky connected to the n-type region (portion where the p-well 3 is not formed) of the epitaxial layer 2 and p ⁺ Ohmic connection is made to the semiconductor protrusion 4. Cathode electrode 9 is provided on the lower surface of SiC substrate 1.

  A guard ring 5 that is a p-type impurity region is provided as a termination region in a region including under the end of the anode electrode 6. Although a strong electric field is likely to be generated under the end of the anode electrode 6, the guard ring 5 functions to relax the electric field.

  On the anode electrode 6, the pad electrode 7 for connecting wiring is provided. The upper surface of the JBS diode is covered with a protective film 8 having an opening on the pad electrode 7.

The JBS diode of FIG. 1 is characteristic in that the p ⁺ region formed on the p well 3 and ohmically connected to the anode electrode 6 is a p ⁺ semiconductor convex portion 4 erected on the p well 3. . In the present embodiment, a plurality of p ⁺ semiconductor convex portions 4 are arranged on one p well 3.

FIG. 2 shows a layout example of the p ⁺ semiconductor convex portion 4 and is an enlarged plan view of the p well 3 portion. In plan view, the p ⁺ semiconductor protrusion 4 may be circular as shown in FIG. 2A or rectangular as shown in FIG. 2B. Alternatively, a line shape may be used as shown in FIG.

  Next, a method of manufacturing the JBS diode shown in FIG. 1 will be described with reference to the process diagram of FIG.

First, an n-type SiC substrate 1 is prepared, and an n-type epitaxial layer 2 is grown thereon (FIG. 3A). Then, the SiC substrate 1 and the epitaxial layer 2 are heated to about 200 ° C., and a p-type impurity such as Al is implanted over the entire surface of the epitaxial layer 2 by high-temperature ion implantation. A high p ⁺ region 4a is formed (FIG. 3B). Since this high-temperature ion implantation is performed on the entire surface of the epitaxial layer 2, a hard mask implantation mask is not required.

As described above, the high-temperature ion implantation is performed with the temperature of the SiC substrate 1 and the epitaxial layer 2 being about 200 ° C., and the temperature is specifically maintained within the range of 175 ° C. or more and 300 ° C. or less. Is more desirable, and it is more desirable if it is kept at a value within the range of 175 ° C. or more and 200 ° C. or less. If the temperature during high-temperature ion implantation is lower than 175 ° C., surface roughness increases in the formed p ⁺ region or crystallinity is insufficiently recovered. If the temperature exceeds 300 ° C., the p ⁺ region and the electrode This is because the ohmic contact resistivity is increased.

Then, on the p ⁺ region 4a, p ⁺ region for forming the semiconductor raised portion 4 to form an opening resist pattern (not shown), by etching using it as a mask, the p ⁺ region 4a is partially removed Thus, the n-type region of the epitaxial layer 2 is exposed. As a result, a p ⁺ semiconductor convex portion 4 protruding upward from the upper surface of the n-type region of the epitaxial layer 2 is formed (FIG. 3C).

Thereafter, a p-type impurity such as Al is implanted into the epitaxial layer 2 by selective ion implantation, thereby forming a p-well 3 under the p ⁺ semiconductor convex portion 4, and thereafter, at the end of the anode electrode 6. The guard ring 5 is formed in the lower part (FIG. 3D). Since the impurity concentration of the p well 3 and the guard ring 5 is lower than that of the p ⁺ semiconductor convex portion 4 (p ⁺ region 4a), this ion implantation is performed by normal ion implantation at room temperature, and used as an implantation mask. Use a resist pattern.

Then, heat treatment (activation annealing) for activating the ion-implanted impurities is performed at 1600 ° C. or higher. Further, cathode electrode 9 is formed on the lower surface of SiC substrate 1, and anode electrode 6 is formed so as to cover the upper surface of epitaxial layer 2 (exposed n-type region and portion of p well 3) and p ⁺ semiconductor protrusion 4. . Further, a pad electrode 7 is formed on the anode electrode 6, a protective film 8 is formed on the entire surface, and an upper portion of the pad electrode 7 is opened. Thereby, the structure of the JBS diode shown in FIG. 1 is obtained.

In the present embodiment, as shown in FIG. 3, the step of forming the p well 3 (FIG. 3D) is performed after the step of forming the p ⁺ semiconductor convex portion 4 (FIG. 3C). . That is, after forming the FIG. 4 (a) p ⁺ semiconductor raised portions 4 on the epitaxial layer 2 as to form a resist pattern 11 having an opening for containing the p ⁺ semiconductor raised portion 4 as shown in FIG. 4 (b) , Ion implantation for forming the p-well 3 is performed. Since this ion implantation is performed through the p ⁺ semiconductor convex portion 4, the p well 3 is formed so that a portion below the p ⁺ semiconductor convex portion 4 is shallow.

Further, in the present embodiment, as shown in FIGS. 1 and 2, a plurality of p ⁺ semiconductor convex portions 4 are disposed on one p well 3. FIG. 5A shows a p ⁺ semiconductor convex portion 4 which is a p ⁺ region of the present invention standing on the p well 3, and FIG. 5B is formed inside the p well 3. A conventional p ⁺ region 104 is shown.

Since the p ⁺ semiconductor convex portion 4 protrudes from the p well 3, it can contact the anode electrode (not shown in FIG. 5) formed on the p ⁺ semiconductor convex portion 4 not only on the top surface but also on the side surface. . On the other hand, since the conventional p ⁺ region 104 is formed in the p well 3 (the upper surface of the conventional p ⁺ region 104 is the same height as the upper surface of the p well 3), it can contact the anode electrode only on the upper surface. Therefore, if the number and height of the p ⁺ semiconductor convex portions 4 are appropriate, the contact area with the anode electrode can be made larger than that of the conventional p ⁺ region 104.

For example, the p ⁺ semiconductor convex portion 4 has a line shape in plan view as shown in FIG. 2C, and as shown in FIG. 5A, the width is W, the width is W1, and the height is H. It is assumed that N p ⁺ semiconductor convex portions are arranged at equal intervals. As an example, assuming that W = 3.3 μm, W1 = 0.3 μm, H = 0.2 μm, and N = 6 (the interval between the p ⁺ semiconductor convex portions 4 is 0.3 μm), the width W = 3.3 μm. Compared to the formed conventional p ⁺ region 104 (FIG. 5B), the contact area with the anode electrode can be increased by 27.3%. As another example, when W = 2.9 μm, W1 = 0.5 μm, H = 0.2 μm, and N = 4 (the interval between the p ⁺ semiconductor protrusions 4 is 0.3 μm), the width W = 2 Compared with the conventional p ⁺ region 104 formed with a thickness of .9 μm, the contact area with the anode electrode can be increased by 10.3%.

As described above, according to the present embodiment, it is possible to form the p ⁺ region (p ⁺ semiconductor convex portion 4) that is in ohmic contact with the anode electrode 6 (metal electrode) without using a hard mask. It is possible to reduce the construction period and cost. The p ⁺ semiconductor convex portion 4 protrudes from the p well 3 and can contact the anode electrode 6 not only on the upper surface but also on the side surface. Therefore, the contact area between the anode electrode 6 and the p ⁺ semiconductor convex portion 4 is increased, and the contact resistance therebetween can be reduced.

Also, by selective ion implantation using the resist pattern as a mask, a p-well can be disposed under the p ⁺ semiconductor convex portion 4 and a guard ring 5 (termination region) is provided in a region including the portion below the end of the anode electrode 6. This can greatly contribute to the increase of the withstand voltage of the silicon carbide JBS diode.

<Embodiment 2>
FIG. 6 is a configuration diagram of a JBS diode according to the second embodiment. In the figure, the same elements as those shown in FIG. In the JBS diode, one p ⁺ semiconductor convex portion 4 is disposed on each p well 3 with respect to the configuration of FIG.

The manufacturing method of the JBS diode of the present embodiment is the same as that of the first embodiment except for the formation pattern of the p ⁺ semiconductor convex portion 4. Therefore, the process of forming the p well 3 is performed after the process of forming the p ⁺ semiconductor convex portion 4. That is, after the formation of the p ⁺ semiconductor raised portions 4 on the epitaxial layer 2 as shown in FIG. 7 (a), a resist pattern 11 having an opening for containing the p ⁺ semiconductor raised portion 4 as shown in FIG. 7 (b) , Ion implantation for forming the p-well 3 is performed. Since this ion implantation is performed through the p ⁺ semiconductor convex portion 4, the p well 3 is formed so that a portion below the p ⁺ semiconductor convex portion 4 is shallow.

Here, the shape of the p-well 3 in FIG. 7B is compared with the shape of the p-well 3 shown in FIG. 4B in the first embodiment. In the present embodiment, since only one p ⁺ semiconductor convex portion 4 is disposed on the p well 3, there is one recess (shallow portion) on the bottom surface of the p well 3 in FIG. On the other hand, in the first embodiment, since a plurality of p ⁺ semiconductor convex portions 4 are arranged on the p well 3, the bottom of the p well 3 in FIG.

  Normally, electric field concentration is likely to occur at the corners of the bottom surface of the p-well 3, so that if the bottom surface of the p-well 3 has many dents, the withstand voltage performance of the JBS diode may deteriorate. The JBS diode of the present embodiment has fewer places where electric field concentration is likely to occur at the bottom of the p-well 3 than in the first embodiment, thereby preventing a reduction in withstand voltage performance.

Since the p ⁺ semiconductor convex portion 4 of the present embodiment is also in contact with the anode electrode 6 on the upper surface and the side surface, the contact resistance with the anode electrode 6 is reduced. For example, the p ⁺ semiconductor convex portion 4 has a line shape in plan view, and as shown in FIG. 8A, one p ⁺ semiconductor convex portion having a width W and a height H is arranged on the p well 3. Suppose that it is installed. As an example, when W = 3.0 μm and H = 0.2 μm, compared with the conventional p ⁺ region 104 (FIG. 8B) similarly formed with a width W = 3.0 μm, The contact area can be increased by 13.3%.

However, if it can increase forming a p ⁺ semiconductor raised portion 4, it means that the area of the side surfaces greatly contributes to the contact area between the anode electrode 6, than broaden the p ⁺ semiconductor raised portions 4, of the embodiment The contact area can be increased efficiently by increasing the number of p ⁺ semiconductor protrusions 4 as in the first mode. The first embodiment has this merit.

<Embodiment 3>
In the third embodiment, in the formation of the JBS diode according to the present invention, the step of forming the p well 3 is performed prior to the step of forming the p ⁺ semiconductor convex portion 4 (patterning of the p ⁺ region 4a). The basic structure of the JBS diode is the same as that shown in FIG.

  Hereinafter, a method of manufacturing the JBS diode according to the third embodiment will be described with reference to the process diagram of FIG.

First, an n-type SiC substrate 1 is prepared, and an n-type epitaxial layer 2 is grown thereon (FIG. 9A). Then, the SiC substrate 1 and the epitaxial layer 2 are heated to about 200 ° C., and a p-type impurity such as Al is implanted over the entire surface of the epitaxial layer 2 by high-temperature ion implantation. A high p ⁺ region 4a is formed (FIG. 9B). Since this high-temperature ion implantation is performed on the entire surface of the epitaxial layer 2, a hard mask implantation mask is not required.

Next, a p-type impurity such as Al is implanted into the epitaxial layer 2 by selective ion implantation to form a p-well 3 and a guard ring 5 deeper than the p ⁺ region 4a (FIG. 9C). Since the impurity concentration of the p well 3 and the guard ring 5 is lower than that of the p ⁺ region 4a, this ion implantation is performed by normal ion implantation at room temperature, and a resist pattern is used as an implantation mask.

Thereafter, on the p ⁺ region 4a, p ⁺ a resist pattern having an opening region for forming the semiconductor raised portion 4 (not shown), by etching using it as a mask, the p ⁺ region 4a is partially removed Thus, the n-type region of epitaxial layer 2 and p well 3 are exposed. As a result, a p ⁺ semiconductor convex portion 4 protruding upward from the n-type region of the epitaxial layer 2 and the upper surface of the p well 3 is formed (FIG. 9D). Here, an example in which a plurality of p ⁺ semiconductor convex portions 4 are provided for one p well 3 is shown, but one p ⁺ semiconductor convex portion 4 may be provided for one p well 3.

Then, heat treatment (activation annealing) for activating the ion-implanted impurities is performed at 1600 ° C. or higher. Further, cathode electrode 9 is formed on the lower surface of SiC substrate 1, and anode electrode 6 is formed so as to cover the upper surface of epitaxial layer 2 (exposed n-type region and portion of p well 3) and p ⁺ semiconductor protrusion 4. . Further, a pad electrode 7 is formed on the anode electrode 6, a protective film 8 is formed on the entire surface, and an upper portion of the pad electrode 7 is opened. Thereby, the structure of the JBS diode shown in FIG. 1 is obtained.

In the present embodiment, as shown in FIG. 9, the step of forming the p well 3 (FIG. 9C) is performed before the step of forming the p ⁺ semiconductor convex portion 4 (FIG. 9D). Is called. That is, as shown in FIG. 10A, a resist pattern 11 having an opening in the formation region of the p well 3 is formed, ion implantation for forming the p well 3 is performed, and then the p ⁺ region 4a is patterned. The p ⁺ semiconductor convex portion 4 is formed as shown in FIG. Since the ion implantation for forming the p well 3 is performed through the p ⁺ region 4a, the p well 3 is formed shallow overall, but the surface of the p ⁺ region 4a before patterning is flat. The bottom surface has a flat shape without a dent.

According to the present embodiment, the number of corners on the bottom surface of the p-well 3 where electric field concentration is likely to occur is minimized (only at both ends of the p-well 3). Withstand voltage performance is improved. However, it should be noted that the formation depth (thickness) of the p-well 3 is limited compared to the first embodiment because the ion implantation for forming the p-well 3 is performed via the p ⁺ region 4a. .

<Embodiment 4>
In the fourth embodiment, a method is proposed in which the bottom surface of the p well 3 can be made flat and the formation depth of the p well 3 can be made equal to that of the first embodiment.

When an impurity is ion-implanted into the epitaxial layer 2, the impurity is implanted with a certain extent in the lateral direction. Therefore, as shown in FIG. 11, the p-well 3 is formed so as to enter under the resist pattern 11 by the width D1 of the spread of the implanted impurity. In the present embodiment, “the maximum value of the shortest distance D2 from an arbitrary point on the p ⁺ semiconductor convex portion 4 to the end of the p ⁺ semiconductor convex portion 4 in plan view” is expressed as “ion implantation for forming the p well 3”. The width of the impurity in the lateral direction is smaller than the width D1 ".

Figure 12 (a) ~ (c) is, in the configuration shown in FIG. 2 (a) ~ (c), from an arbitrary point on the p ⁺ semiconductor raised portion 4 (black dots) of the p ⁺ semiconductor protrusions 4 An example of the shortest distance D2 to the end is shown. For example, when the p ⁺ semiconductor convex portion 4 is circular as shown in FIG. 12A, the “maximum value of the distance D2” corresponds to the radius of the circle. If the rectangle is as shown in FIG. 12B, the “maximum value of the distance D2” corresponds to half the length of the short side of the rectangle, and if it is a line shape as shown in FIG. The “maximum value of the distance D2” corresponds to half of the line width.

The procedure for manufacturing the JBS diode according to the present embodiment is the same as that in the first embodiment (FIG. 3). Therefore, the step of forming the p well 3 (FIG. 3D) is performed after the step of forming the p ⁺ semiconductor convex portion 4 (FIG. 3C). That is, after the formation of the p ⁺ semiconductor raised portions 4 on the epitaxial layer 2 as shown in FIG. 13 (a), a resist pattern 11 having an opening for containing the p ⁺ semiconductor raised portion 4 as shown in FIG. 13 (b) , Ion implantation for forming the p-well 3 is performed. Since This ion implantation is performed through the p ⁺ semiconductor protrusions 4, "the maximum value of the distance D2" of the p ⁺ semiconductor raised portion 4 is smaller than the "spread width D1 of the impurity of the p-well 3", p The well 3 is formed so as to enter the entire lower portion of the p ⁺ semiconductor convex portion 4. Therefore, the bottom surface of the p-well 3 has a flat shape without a dent.

According to the present embodiment, the number of corners on the bottom surface of the p-well 3 where electric field concentration is likely to occur is minimized (only at both ends of the p-well 3). Withstand voltage performance is improved. In addition, since the ion implantation for forming the p well 3 is performed after the formation of the p ⁺ semiconductor protrusion 4 (patterning of the p ⁺ region 4a), the p well 3 can be formed at the same depth as in the first embodiment. .

  FIG. 14 shows the result of simulating the lateral spread of Al in the SiC substrate when Al is ion-implanted into the SiC substrate with an energy of 700 keV. In this case, Al was observed to spread about 250 nm in the lateral direction. This spread increases as the implantation energy increases.

For example, when the “maximum value of the distance D2” of the p ⁺ semiconductor convex portion 4 is 250 nm, if the ion implantation of Al at an energy of 700 keV or more is performed at least once in the ion implantation for forming the p well 3, the p well 3 Can be formed so as to enter the entire lower part of the p ⁺ semiconductor convex portion 4, and the bottom surface of the p well 3 can be made flat.

<Embodiment 5>
FIG. 15 is a configuration diagram of a JBS diode according to the fifth embodiment. In the JBS diode, the anode electrode 6 is composed of a first metal part 61 and a second metal part 62 made of different metals, respectively, compared to the structure of FIG.

The first metal portion 61 is a portion that is formed on the n-type region (portion where the p-well 3 is not formed) of the epitaxial layer 2 and is Schottky connected to the n-type region. Second metal portion 62 is a portion that is in ohmic contact with p well 3, is formed on p well 3 so as to cover p ⁺ semiconductor convex portion 4, and is p-type silicon carbide rather than the material of first metal portion 61. It consists of a material with low contact resistance with respect to a semiconductor (p ⁺ semiconductor convex part 4). Examples of the material of the first metal part 61 include Ti, Ni, W, and the like. Moreover, as a material of the 2nd metal part 62, the laminated structure of Ni, Ti-Al, etc. are mentioned.

As described above, in the JBS diode according to the present invention, since the p ⁺ semiconductor convex portion 4 protrudes from the upper surface of the epitaxial layer 2, the contact area between the p ⁺ semiconductor convex portion 4 and the anode electrode 6 is large. Thus the portion in contact with p ⁺ semiconductor raised portion 4, by the contact resistance with the p ⁺ semiconductor raised portion 4 is disposed a lower second metal portion 62, can be efficiently reduce the contact resistance.

However, in order to form the anode electrode 6, the step of forming the first metal portion 61 on the n-type region of the epitaxial layer 2 and the second metal portion 62 on the p well 3 are p ⁺ semiconductor convex portions. It should be noted that the number of manufacturing steps increases because it is necessary to perform the process separately to cover 4. In addition, when high temperature heat treatment is necessary to obtain an ohmic connection between the second metal portion 62 and the p ⁺ semiconductor convex portion 4, the second metal portion 62 is formed so that the Schottky characteristics are not deteriorated thereby. After the high temperature heat treatment, the first metal part 61 may be formed.

DESCRIPTION OF SYMBOLS 1 SiC substrate, 2 Epitaxial layer, 3 p well, 4 p ⁺ semiconductor convex part, 4ap ⁺ area | region, 5 guard ring, 6 anode electrode, 7 pad electrode, 8 protective film, 9 cathode electrode, 11 resist pattern, 61st 1 metal part, 62 2nd metal part.

Claims (14)

forming a p-type region by ion implantation over the entire upper portion of the semiconductor layer made of n-type silicon carbide;
Selectively etching the p-type region to partially expose the n-type region below the p-type region, thereby forming a p-type semiconductor protrusion protruding upward from the upper surface of the n-type region; ,
Forming a metal electrode that covers the exposed portion of the n-type region and the p-type semiconductor protrusion, and a method for manufacturing a silicon carbide junction barrier Schottky diode. 2. The method of manufacturing a silicon carbide junction barrier Schottky diode according to claim 1, wherein the step of forming the p-type region is performed in a state where the semiconductor layer is heated to a temperature within a range of 175 ° C. or more and 300 ° C. or less . The method further comprising: forming a p-well having a lower impurity concentration than that of the p-type region in the semiconductor layer in a region including under the p-type semiconductor protrusion by selective ion implantation. The manufacturing method of the silicon carbide junction barrier Schottky diode of description. 4. The method for manufacturing a silicon carbide junction barrier Schottky diode according to claim 3, wherein a photoresist pattern is used as a mask in the selective ion implantation in the step of forming the p-well. The method for manufacturing a silicon carbide junction barrier Schottky diode according to claim 3 or 4, wherein a plurality of the p-type semiconductor protrusions are disposed on one p-well. The step of forming the p-well is performed after the step of forming the p-type region and before the step of forming the p-type semiconductor convex portion. A method for manufacturing a silicon carbide junction barrier Schottky diode. 6. The method for manufacturing a silicon carbide junction barrier Schottky diode according to claim 3, wherein the step of forming the p-well is performed after the step of forming the p-type semiconductor convex portion. The maximum value of the shortest distance from an arbitrary point on the p-type semiconductor convex portion to the end of the p-type semiconductor convex portion in plan view is smaller than the width of impurities in the lateral direction in the selective ion implantation. A method for manufacturing a silicon carbide junction barrier Schottky diode according to claim 7. The silicon carbide junction according to any one of claims 1 to 8, further comprising a step of forming a p-type termination region in the semiconductor layer in a region under the end of the metal electrode by selective ion implantation. Barrier Schottky diode manufacturing method. The step of forming the metal electrode includes:
Forming a first metal that is Schottky connected to the n-type region so as to cover an exposed portion of the n-type semiconductor region;
10. A method of forming a second metal having a contact resistance with respect to a p-type silicon carbide semiconductor lower than that of the first metal so as to cover the p-type semiconductor convex portion. The manufacturing method of the silicon carbide junction barrier Schottky diode of description. a semiconductor layer made of n-type silicon carbide;
A p-well selectively formed in the main surface of the semiconductor layer;
An n-type region that is a portion of the semiconductor layer where the p-well is not formed;
A p-type semiconductor convex portion formed on the main surface of the semiconductor layer corresponding to the p well so as to protrude upward from the main surface, and having a higher impurity concentration than the p well;
A metal electrode that covers the n-type region, the p-well and the p-type semiconductor protrusion ,
A plurality of the p-type semiconductor protrusions are disposed on one p-well,
On the respective p-wells, the number and height of the plurality of p-type semiconductor protrusions are such that the contact area between the upper surface and side surfaces of the plurality of p-type semiconductor protrusions and the metal electrode is the p-type semiconductor protrusion. The silicon carbide junction barrier Schottky diode is set so as to be larger than the area of the plurality of p-type semiconductor protrusions including the region between the portions . The bottom surface of the p-well is flat
The silicon carbide junction barrier Schottky diode according to claim 11. A p-type termination region formed in the semiconductor layer in a region including under the end of the metal electrode;
The silicon carbide junction barrier Schottky diode according to claim 11 or 12. The metal electrode is
A first metal part Schottky connected to the n-type region;
a second metal portion made of a material having a lower contact resistance with respect to the p-type silicon carbide semiconductor than the material of the first metal portion and connected to the p-type semiconductor convex portion.
The silicon carbide junction barrier Schottky diode according to any one of claims 11 to 13.