JP2013089907A - Silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device with improved bonding resistance, and a manufacturing method thereof.SOLUTION: A silicon carbide semiconductor device comprises: a silicon carbide substrate 1; an n-type silicon carbide layer 2 formed on the silicon carbide substrate 1; a low-concentration p-type JTE region 3 formed in a ring shape near a surface of the n-type silicon carbide layer 2 in a plan view; a high-concentration p-type region 4 formed in the ring shape in contact with the low-concentration p-type JTE region 3 inside a low-concentration p-type JTE 3 near the surface of the n-type silicon carbide layer 2 in a plan view; a p-type ohmic electrode 5 formed on a part of the high-concentration p-type region 4; a Schottky electrode 6 covering the p-type ohmic electrode 5 and formed on the high-concentration p-type region 4 and the n-type silicon carbide layer 2; a first electrode formed on the Schottky electrode 6; and a second electrode formed on the side on which the n-type silicon carbide layer of the silicon carbide substrate is not formed.

Description

The present invention relates to a silicon carbide semiconductor device.

  Silicon carbide semiconductor (SiC) has superior characteristics such as a higher breakdown voltage, a wider energy band gap, and higher thermal conductivity than silicon semiconductor, and thus has excellent characteristics such as a light emitting element, a high power power device, and a high temperature resistant element. Applications to radiation resistant elements, high frequency elements, etc. are expected.

  Conventionally, SiC Schottky barrier diodes are known to cause element breakdown even when a surge current flows in the forward direction, even with a relatively low surge current. In order to solve this problem, an n-type region and a p-type region are arranged in parallel on one surface of the SiC semiconductor element so that holes that are minority carriers are injected from the p-type region when a large current is conducted. An element structure has been proposed (see, for example, Non-Patent Document 1). In the case of such an element structure, surge resistance can be improved.

Such an element structure is called an MPS (Merged PN Schottky) structure. In the MPS structure, Schottky diodes and pn-type diodes are alternately arranged on one surface of the semiconductor element. In the conventional MPS structure, by providing the pn diode in the Schottky barrier diode as described above, a structure that is resistant to a forward current surge, that is, a high IFSM (Forward Surge Maximum) is realized.
The basic structure of a JBS (Junction Barrier Controlled Shotky) diode is the same as that of an MPS diode.

JP 2003-51601 A JP 2006-196775 A JP 2008-42198 A

Analysis of a High-Voltage Merged pin / Schotty (MPS) Rectifier: IEEE Electron Device Letters, Vol. Edl8; 9, September 1987: p407-409.

  However, in the conventional MPS structure, when providing the p-type ohmic electrode on the p-type semiconductor layer, it is necessary to provide a margin of several μm to several tens of μm for each p-type ohmic electrode with respect to the p-type semiconductor layer. Therefore, this margin hinders reduction of the element area. That is, the conventional MPS structure has a configuration in which a plurality of pn diodes are provided in the center of the element, and a p-type ohmic electrode is disposed on each pn diode, and a plurality of p-type ohmic electrodes are disposed in the center of the element. To do. In this configuration, a margin space as many as the number of p-type ohmic electrodes is required at the center of the element, and this margin hinders miniaturization of the element.

  Further, in the conventional MPS structure, since the p-type ohmic electrode is in the bonding region at the center of the element, the device characteristics may be impaired if the bonding power is increased during bonding.

  The present invention has been made in view of the above circumstances, and a p-type impurity region having a higher concentration than the JTE region is formed in a ring shape adjacent to the ring-shaped JTE region disposed at the end of the element. In addition, by providing a p-type ohmic electrode only on a part of the p-type impurity region, a function of resistance to forward current surge is assigned to the end portion of the element, and a p-type is provided in the central portion of the element. An object of the present invention is to provide a silicon carbide semiconductor device having improved bonding resistance by disposing no ohmic electrode and a method for manufacturing the same.

In order to achieve the above object, the present invention provides the following means.
(1) A silicon carbide substrate, an n-type silicon carbide layer formed on the silicon carbide substrate, and a low-concentration p-type JTE formed in a ring shape in plan view near the surface of the n-type silicon carbide layer A high-concentration p-type region formed in a ring shape in plan view in contact with the low-concentration p-type JTE region on the inside of the low-concentration p-type JTE near the surface of the n-type silicon carbide layer And a p-type ohmic electrode formed in a part on the high-concentration p-type region, and the p-type ohmic electrode, and formed on the high-concentration p-type region and the n-type silicon carbide layer. A Schottky electrode; a first electrode formed on the Schottky electrode; and a second electrode formed on a side of the silicon carbide substrate where the n-type silicon carbide layer is not formed. The silicon carbide semiconductor device characterized by the above-mentioned.
(2) The low-concentration p-type JTE region is formed in a ring shape in plan view, and a plurality of p-type regions having different impurity concentrations are adjacent to each other. Silicon carbide semiconductor device.
(3) The area of the high concentration p-type region is 0.8 to 3.5 times larger than the area of the region surrounded by the low concentration p-type JTE region (1) or ( 2) The silicon carbide semiconductor device according to any one of 2).
(4) The low-concentration p-type JTE region and the high-concentration p-type region are similar in shape, and the ring-shaped width of the high-concentration p-type region is 2 of the ring-shaped width of the low-concentration p-type JTE. The silicon carbide semiconductor device according to any one of (1) to (3), wherein the size is 5 to 5 times.

  The “ring shape” of the present invention is not limited to a circular shape, and may be a shape close to a rectangle or other shapes.

  According to the silicon carbide semiconductor device of the present invention, it is formed inside the low-concentration p-type JTE near the surface of the n-type silicon carbide layer, in contact with the low-concentration p-type JTE region, and in a ring shape in plan view. Since the structure including the high-concentration p-type region formed and the p-type ohmic electrode formed on a part of the high-concentration p-type region is employed, the p-type ohmic electrode is close to the end side of the element. Since the margin for the p-type ohmic electrode need only be provided on the end side of the element, the element area can be reduced. In addition, the p-type ohmic electrode is closer to the end of the element, and since there is no p-type ohmic electrode in the center of the element, a loss of element characteristics due to the p-type ohmic electrode is caused during bonding. There is no.

  According to the silicon carbide semiconductor device of the present invention, the low-concentration p-type JTE region is formed in a ring shape in plan view, and adopts a configuration in which a plurality of p-type regions having different impurity concentrations are adjacent to each other. Thus, the electric field concentration can be relaxed more smoothly.

  According to the silicon carbide semiconductor device of the present invention, a configuration is employed in which the area of the high-concentration p-type region is 0.8 to 3.5 times the area of the region surrounded by the low-concentration p-type JTE region. As a result, the bonding resistance can be improved without reducing the IFSM capability as compared with the conventional striped pn diode structure.

  According to the silicon carbide semiconductor device of the present invention, the low-concentration p-type JTE region and the high-concentration p-type region are similar in shape, and the ring-shaped width of the high-concentration p-type region is the ring shape of the low-concentration p-type JTE. By adopting a configuration that is at least 2.5 times as large as the width, the forward surge absorbing portion can be provided using the high-concentration p-layer while providing the effect of JTE.

(A) It is a plane schematic diagram of the silicon carbide semiconductor device which is 1st Embodiment to which this invention is applied. (B) It is a cross-sectional schematic diagram along the A-A 'line | wire shown by (a). FIG. 2 is an enlarged schematic cross-sectional view around a p-type ohmic electrode of the silicon carbide semiconductor device shown in FIG. 1. (A) It is a plane schematic diagram of the silicon carbide semiconductor device which is 2nd Embodiment to which this invention is applied. (B) It is a cross-sectional schematic diagram along the B-B 'line | wire shown by (a). It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the silicon carbide semiconductor device which is one Embodiment to which this invention is applied. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the silicon carbide semiconductor device which is one Embodiment to which this invention is applied. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the silicon carbide semiconductor device which is one Embodiment to which this invention is applied. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the silicon carbide semiconductor device which is one Embodiment to which this invention is applied. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the silicon carbide semiconductor device which is one Embodiment to which this invention is applied. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the silicon carbide semiconductor device which is one Embodiment to which this invention is applied. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the silicon carbide semiconductor device which is one Embodiment to which this invention is applied. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the silicon carbide semiconductor device which is one Embodiment to which this invention is applied. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the silicon carbide semiconductor device which is one Embodiment to which this invention is applied. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the silicon carbide semiconductor device which is one Embodiment to which this invention is applied.

  Hereinafter, the configuration of the present invention will be described with reference to the drawings. In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. . In addition, the materials, dimensions, and the like exemplified in the following description are examples, and the present invention is not limited to them, and can be appropriately changed and implemented without changing the gist thereof.

[Silicon carbide semiconductor device (first embodiment)]
FIG. 1A is a schematic plan view showing an example of a part of the silicon carbide semiconductor device (Schottky barrier diode) of the first embodiment to which the present invention is applied. FIG. 1B is a schematic cross-sectional view along the line AA ′ shown in FIG.
This will be described in detail below with reference to FIGS. 1 (a) and 1 (b).

  Silicon carbide semiconductor device 100 is formed in a ring shape in plan view in the vicinity of the surface of silicon carbide substrate 1, n-type silicon carbide layer 2 formed on silicon carbide substrate 1, and n-type silicon carbide layer 2. The low-concentration p-type JTE region 3 and the low-concentration p-type JTE 3 near the surface of the n-type silicon carbide layer 2 are in contact with the low-concentration p-type JTE region 3 and formed in a ring shape in plan view. The high-concentration p-type region 4, the p-type ohmic electrode 5 formed on a part of the high-concentration p-type region 4, and the p-type ohmic electrode 5. The Schottky electrode 6 formed on the silicon carbide layer 2, the first electrode (not shown) formed on the Schottky electrode 6, and the n-type silicon carbide layer of the silicon carbide substrate are not formed. And a second electrode (not shown) formed on the side.

  As silicon carbide substrate 1, a 4H—SiC substrate which is a SiC single crystal can be used. The plane orientation may be a c plane and an off angle may be provided. Furthermore, the Si surface or the C surface may be used. The SiC single crystal substrate 1 is an n-type semiconductor substrate doped with an n-type impurity at a high concentration.

  N-type silicon carbide layer 2 is preferably formed by epitaxial growth on silicon carbide single crystal substrate 1.

  The low-concentration p-type JTE region 3 is provided in order to alleviate electric field concentration at the peripheral portion (element end portion) of the Schottky junction. It is preferable that the impurity concentration be reduced from the periphery of the Schottky junction toward the periphery.

High-concentration p-type region (p-type impurity region) 4 is formed in n-type silicon carbide layer 2, and a pn junction is formed at the interface with n-type silicon carbide layer 2. Thereby, the rectification property of silicon carbide semiconductor device 100 is improved.
The high concentration p-type region 4 is formed in contact with the low concentration p-type JTE region 3 inside the low concentration p-type JTE 3 disposed at the peripheral portion (element end) of the Schottky junction. That is, the high-concentration p-type region 4 on which the p-type ohmic electrode 5 is formed is formed not on the center portion of the device but on the peripheral portion (end portion) of the Schottky junction.

  The area of the high-concentration p-type region 4 is 0.8 to 3.5 times the area of the region surrounded by the low-concentration p-type JTE region 3 (the region inside the low-concentration p-type JTE region 3 in FIG. 1). The size is preferred. This is because the resistance equal to or less than the forward current surge resistance of the conventional stripe-shaped p-type impurity region cannot be exhibited at 0.8 times or less. Further, if it is 3.5 times or more, the pad electrode burns out, and the withstand amount does not increase any more.

  The high-concentration p-type region 4 is similar to the low-concentration p-type JTE region 3, and the ring-shaped width of the high-concentration p-type region 4 is 2.5 of the ring-shaped width of the low-concentration p-type JTE region 3. It is preferable that the size is ˜5 times. This is because if it is 2.5 times or less, sufficient forward surge resistance cannot be obtained. In addition, if it is 5 times or more, the withstand capability cannot be improved only by increasing the area of the high-concentration p-type region 4.

The p-type ohmic electrode 5 is formed on a part of the high-concentration p-type region 4 disposed on the peripheral edge (element end) side of the Schottky junction. The p-type ohmic electrode 5 is provided not on the central portion of the element but only on the peripheral edge (end of the element) side of the Schottky junction.
As described above, since the forward current surge resistance function is assigned to the end portion of the element and the p-type ohmic electrode is not disposed in the central portion of the element, the bonding resistance is improved.
A titanium-aluminum (Ti-Al) alloy is known as one of metals forming an ohmic electrode with respect to p-type silicon carbide.

FIG. 2 is an enlarged view of the periphery of the p-type ohmic electrode 5 and is before alloying described later.
As shown in FIG. 2, the p-type ohmic electrode 5 includes a first alloy layer 5a provided on the high-concentration p-type region 4 side, and a side opposite to the high-concentration p-type region 4 with the first alloy layer 5a interposed therebetween. It has a two-layer structure with the second alloy layer 5b provided. In addition, the p-type ohmic electrode 5 in which a two-layer structure is observed in the cross-sectional observation of the electrode is an electrode having a good ohmic characteristic and a good surface state. This is related to the fact that, in the formation of the p-type ohmic electrode 5, the aluminum is deposited after the titanium is deposited, as will be described later in the method for manufacturing a silicon carbide semiconductor device. Therefore, when it is different from the above-described stacking order, it is not observed as a clear layer.
Note that the boundary between the first alloy layer 5a and the second alloy layer 5b can be determined from a boundary having different contrast when the cross section is observed using an electron microscope.

The p-type ohmic electrode 5 is a binary alloy layer containing at least titanium and aluminum. And as for the ratio of titanium and aluminum of this alloy layer, it is preferable that aluminum (Al) is 40-70 mass% and titanium (Ti) is 20-50 mass%. If the aluminum content is less than 40% by mass, it is not preferable because it does not exhibit ohmic properties. If the aluminum content exceeds 70% by mass, surplus aluminum forms a liquid phase and scatters to the surroundings, and a protective film such as SiO ₂ It is not preferable because it reacts with. Further, when Ti is less than 20%, excess aluminum is scattered to the surroundings and reacts with the SiO ₂ protective film, and when it exceeds 50% by mass, ohmic properties are not exhibited.

The Schottky electrode 6 is formed on the high-concentration p-type region 4 and the n-type silicon carbide layer 2, and the interface between the high-concentration p-type region 4 and the n-type silicon carbide layer 2 and the Schottky metal portion 5 has a metal A Schottky barrier generated by the junction of the semiconductor and the semiconductor is formed, and a Schottky junction region is formed. Thereby, the forward voltage drop of silicon carbide semiconductor device (Schottky barrier diode) 100 can be made lower than that of pn diode, and the switching speed can be increased.
Note that by increasing the ratio of the area occupied by the Schottky junction region in the entire electrode, the voltage drop when a current is passed in the forward direction can be reduced and the power loss can be reduced.

  Note that the p-type ohmic electrode 5 is placed on the center portion of the element of the silicon carbide semiconductor device (the portion inside the high-concentration p-type region 4 (portion P surrounded by the dotted line in FIG. 1B)). A p-type impurity region may be formed in order to provide a pn junction region in a manner that does not exist.

[Silicon Carbide Semiconductor Device (Second Embodiment)]
FIG. 3A is a schematic plan view showing an example of part of the silicon carbide semiconductor device of the second embodiment to which the present invention is applied. FIG. 3B is a schematic cross-sectional view taken along the line BB ′ shown in FIG.
This will be described in detail below with reference to FIGS. 3 (a) and 3 (b).

  Silicon carbide semiconductor device 200 is formed in a ring shape in plan view in the vicinity of the surface of silicon carbide substrate 1, n-type silicon carbide layer 2 formed on silicon carbide substrate 1, and n-type silicon carbide layer 2. Further, inside the low-concentration p-type JTE region 33 in which two p-type regions 33a and 33b having different impurity concentrations are adjacent to each other and the low-concentration p-type JTE 33 near the surface of the n-type silicon carbide layer 2, A high-concentration p-type region 4 formed in a ring shape in plan view in contact with the low-concentration p-type JTE region 33; and a p-type ohmic electrode 5 formed in a part on the high-concentration p-type region 4; The Schottky electrode 6 which covers the p-type ohmic electrode 5 and is formed on the high-concentration p-type region 4 and the n-type silicon carbide layer 2 and the first electrode formed on the Schottky electrode 6 (FIG. And the n-type silicon carbide layer of the silicon carbide substrate is formed. A second electrode formed on have side (not shown), and a.

The silicon carbide semiconductor device of the second embodiment differs from the silicon carbide semiconductor device of the first embodiment in that the low-concentration p-type JTE region is composed of two p-type regions having different impurity concentrations.
In the example shown in FIG. 3, the number of p-type regions having different impurity concentrations is two, but may be three or more.

The plurality of p-type regions having different impurity concentrations are preferably configured such that the impurity concentration decreases toward the periphery of the element. This is because the electric field concentration can be relaxed more smoothly.
In the example shown in FIG. 3, the p-type region 33b preferably has a lower impurity concentration than the p-type region 33a.

[Method of Manufacturing Silicon Carbide Semiconductor Device]
A method for manufacturing the Schottky barrier diode 100 according to the embodiment of the present invention will be described. 4 to 12 are process cross-sectional views illustrating an example of a method for manufacturing the Schottky barrier diode 100 of the present embodiment. In addition, the same code | symbol is attached | subjected about the member same as the member shown in FIG.1 and FIG.2.

  The manufacturing method of the Schottky barrier diode 100 of the present embodiment includes a step of forming the low concentration p-type JTE region 3 and the high concentration p-type region 4 on the surface 1a of the SiC single crystal substrate 1 (p-type impurity region formation step). The protective film 7 is formed so as to cover the step of forming the p-type ohmic electrode 5 (p-type ohmic electrode forming step) and the low-concentration p-type JTE region 3, the high-concentration p-type region 4, and the p-type ohmic electrode 5. A process (protective film forming process), a process of forming a back ohmic electrode 8 on the back surface 1b of the SiC single crystal substrate 1 (back ohmic electrode forming process), a low-concentration p-type JTE region 3, a high-concentration p-type region 4 and A step of forming the Schottky electrode 6 connected to the p-type ohmic electrode 5 (Schottky electrode formation step), and a step of forming the surface pad electrode 9 so as to cover the Schottky electrode 6 (table) Comprises a pad electrode formation step), a.

<P-type impurity region forming step>
First, as shown in FIG. 4, n-type epitaxial layer (n-type silicon carbide layer) 2 is formed on SiC single crystal substrate (silicon carbide substrate) 1.
In order to clean the n-type epitaxial layer (n-type silicon carbide layer) 2, the substrate is cleaned. As the cleaning, for example, so-called RCA cleaning is performed using sulfuric acid + hydrogen peroxide, ammonium hydroxide + hydrogen peroxide, hydrochloric acid + hydrogen peroxide, hydrofluoric acid aqueous solution, or the like.
Next, an oxide film is formed on the n-type epitaxial layer 2 by the CVD method.
Next, after applying a resist on the oxide film, a photo having windows corresponding to the low-concentration p-type JTE region (p-type impurity region) 3 and the high-concentration p-type region (p-type impurity region) 4 by a stepper. A resist pattern is formed. Although patterning by any suitable known photolithography method can be performed, a photoresist pattern including a fine pattern can be formed by using a stepper. Thereafter, the oxide film is dry etched to form windows corresponding to the low concentration p-type JTE region 3 and the high concentration p-type region 4.

  Next, using the oxide film in which the window portion is formed as a mask, ion implantation of aluminum or boron as a p-type impurity is performed into the n-type epitaxial layer 2. Then, after applying a resist again on the oxide film, a photoresist pattern having a window corresponding to the high concentration p-type region 4 is formed by a stepper, and then the oxide film is dry-etched to dry the high concentration p-type region 4. The window part corresponding to is formed. Next, using the oxide film in which the window portion is formed as a mask, ion implantation of aluminum or boron as a p-type impurity is performed into the n-type epitaxial layer 2. Thereafter, the oxide film is removed.

Next, after a carbide film (for example, a carbon film) is formed on the n-type epitaxial layer 2 by sputtering, a high-temperature heat treatment (for example, 1700 ° C.) is performed to activate the p-type impurities subjected to ion implantation. Is performed in an inert gas atmosphere or in a vacuum. Thereafter, the carbonized film is removed. Thereby, the low concentration p-type JTE region 3 and the high concentration p-type region 4 are formed.
The carbonized film may be formed by applying an organic material and then performing a heat treatment instead of the sputtering method.
FIG. 5 is a cross-sectional process diagram showing a state at the time after the formation of the low concentration p-type JTE region 3 and the high concentration p-type region 4.

<Protective film formation process>
Next, a surface protective film 7 made of a silicon oxide film (SiO ₂ ) is formed on the n-type epitaxial layer 2 in which the low-concentration p-type JTE region 3 and the high-concentration p-type region 4 are formed by, for example, the CVD method. .
FIG. 6 is a sectional process diagram showing the state at this point.

<Backside ohmic electrode formation process>
Next, a metal film made of, for example, Ni is formed on the back surface of the SiC single crystal substrate 1 on which the low-concentration p-type JTE region 3 and the high-concentration p-type region 4 are formed, for example, by sputtering or vapor deposition.
Next, heat treatment (for example, heat treatment at 950 ° C.) is performed in an inert gas atmosphere or vacuum to form the back ohmic electrode 8. Thereby, back surface ohmic electrode 8 forms a good ohmic contact with the back surface of SiC single crystal substrate 1.
FIG. 7 is a sectional process diagram showing the state at this point.
Next, as shown in FIG. 8, the surface protective film 7 is removed.

<P-type ohmic electrode formation process>
Next, a p-type ohmic electrode 5 having a desired size is formed on the high-concentration p-type region 4 by using a lift-off method, an etching method, or the like.
The p-type ohmic electrode 5 is formed by a step of laminating titanium on the n-type epitaxial layer 2 in which the high-concentration p-type region 4 is formed (titanium laminating step), and a step of laminating aluminum above the laminated titanium ( An aluminum lamination step) and a step of alloying by heat treatment (heat treatment step) are roughly configured.
Below, the case where the lift-off method is used is demonstrated.

First, as a pretreatment, the front surface of the substrate (the surface on which the high concentration p-type region 4 is formed) is cleaned. As the cleaning, for example, so-called RCA cleaning is performed using sulfuric acid + hydrogen peroxide, ammonium hydroxide + hydrogen peroxide, hydrochloric acid + hydrogen peroxide, hydrofluoric acid aqueous solution, or the like.
Next, an oxide film (not shown) is formed on the cleaned front surface.
Next, after applying a resist on the oxide film, a photoresist pattern having an opening in a portion corresponding to a region (a part of the high-concentration p-type region 4) where the p-type ohmic electrode 5 is formed is formed by a stepper. To do. Although patterning by any suitable known photolithography method can be performed, a photoresist pattern including a fine pattern can be formed by using a stepper.
Next, by wet etching, a portion of the oxide film that is not covered with the resist is removed to expose a part of the surface of the high-concentration p-type region 4 (region where the p-type ohmic electrode 5 is formed).

(Titanium lamination process)
Next, as shown in FIG. 9, a titanium film is laminated on a part of the exposed surface of the high-concentration p-type region 4 and the photoresist by using, for example, sputtering or vapor deposition. Thereby, the titanium layer 15a is formed.

(Aluminum lamination process)
Next, as shown in FIG. 9, an aluminum layer 15b is stacked on the titanium layer 15a by sputtering or vapor deposition.
Here, it is preferable that the film thicknesses of the titanium layer 15a and the aluminum layer 15b are each 10 to 10000 mm, more preferably 100 to 1000 mm, and particularly preferably 500 to 1000 mm. If the thickness of the titanium layer 15a and the aluminum layer 15b is less than 10 mm, it is not preferable because an electrode layer sufficient for ohmic bonding cannot be formed, and if it exceeds 10,000 mm, the surrounding insulating film may be affected. Absent.

In the present embodiment, the stacking order of titanium and aluminum when forming the p-type ohmic electrode 5 is defined as described above.
Next, by performing lift-off (peeling the oxide film and resist), a laminated structure of a titanium layer 15a and an aluminum layer 15b is formed on the high concentration p-type region 4 as shown in FIG.

(Heat treatment process)
Next, as shown in FIG. 10, the laminated titanium layer 15a and aluminum layer 15b are alloyed by heat treatment to form the p-type ohmic electrode 5.
An infrared lamp heating device (RTA device) or the like can be used for the heat treatment. The heat treatment temperature is preferably 880 to 930 ° C, and more preferably 890 to 910 ° C. If the heat treatment temperature is less than 880 ° C., the alloying reaction is not sufficiently promoted, and it is not preferable, and if it exceeds 930 ° C., diffusion control becomes difficult and a desired alloy composition cannot be obtained. The heat treatment time is preferably 1 to 5 minutes, more preferably 1 to 3 minutes. If the heat treatment time is less than 1 minute, the alloying reaction is not sufficiently promoted, and if it exceeds 5 minutes, the reaction with the substrate proceeds excessively and the surface of the electrode becomes rough. Note that the heat treatment is preferably performed in an inert gas atmosphere, and more preferably in an argon atmosphere. In this way, a binary alloy film made of titanium-aluminum is formed.

<Schottky electrode formation process>
Next, after applying a resist on the n-type epitaxial layer 2 on which the p-type ohmic electrode 5 is formed, a photoresist pattern is formed.
Next, a metal film made of, for example, titanium or molybdenum is formed on the resist in which the window has been formed by sputtering or vapor deposition.
Next, by removing (lifting off) the resist, only the metal film formed on the window portion can be left so as to cover the p-type ohmic electrode 5.
Next, heat treatment for controlling the Schottky barrier (for example, heat treatment at 600 ° C.) is performed in an inert gas atmosphere to form the Schottky electrode 6. Schottky electrode 6 is connected to SiC single crystal substrate 1 to form a Schottky contact.
FIG. 11 is a sectional process diagram showing the state at this point.
In this step, the resist protective film may be formed in the shape of the Schottky electrode 6 instead of the lift-off method, and portions other than the Schottky electrode 6 may be removed by wet or dry etching.

<Front surface pad electrode formation process>
Next, after applying a resist on the n-type epitaxial layer 2 on which the Schottky electrode 6 is formed, a photoresist pattern is formed by exposure and development.
Next, a metal film made of, for example, aluminum is formed on the resist in which the window has been formed by sputtering or vapor deposition.
Next, by removing the resist (lift-off), only the metal film formed on the window can be left on the Schottky electrode 6.
Thereby, the front surface pad electrode (first electrode) 9 connected to the Schottky electrode 6 is formed.
FIG. 12 is a sectional process diagram showing the state at this point.

Next, a passivation film is applied on the n-type epitaxial layer 2 on which the surface pad electrode 9 is formed. For example, a photosensitive polyimide film is used as the passivation film.
Next, a patterned passivation film 10 is formed by exposure and development.
FIG. 13 is a cross-sectional process diagram illustrating the state at this time. The passivation film 10 is formed so that a part of the surface of the front surface pad electrode 9 is exposed and only the end portion 9c of the front surface pad electrode 9 is covered. Is formed.
Finally, a two-layer metal film made of, for example, Ni / Ag or the like is formed as the back surface pad electrode (second electrode) 11 on the back surface ohmic electrode 8 by sputtering.

    Through the above process, the Schottky barrier diode 100 shown in FIG. 1 is manufactured.

1 silicon carbide substrate 2 n-type silicon carbide layer 3 low concentration p-type JTE region 4 high concentration p-type region 5 p-type ohmic electrode 6 Schottky electrode 8 back ohmic electrode 9 front surface pad electrode (first electrode)
11 Back pad electrode (second electrode)

Claims (4)

A silicon carbide substrate;
An n-type silicon carbide layer formed on the silicon carbide substrate;
A low-concentration p-type JTE region formed in a ring shape in plan view in the vicinity of the surface of the n-type silicon carbide layer;
A high-concentration p-type region formed in a ring shape in plan view in contact with the low-concentration p-type JTE region inside the low-concentration p-type JTE near the surface of the n-type silicon carbide layer;
A p-type ohmic electrode formed in a part on the high-concentration p-type region;
A Schottky electrode that covers the p-type ohmic electrode and is formed on the high-concentration p-type region and the n-type silicon carbide layer;
A first electrode formed on the Schottky electrode;
A silicon carbide semiconductor device comprising: a second electrode formed on a side of the silicon carbide substrate where the n-type silicon carbide layer is not formed.   2. The silicon carbide semiconductor device according to claim 1, wherein the low-concentration p-type JTE region is formed in a ring shape in plan view, and a plurality of p-type regions having different impurity concentrations are adjacent to each other. .   The area of the high-concentration p-type region is 0.8 to 3.5 times as large as the area of the region surrounded by the low-concentration p-type JTE region. The silicon carbide semiconductor device described.   The low-concentration p-type JTE region and the high-concentration p-type region are similar in shape, and the ring-shaped width of the high-concentration p-type region is 2.5 of the ring-shaped width of the low-concentration p-type JTE region. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the silicon carbide semiconductor device has a size of -5 times.

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