JP2009224641A - Silicon carbide semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device having a vertical power element capable of preventing side electric discharge from occurring. <P>SOLUTION: A conductive layer 9 is formed so that it covers the end face of a semiconductor chip, namely, it is in contact with a back surface electrode 7, entirely covers the end face of an n<SP>+</SP>-type substrate 1 and an n<SP>-</SP>-type drift layer 2, and reaches a passivation film 6. As a result of this, isopotential is attained instantaneously by the conductive layer 9, even if a high voltage is applied to a Schottky electrode 4 and potential is biased at the outer-periphery section of the semiconductor chip. Hence, side electric discharge is made less apt to occurring, and element destruction caused by the side electric discharge is restrained. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a SiC semiconductor device including a semiconductor element such as a Schottky barrier diode (hereinafter referred to as SBD) configured using silicon carbide (hereinafter referred to as SiC) and a method for manufacturing the same.

  SiC has a high breakdown electric field strength and can reduce the area of the outer peripheral portion provided to surround the outer periphery of the active region serving as the cell portion. For this reason, compared with the case where the chip area is the same as that of the Si semiconductor, the area of the active region can be increased. However, since the distance from the electrode or wiring formed in the active region to the end face of the semiconductor chip is shortened, a negative voltage such as a surge voltage is generated on the surface of the semiconductor chip in the semiconductor chip on which the vertical power element is formed. When applied to the side electrode, there is a problem that side discharge occurs between the electrode and the end face of the semiconductor chip, leading to element destruction. This will be described by taking as an example a case where a Schottky barrier diode (hereinafter referred to as SBD) is formed as a vertical power element on a semiconductor chip.

FIG. 4 is a schematic cross-sectional view showing a state of side discharge when the SBD 100 is formed. As shown in FIG, SBD 100 is, n on the surface of the n ⁺ -type substrate 101 ^- shot in contact with the surface of the type drift layer 102 through an opening 103a of the oxide film 103 ^- -type drift layer 102, n An anode electrode composed of the key electrode 104 and the wiring electrode 105 is formed, and a p-type RESURF is formed on the surface layer portion of the n ⁻ -type drift layer 102 so as to surround a Schottky contact place with the n ⁻ -type drift layer 103 in the Schottky electrode 104. The layer 108 is formed, and the back surface electrode 107 corresponding to the cathode electrode is formed on the back surface side of the n ⁺ type substrate 101. In such SBD 100, the outer peripheral portions of the Schottky electrode 104 and the wiring electrode 105 are covered with the passivation film 106. However, the distance over which the passivation film 106 covers the n ⁻ type drift layer 102, that is, the distance from the opening end of the opening 106 a of the passivation film 106 to the end face of the semiconductor chip is short, and as shown in FIG. Electric discharge easily occurs between the end face of the chip.

In order to solve such a problem, Patent Document 1 proposes a structure in which a mortar-shaped reinforcing insulating film is formed on the chip surface, and a guide electrode is disposed in a mortar-shaped portion of the mortar-shaped reinforcing insulating film. ing.
JP 2001-291860 A

  However, the mortar-shaped reinforcing insulating film as shown in Patent Document 1 has a complicated structure and cannot be formed with good reproducibility.

  In view of the above points, an object of the present invention is to provide a SiC semiconductor device including a vertical power element that can prevent side discharge from occurring, and a manufacturing method thereof.

  In order to achieve the above object, the present inventors have conducted intensive investigations. As a result, side discharge occurs when a high voltage is applied, causing a potential bias in the outer periphery of the semiconductor chip, thereby causing unevenness. It was found that the generation of a strong electric field has an effect. FIG. 5 is a top surface layout diagram of the SiC semiconductor device showing the portion where the potential is biased. In addition, although this figure is not sectional drawing, hatching is shown in order to make a figure legible. As shown in this figure, it was confirmed that a potential bias occurred in a portion where the width of the passivation film was narrow, and a side discharge occurred in this portion.

  Therefore, in the first aspect of the present invention, the end surface of the semiconductor chip is in contact with the back electrode (7), covers the entire end surfaces of the substrate (1) and the drift layer (2), and up to the passivation film (6). It is characterized in that a conductive layer (9) is provided.

  As described above, the conductor is formed so as to cover the end face of the semiconductor chip, that is, in contact with the back electrode (7), covers the entire end face of the substrate (1) and the drift layer (2), and reaches the passivation film (6). If the layer (9) is formed, even if a high voltage is applied to the surface electrodes (4, 5) and potential deviation is likely to occur in the outer peripheral portion of the semiconductor chip, the conductor layer (9) instantly performs the same. It becomes possible to make it a potential. As a result, side surface discharge is less likely to occur, and element breakdown due to side surface discharge can be suppressed.

  For example, as described in claim 2, any one of a metal layer, conductive grease, silver paste, or solder can be used as the conductive layer (9).

  Further, as described in claim 3, the first layer (9a) formed on the end face of the substrate (1) and the drift layer (2) and the surface of the passivation film (6) is in contact with the back electrode (7). The conductor layer (9) can also be configured as a structure having the second layer (9b) formed on the surface of the first layer (9a). In this case, as described in claim 4, the first layer (9a) can be a metal layer and the second layer (9b) can be a solder.

  Further, when mounting the SiC semiconductor device according to any one of claims 1 to 4 to the mounting substrate (20), the back electrode (7) is mounted by soldering to the mounting substrate (20). However, the conductor layer (8) can also be constituted by soldering.

  According to a sixth aspect of the present invention, there is provided a method of manufacturing a SiC semiconductor device, wherein the semiconductor chip is divided into semiconductor chips, and then contacted with the back electrode (7) at the end face of the semiconductor chip, and the substrate (1) and the drift layer ( 2) is characterized in that it includes a step of covering the entire end face and forming a conductor layer (9) extending to the passivation film (6).

  By performing the process of forming such a conductor layer (9), the SiC semiconductor device having the structure shown in claim 1 can be manufactured.

  For example, as described in claim 7, the step of forming the conductor layer (9) is performed by fixing the surface side of the semiconductor chip (1) on which the passivation film (6) is formed with a jig. After covering the side, it is performed as a step of applying a conductor layer (9) to the end face of the semiconductor chip (1). In this case, as described in claim 8, after the surface side of the semiconductor chip (1) on which the passivation film (6) is formed is fixed with a jig, the surface side is covered, and then the semiconductor chip (1 The back electrode (7) can be formed at the same time by applying the conductor layer (9) to the end face of). Thereby, since a conductor layer (9) and a back surface electrode (7) can be formed simultaneously, a simplification of a manufacturing process can be achieved.

  Moreover, when soldering a back surface electrode (7) with respect to a mounting board | substrate (20) as described in Claim 9, the process of forming a conductor layer (9) is made into the mounting board | substrate ( 20) Before soldering to the first layer (9a), which is in contact with the back electrode (7) and formed on the end surfaces of the substrate (1) and the drift layer (2) and the surface of the passivation film (6). And when the back electrode (7) is soldered to the mounting substrate (20), the second layer (9b) is formed by allowing the solder to spread over the surface of the first layer (9a). And forming the conductor layer (9) with the first layer (9a) and the second layer (9b).

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. In the present embodiment, an SiC semiconductor device including an SBD as a vertical power element will be described as an example.

FIG. 1 is a cross-sectional view of a semiconductor chip constituting an SiC semiconductor device including the SBD 10 according to the present embodiment. As shown in this figure, the SiC semiconductor device is formed using an n ⁺ type substrate 1 made of silicon carbide having an impurity concentration of about 2 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , for example. When the upper surface of the n ⁺ -type substrate 1 is the main surface 1a and the lower surface opposite to the main surface 1a is the back surface 1b, a dopant concentration lower than that of the substrate 1 on the main surface 1a, for example, 1 × 10 ^{15 to} 5 × An n ⁻ type drift layer 2 made of silicon carbide having an impurity concentration of about 10 ¹⁶ cm ⁻³ is laminated. The SBD 10 is formed in the cell portion (active region) of the n ⁺ -type substrate 1 and the n ⁻ -type drift layer 2, and the termination structure is formed in the outer peripheral region, thereby forming a SiC semiconductor device.

Specifically, an insulating film 3 made of a silicon oxide film or the like in which an opening 3a is partially formed in the cell portion is formed on the surface of the n ⁻ type drift layer 2. A Schottky electrode 4 made of, for example, Mo (molybdenum) or Ti (titanium) is formed so as to be in contact with the n ⁻ -type drift layer 2 in the portion 3a. The opening 3a formed in the insulating film 3 has, for example, a polygonal shape such as a square shape with rounded corners or a circular shape, and the Schottky electrode 4 has an n ⁻ type drift in the opening 3a. Schottky connection to layer 2 is made. Further, a wiring electrode 5 made of, for example, Al (aluminum) or the like is formed on the surface of the Schottky electrode 4, and the Schottky electrode 4 and the wiring electrode 5 constitute a surface electrode serving as an anode electrode. The voltage is applied to the Schottky electrode 4 by bonding the wiring electrode 5 or the like. Then, a passivation film 6 made of, for example, polyimide or a nitride film is formed so as to cover the outer edges of the wiring electrode 5 and the Schottky electrode 4 and the surface of the insulating film 3. An opening 6a is formed in the central portion of the passivation film 6, and the wiring electrode 5 is exposed through the opening 6a, so that the wiring electrode 5 can be electrically connected to the outside.

On the other hand, in the rear surface 1b side of the n ⁺ -type substrate 1, so as to be in contact with the rear surface 1b of the n ⁺ -type substrate 1, for example Ti, Mo, Ni (nickel), and a cathode electrode composed of a W (tungsten) or the like A back electrode 7 is formed. Thereby, SBD10 is comprised.

Further, as a termination structure formed in the outer peripheral region of the SBD 10, the Schottky electrode 4 is formed on the surface layer portion of the n ⁻ -type drift layer 2 so as to extend further radially outward from the outer edge portion of the Schottky electrode 4. The termination structure is configured by forming the p-type RESURF layer 8 so as to be in contact with. The p-type RESURF layer 8 is formed using, for example, Al as an impurity, and is formed with an impurity concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ , for example. By disposing the p-type RESURF layer 8, the electric field can extend over a wide range on the outer periphery of the SBD 10, and the electric field concentration can be relaxed, so that the breakdown voltage can be improved.

In the SiC semiconductor device including the SBD 10 having such a structure, the conductor layer 9 is provided so as to surround the end face of the semiconductor chip. The conductor layer 9 is in contact with the back electrode 7, covers the entire end surfaces of the n ⁺ -type substrate 1 and the n ⁻ -type drift layer 2, and extends to the passivation film 6. The conductor layer 9 is made of, for example, a metal layer, conductive grease, silver paste, or the like, and plays the role of making the potential of the end face of the semiconductor chip the same potential.

  Next, a method for manufacturing the SiC semiconductor device according to the present embodiment will be described. FIG. 2 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG.

First, in the step shown in FIG. 2A, the n ⁻ type drift layer 2 is epitaxially grown on the main surface 1a of the n ⁺ type substrate 1. Subsequently, in the step shown in FIG. 2B, after the mask 11 made of LTO (low-temperature oxide) or the like is disposed, the p-type RESURF layer 8 of the mask 11 is formed in the photolithography etching step. Open the planned area. Then, a p-type resurf layer 8 is formed by ion implantation of a p-type impurity such as Al using the mask 11 and activation by heat treatment or the like.

  Next, in the step shown in FIG. 2C, after the mask 11 is removed, a silicon oxide film is formed by, for example, plasma CVD, and then the insulating film 3 is formed by performing a reflow process. An opening 3a is formed in the insulating film 3 through a lithography / etching process. In the step shown in FIG. 2D, a metal layer composed of Mo or Ti is formed on the insulating film 3 including the inside of the opening 3a, and then the metal layer is patterned to form a Schottky electrode. 4 is formed. Further, a metal layer made of Al or the like is disposed on the surface of the Schottky electrode 4 and the surface of the insulating film 3, and the wiring layer 5 is formed by patterning the metal layer. Further, after forming a passivation film 6 thereon, patterning is performed to form openings 6a and the like.

Thereafter, a metal layer composed of Ni, Ti, Mo, W, or the like is formed on the back surface 1b side of the n ⁺ type substrate 1 to form the back surface electrode 7 and then dicing cut in units of chips. Thereby, a semiconductor chip is formed. After manufacturing the semiconductor chip in this way, the conductor layer 9 is formed by applying a metal layer, conductive grease, silver paste or the like to the end face of the semiconductor chip. For example, after covering the surface side by fixing the surface of the completed semiconductor chip to a jig, a metal layer on the side surface of the semiconductor chip, for example, Ti is 200 nm, Ni is 500 nm, Au is 50 nm in order, a vaporizer or a sputtering device The conductor layer 9 may be formed by vapor deposition. In the case of such a technique, the conductor layer 9 is also formed on the back surface of the semiconductor chip. However, since the back electrode 7 and the conductor layer 9 are connected, there is no problem even if they are formed. Conversely, if a material for the back electrode 7, that is, a material that can be ohmic-connected to the n ⁺ -type substrate 1, the back electrode 7 and the conductor layer 9 can be formed simultaneously.

  With such a manufacturing method, the semiconductor chip constituting the SiC semiconductor device shown in FIG. 1 can be manufactured.

As described above, in the SiC semiconductor device having the structure shown in the present embodiment, the end surfaces of the n ⁺ type substrate 1 and the n ⁻ type drift layer 2 are entirely covered so as to cover the end surface of the semiconductor chip, that is, in contact with the back electrode 7. A conductor layer 9 is formed so as to cover and reach the passivation film 6. For this reason, even if a high voltage is applied to the Schottky electrode 4 and potential deviation is likely to occur at the outer peripheral portion of the semiconductor chip, the potential can be instantaneously made equal by the conductor layer 9. As a result, side surface discharge is less likely to occur, and element breakdown due to side surface discharge can be suppressed.

  In FIG. 2, the case where the conductor layer 9 is formed before the semiconductor chip is mounted on the mounting substrate has been described. However, after the semiconductor chip is mounted on the mounting substrate, a metal layer, conductive grease or A conductor layer 9 made of silver paste or the like may be applied.

(Second Embodiment)
A second embodiment of the present invention will be described. The SiC semiconductor device of the present embodiment is obtained by changing the configuration of the conductor layer 9 with respect to the first embodiment, and the other parts are the same as those of the first embodiment, and therefore only different parts will be described.

FIG. 3 is a cross-sectional view showing a state when a semiconductor chip constituting the SiC semiconductor device including the SBD 10 according to the present embodiment is mounted on the mounting substrate 20. As shown in this figure, in this embodiment, the conductor layer 9 has a two-layer structure. Specifically, a first layer 9 a formed in contact with the back electrode 7, covering the entire end surfaces of the n ⁺ -type substrate 1 and the n ⁻ -type drift layer 2 and reaching the passivation film 6, and the first layer The conductor layer 9 is constituted by the second layer 9 b formed on the surface of the conductor 9. The first layer 9a is made of a metal layer, conductive grease, silver paste, or the like, and is formed by, for example, being applied to the side surface of a semiconductor chip. The second layer 9b is made of, for example, solder, and is formed by wetting and spreading the solder on the surface of the first layer 9a after forming the first layer 9a. The material of the first layer 9a is arbitrary, but if the second layer 9b is made of solder, a material with good solder wettability, for example, a metal containing Au such as a multilayer structure of Ti / Ni / Au Is preferable.

  In this way, the conductor layer 9 can be composed of a plurality of layers. In the semiconductor chip having such a structure, since the back electrode 7 is mounted on the mounting substrate 20 via the solder 21, the first layer 9a is formed of a material having good solder wettability on the end surface of the semiconductor chip. If the soldering is performed so that the solder rises to the surface of the first layer 9a when mounted on the mounting substrate 20, the mounting process and the second layer 9b forming process can be performed simultaneously.

(Other embodiments)
In each of the embodiments described above, the conductor layer 9 is formed so that the end face of the passivation film 6 is entirely covered. However, the end faces of the n ⁺ type substrate 1 and the n ⁻ type drift layer 2 are in contact with at least the back electrode 7. And the interface between the n ⁻ type drift layer 2 and the insulating film 3 or the passivation film 6 may be covered.

  In each of the above embodiments, only the p-type RESURF layer 8 is shown as the termination structure. However, other termination structures, for example, a plurality of p-type guard ring layers are provided so as to further surround the outer periphery of the p-type RESURF layer 8. It may be an arranged structure.

  In each of the above embodiments, the insulating film 3 is disposed below the passivation film 6. However, the insulating film 3 is not necessarily provided, and the Schottky electrode 4 is only provided at a position where the Schottky contact is desired. May be arranged.

  In each of the above embodiments, the SBD 10 is taken as an example of the vertical power element formed in the cell portion (active region). However, the vertical power element is not limited to the SBD 10, and other vertical power elements such as a vertical MOSFET, IGBT, and the like. The present invention can be applied to any structure as long as the surface electrode and the back electrode are formed on the semiconductor chip, such as J-FET.

It is sectional drawing of the semiconductor chip which comprises the SiC semiconductor device provided with SBD concerning 1st Embodiment of this invention. FIG. 3 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG. 1. It is sectional drawing which showed a mode when the semiconductor chip which comprises the SiC semiconductor device provided with SBD concerning 2nd Embodiment of this invention was mounted in the mounting board | substrate. It is typical sectional drawing which showed the mode of the side surface discharge at the time of forming SBD. It is a top surface layout diagram of a SiC semiconductor device showing a portion where a potential is biased.

Explanation of symbols

1 n ⁺ type substrate 1a main surface 1b back surface 2 n ⁻ type drift layer 3 insulating film 3a opening 4 Schottky electrode 5 wiring electrode 6 passivation film 6a opening 7 back electrode 8 p-type resurf layer 9 conductor layer 9a first layer 9b 2nd layer 10 SBD
20 Mounting board

Claims (9)

A substrate (1) having a main surface (1a) and a back surface (1b) and made of silicon carbide;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the main surface (1a) of the substrate (1) and having a lower impurity concentration than the substrate (1);
A semiconductor element (10) formed in a cell portion in the drift layer (2);
On the drift layer (2), surface electrodes (4, 5) electrically connected to the semiconductor element (10);
An opening (6a) that is disposed so as to cover the drift layer (2) in the outer peripheral portion of the cell portion while covering the outer edge portion of the surface electrode (4, 5), and exposes the surface electrode (4, 5). A passivation film (6) provided with
The back surface (1b) of the substrate (1) has a back surface electrode (7) electrically connected to the semiconductor element (10), and is carbonized by being divided into chips to form a semiconductor chip. A silicon semiconductor device,
A conductor layer (9) in contact with the back electrode (7) at the end face of the semiconductor chip, covering the entire end faces of the substrate (1) and the drift layer (2), and reaching the passivation film (6). A silicon carbide semiconductor device comprising:   The silicon carbide semiconductor device according to claim 1, wherein the conductive layer (9) is any one of a metal layer, conductive grease, silver paste, or solder.   The conductor layer (9) is in contact with the back electrode (7), and a first layer (9a) formed on the end surfaces of the substrate (1) and the drift layer (2) and the surface of the passivation film (6). And a second layer (9b) formed on the surface of the first layer (9a). 3. The silicon carbide semiconductor device according to claim 1 or 2, wherein The first layer (9a) is a metal layer,
The silicon carbide semiconductor device according to claim 3, wherein the second layer (9b) is solder. A silicon carbide semiconductor device mounting structure in which the silicon carbide semiconductor device according to any one of claims 1 to 4 is mounted on a mounting substrate (20),
The back electrode (7) is mounted by being soldered to the mounting substrate (20), and the conductor layer (8) is composed of solder by the soldering. Mounting structure of a silicon carbide semiconductor device. A substrate (1) having a main surface (1a) and a back surface (1b) and made of silicon carbide;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the main surface (1a) of the substrate (1) and having a lower impurity concentration than the substrate (1);
A semiconductor element (10) formed in a cell portion in the drift layer (2);
On the drift layer (2), surface electrodes (4, 5) electrically connected to the semiconductor element (10);
A passivation film (6) disposed so as to cover the drift layer (2) in the outer peripheral part of the cell part while covering the outer edge part of the surface electrode (4, 5);
The back surface (1b) of the substrate (1) has a back surface electrode (7) electrically connected to the semiconductor element (10), and is carbonized by being divided into chips to form a semiconductor chip. A method for manufacturing a silicon semiconductor device, comprising:
After the semiconductor chip is divided, the end face of the semiconductor chip is in contact with the back electrode (7), covers the entire end face of the substrate (1) and the drift layer (2), and the passivation film (6 A method for manufacturing a silicon carbide semiconductor device, comprising the step of forming a conductor layer (9) extending to   In the step of forming the conductor layer (9), the surface side of the semiconductor chip (1) on which the passivation film (6) is formed is fixed with a jig to cover the surface side, and then the semiconductor chip The method for manufacturing a silicon carbide semiconductor device according to claim 6, which is a step of applying the conductor layer (9) to an end face of the chip (1).   In the step of forming the conductor layer (9), the surface side of the semiconductor chip (1) on which the passivation film (6) is formed is fixed with a jig to cover the surface side, and then the semiconductor chip The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein the back electrode (7) is formed simultaneously by applying the conductor layer (9) to an end face of the chip (1). Soldering the back electrode (7) to the mounting substrate (20);
The step of forming the conductor layer (9) comprises contacting the back electrode (7) with the substrate (1) and the back electrode (7) before soldering the back electrode (7) to the mounting substrate (20). Forming a first layer (9a) formed on the end face of the drift layer (2) and the surface of the passivation film (6), and soldering the back electrode (7) to the mounting substrate (20); A step of forming a second layer (9b) by allowing the solder to spread on the surface of the first layer (9a) when attaching the conductive layer (9) to the first layer (9a). 9. The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein the structure is provided with (9 a) and the second layer (9 b).

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