JPWO2013099050A1 - Silicon carbide semiconductor device manufacturing method, silicon carbide semiconductor device, and silicon carbide semiconductor module - Google Patents

Silicon carbide semiconductor device manufacturing method, silicon carbide semiconductor device, and silicon carbide semiconductor module Download PDF

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JPWO2013099050A1
JPWO2013099050A1 JP2013551179A JP2013551179A JPWO2013099050A1 JP WO2013099050 A1 JPWO2013099050 A1 JP WO2013099050A1 JP 2013551179 A JP2013551179 A JP 2013551179A JP 2013551179 A JP2013551179 A JP 2013551179A JP WO2013099050 A1 JPWO2013099050 A1 JP WO2013099050A1
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silicon carbide
carbide semiconductor
semiconductor element
semiconductor device
silicon
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JP5840228B2 (en
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隆夫 沢田
隆夫 沢田
三宅 英孝
英孝 三宅
洋介 中西
洋介 中西
末廣 善幸
善幸 末廣
善夫 藤井
善夫 藤井
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Mitsubishi Electric Corp
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23HWORKING OF METAL BY THE ACTION OF A HIGH CONCENTRATION OF ELECTRIC CURRENT ON A WORKPIECE USING AN ELECTRODE WHICH TAKES THE PLACE OF A TOOL; SUCH WORKING COMBINED WITH OTHER FORMS OF WORKING OF METAL
    • B23H7/00Processes or apparatus applicable to both electrical discharge machining and electrochemical machining
    • B23H7/02Wire-cutting
    • B23H7/04Apparatus for supplying current to working gap; Electric circuits specially adapted therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66053Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23HWORKING OF METAL BY THE ACTION OF A HIGH CONCENTRATION OF ELECTRIC CURRENT ON A WORKPIECE USING AN ELECTRODE WHICH TAKES THE PLACE OF A TOOL; SUCH WORKING COMBINED WITH OTHER FORMS OF WORKING OF METAL
    • B23H9/00Machining specially adapted for treating particular metal objects or for obtaining special effects or results on metal objects
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608Silicon carbide

Abstract

端側面に導電層を、正確かつ簡便に形成した炭化珪素半導体素子を得る。炭化珪素半導体デバイス基板1a上に形成された複数の半導体デバイス18を放電加工法によりそれぞれの炭化珪素半導体素子に切り出し、炭化珪素半導体素子の端側面に炭化珪素半導体デバイス基板1aの炭化珪素基体11の体積抵抗率よりも低い体積抵抗率を有する導電層17を形成する工程を含む。A silicon carbide semiconductor element in which a conductive layer is accurately and simply formed on the end surface is obtained. A plurality of semiconductor devices 18 formed on silicon carbide semiconductor device substrate 1a are cut into respective silicon carbide semiconductor elements by an electric discharge machining method, and silicon carbide substrate 11 of silicon carbide semiconductor device substrate 1a is formed on an end side surface of the silicon carbide semiconductor element. Forming a conductive layer 17 having a volume resistivity lower than the volume resistivity.

Description

本発明は、炭化珪素半導体素子の製造方法及び炭化珪素半導体素子及び炭化珪素半導体モジュールに関するものであり、詳しくは放電破壊に対する信頼性の高い炭化珪素半導体素子の製造方法及び炭化珪素半導体素子及び炭化珪素半導体モジュールに関するものである。   The present invention relates to a method for manufacturing a silicon carbide semiconductor element, a silicon carbide semiconductor element, and a silicon carbide semiconductor module, and more specifically, a method for manufacturing a silicon carbide semiconductor element having high reliability against discharge breakdown, and a silicon carbide semiconductor element and silicon carbide. The present invention relates to a semiconductor module.

炭化珪素半導体素子では、高電圧が印加されるため、炭化珪素半導体素子の端側面に電荷が蓄積されやすく、蓄積された電荷が沿面放電を引き起こして素子が破壊されることが知られている。   In a silicon carbide semiconductor element, since a high voltage is applied, it is known that charges are easily accumulated on the end side surface of the silicon carbide semiconductor element, and the accumulated charges cause creeping discharge and the element is destroyed.

この沿面放電を防ぐために、炭化珪素半導体素子の表面に金属膜を形成して、炭化珪素半導体素子に高電圧が印加され、炭化珪素半導体素子の端側面等に蓄積された電荷の局在化を防ぐ方法(例えば、特許文献1)が提案されている。   In order to prevent this creeping discharge, a metal film is formed on the surface of the silicon carbide semiconductor element, and a high voltage is applied to the silicon carbide semiconductor element to localize charges accumulated on the side surfaces of the silicon carbide semiconductor element. A prevention method (for example, Patent Document 1) has been proposed.

特開2009−224641号公報JP 2009-224641 A

沿面放電を防ぐために、炭化珪素半導体素子表面に金属膜等の導電層を形成する場合、炭化珪素半導体素子の4つの端側面にも導電層を形成することが必要である。しかし、切断された炭化珪素半導体素子の厚みは薄く、通常350μm以下である。この炭化珪素半導体素子の端側面に、導電ペースト、金属蒸着膜、半田等からなる導電層を、正確かつ簡便に形成することは非常に困難であるという問題がある。   In order to prevent creeping discharge, when a conductive layer such as a metal film is formed on the surface of the silicon carbide semiconductor element, it is necessary to form the conductive layer also on the four side surfaces of the silicon carbide semiconductor element. However, the thickness of the cut silicon carbide semiconductor element is thin and is usually 350 μm or less. There is a problem that it is very difficult to accurately and simply form a conductive layer made of a conductive paste, a metal vapor deposition film, solder, or the like on the side surface of the silicon carbide semiconductor element.

本発明は、このような課題を解決するためになされたもので、炭化珪素半導体素子の端側面に導電層を、正確かつ簡便に形成し、炭化珪素半導体素子の沿面放電を防ぎ、信頼性の高い炭化珪素半導体素子の製造方法及び炭化珪素半導体素子及び炭化珪素半導体モジュールを得ることを目的としている。   The present invention has been made to solve such a problem, and a conductive layer is accurately and simply formed on the end side surface of a silicon carbide semiconductor element to prevent creeping discharge of the silicon carbide semiconductor element, thereby improving reliability. An object of the present invention is to obtain a high silicon carbide semiconductor element manufacturing method, a silicon carbide semiconductor element, and a silicon carbide semiconductor module.

本発明の炭化珪素半導体素子の製造方法は、炭化珪素半導体デバイス基板上に形成された複数の半導体デバイスを放電加工法によりそれぞれの炭化珪素半導体素子に切り出し、炭化珪素半導体素子の端側面に炭化珪素半導体デバイス基板の炭化珪素基体の体積抵抗率よりも低い体積抵抗率を有する導電層を形成する工程を含むものである。   A method for manufacturing a silicon carbide semiconductor element of the present invention includes cutting a plurality of semiconductor devices formed on a silicon carbide semiconductor device substrate into respective silicon carbide semiconductor elements by an electric discharge machining method, and forming silicon carbide on an end side surface of the silicon carbide semiconductor element. The method includes a step of forming a conductive layer having a volume resistivity lower than that of the silicon carbide substrate of the semiconductor device substrate.

また、本発明の炭化珪素半導体素子は、炭化珪素半導体素子の端側面に炭化珪素基体の体積抵抗率よりも低い体積抵抗率を有する珪素欠乏層を備えたものである。   Moreover, the silicon carbide semiconductor element of this invention is equipped with the silicon deficiency layer which has a volume resistivity lower than the volume resistivity of a silicon carbide base | substrate at the end side surface of a silicon carbide semiconductor element.

本発明の製造方法を用いることにより、炭化珪素半導体デバイス基板を切断して作製した炭化珪素半導体素子の端側面に炭化珪素基体の体積抵抗率よりも低い体積抵抗率を有する導電層を正確かつ簡便に形成することができ、炭化珪素半導体素子に高電圧を印加した場合に見られる沿面放電を防止し、信頼性の高い炭化珪素半導体素子の製造方法を得ることができる。   By using the manufacturing method of the present invention, a conductive layer having a volume resistivity lower than the volume resistivity of the silicon carbide substrate is accurately and simply formed on the end side surface of the silicon carbide semiconductor element produced by cutting the silicon carbide semiconductor device substrate. The creeping discharge seen when a high voltage is applied to the silicon carbide semiconductor element can be prevented, and a highly reliable silicon carbide semiconductor element manufacturing method can be obtained.

また、本発明の炭化珪素半導体素子は、その端側面に炭化珪素基体の体積抵抗率よりも低い体積抵抗率を有する珪素欠乏層を有するので、沿面放電の発生が抑制された信頼性の高い炭化珪素半導体素子を得ることができる。さらに副次的な効果として、放電加工により炭化珪素半導体素子の端側面に形成した導電層の表面粗さを0.1μm以上10μm以下とすることで、炭化珪素半導体モジュール作製において炭化珪素半導体素子とそれを覆う樹脂との密着性の向上した炭化珪素半導体素子を得ることができる。   In addition, the silicon carbide semiconductor element of the present invention has a silicon-deficient layer having a volume resistivity lower than that of the silicon carbide substrate on the side surface of the silicon carbide semiconductor element, so that the occurrence of creeping discharge is suppressed and the carbonization is highly reliable. A silicon semiconductor element can be obtained. Further, as a secondary effect, the surface roughness of the conductive layer formed on the end side surface of the silicon carbide semiconductor element by electric discharge machining is 0.1 μm or more and 10 μm or less. A silicon carbide semiconductor element having improved adhesion to the resin covering it can be obtained.

実施の形態1で用いたワイヤーカット放電加工機の概略図である。1 is a schematic diagram of a wire cut electric discharge machine used in Embodiment 1. FIG. 実施の形態1におけるショットキーバリアダイオードの断面模式図である。2 is a schematic cross-sectional view of a Schottky barrier diode in Embodiment 1. FIG. 実施の形態2で用いたマルチワイヤーカット放電加工機の概略図である。It is the schematic of the multi wire cut electric discharge machine used in Embodiment 2. FIG. 実施の形態3における炭化珪素半導体デバイス基板の放電加工時の表面冷却機構を示す上面模式図である。FIG. 12 is a schematic top view showing a surface cooling mechanism during electric discharge machining of a silicon carbide semiconductor device substrate in a third embodiment. 実施の形態3における炭化珪素半導体デバイス基板の放電加工時の表面冷却機構を示す断面模式図である。FIG. 11 is a schematic cross sectional view showing a surface cooling mechanism during electric discharge machining of a silicon carbide semiconductor device substrate in the third embodiment. (a)は、実施の形態4における炭化珪素半導体デバイス基板とワイヤー線と間に印加したパルス電圧特性、(b)はその条件で加工した時の表面粗さの模式図である。(A) is the pulse voltage characteristic applied between the silicon carbide semiconductor device substrate and wire wire in Embodiment 4, (b) is a schematic diagram of the surface roughness when processed on the conditions. 実施の形態4で示す条件で作製した炭化珪素半導体デバイス基板から炭化珪素半導体素子を切断した際の、炭化珪素半導体素子の端側面に形成された導電層表面のAFM(Atomic force microscope)像である。6 is an AFM (Atomic force microscope) image of the surface of a conductive layer formed on an end side surface of a silicon carbide semiconductor element when the silicon carbide semiconductor element is cut from a silicon carbide semiconductor device substrate manufactured under the conditions shown in Embodiment 4. .

実施の形態の説明及び各図において、同一の符号を付した部分は、同一又は相当する部分を示すものである。また、実施の形態において、炭化珪素半導体デバイス基板とは、炭化珪素ウエハ基板にダイオード、トランジスタ等の半導体デバイスを形成した状態のものを示し、炭化珪素半導体素子とは、炭化珪素半導体デバイス基板から切り出された半導体デバイスあって、単独で電子部品としての機能を有するものを示している。また、炭化珪素半導体モジュールとは、1個または複数の炭化珪素半導体素子と、必要に応じて、その他の電子部品とを合わせて、動作、機能する状態としたものを示している。なお、炭化珪素半導体素子としては、ショットキーバリアダイオード等の各種ダイオードであっても良く、MOSFET(電界効果トランジスタ)等の各種トランジスタ、さらにはそれらの半導体素子の組み合わせであっても良いことは言うまでも無い。   In the description of the embodiments and the respective drawings, the portions denoted by the same reference numerals indicate the same or corresponding portions. In the embodiment, the silicon carbide semiconductor device substrate refers to a silicon carbide wafer substrate in which semiconductor devices such as diodes and transistors are formed, and the silicon carbide semiconductor element is cut out from the silicon carbide semiconductor device substrate. 1 shows a semiconductor device having a function as an electronic component by itself. In addition, the silicon carbide semiconductor module indicates a state in which one or a plurality of silicon carbide semiconductor elements are combined with other electronic components as necessary to operate and function. In addition, as a silicon carbide semiconductor element, various diodes, such as a Schottky barrier diode, may be sufficient as various transistors, such as MOSFET (field effect transistor), and also the combination of those semiconductor elements. Not too long.

実施の形態1.
<炭化珪素半導体デバイス基板の切断>
図1を用いて、本実施の形態における炭化珪素半導体デバイス基板1aの切断工程を説明する。図1は、実施の形態1で用いたワイヤーカット放電加工機の概略図である。
Embodiment 1 FIG.
<Cutting of silicon carbide semiconductor device substrate>
The cutting process of silicon carbide semiconductor device substrate 1a in the present embodiment will be described using FIG. FIG. 1 is a schematic view of the wire cut electric discharge machine used in the first embodiment.

炭化珪素半導体デバイス基板1a上に半導体デバイスが複数個形成され、その後に放電加工法を用いて炭化珪素半導体デバイス基板1aを切断し、個々の炭化珪素半導体素子が切り出される。本実施の形態では炭化珪素ショットキーバリアダイオードを炭化珪素半導体デバイス基板1a上に形成し、切り出して炭化珪素ショットキーバリアダイオード素子を得た。炭化珪素ショットキーバリアダイオードの構造は後述する。   A plurality of semiconductor devices are formed on silicon carbide semiconductor device substrate 1a, and thereafter, silicon carbide semiconductor device substrate 1a is cut using an electric discharge machining method to cut out individual silicon carbide semiconductor elements. In the present embodiment, a silicon carbide Schottky barrier diode was formed on silicon carbide semiconductor device substrate 1a and cut out to obtain a silicon carbide Schottky barrier diode element. The structure of the silicon carbide Schottky barrier diode will be described later.

図1に示すように、本実施の形態においては、シングルワイヤー型のワイヤーカット放電加工機を用いた。ワイヤーカット放電加工機は、ワイヤーガイド2aにかけられたワイヤー線3a、加工対象物を載せX−Y面内での移動が可能なステージ4a、ステージを移動させ切断位置を変化させるステージ制御部5a、パルス電圧をワイヤー線に印加する加工電源6a、ワイヤー線の送りを制御するワイヤー制御部7a、及び放電加工の工程全体を制御する放電加工制御部8aから構成されている。   As shown in FIG. 1, in the present embodiment, a single wire type wire cut electric discharge machine is used. The wire-cut electric discharge machine has a wire wire 3a hung on a wire guide 2a, a stage 4a that can be moved in an XY plane, a stage controller 5a that moves the stage and changes the cutting position, It comprises a machining power source 6a for applying a pulse voltage to the wire, a wire controller 7a for controlling the wire wire feed, and an electric discharge machining controller 8a for controlling the entire electric discharge machining process.

炭化珪素ショットキーバリアダイオードが複数個形成された炭化珪素半導体デバイス基板1aが、導電性のダイシングテープを用いてステージ4aに固定される。ワイヤー線3aと炭化珪素半導体デバイス基板1aとに加工電源6aからパルス電圧が印加され、切断が開始される。炭化珪素半導体デバイス基板1aの端部から切断し、ステージ制御部5aによりステージ4aを移動させて炭化珪素半導体デバイス基板1aが切断され、炭化珪素半導体素子が切り出される。   Silicon carbide semiconductor device substrate 1a on which a plurality of silicon carbide Schottky barrier diodes are formed is fixed to stage 4a using a conductive dicing tape. A pulse voltage is applied from the machining power supply 6a to the wire 3a and the silicon carbide semiconductor device substrate 1a to start cutting. Cut from the end of silicon carbide semiconductor device substrate 1a, stage 4a is moved by stage control portion 5a, silicon carbide semiconductor device substrate 1a is cut, and a silicon carbide semiconductor element is cut out.

本実施の形態においては、放電加工機のワイヤー線3aは、厚さ1μmの黄銅被覆した直径50μmのスチール線が用いられる。また、ワイヤー線3aに印加されるパルス電圧は、ワイヤー線側を(−)、炭化珪素半導体デバイス基板1a側を(+)として接続されて印加された。パルス幅1μ秒(25%duty)、80Vのパルス電圧を印加し、ワイヤー線3aの送り速度は0.5mm/分で、純水中で切断を行なった。   In the present embodiment, the wire wire 3a of the electric discharge machine is a steel wire having a diameter of 50 μm and coated with brass having a thickness of 1 μm. Moreover, the pulse voltage applied to the wire line 3a was applied by connecting the wire line side as (−) and the silicon carbide semiconductor device substrate 1a side as (+). The pulse width was 1 μsec (25% duty), a pulse voltage of 80 V was applied, the feed rate of the wire 3a was 0.5 mm / min, and cutting was performed in pure water.

<炭化珪素ショットキーバリアダイオードの構成>
図2を用いて、本実施の形態における炭化珪素ショットキーバリアダイオードの構成を説明する。図2は、実施の形態1におけるショットキーバリアダイオードの断面模式図である。
<Configuration of silicon carbide Schottky barrier diode>
The configuration of the silicon carbide Schottky barrier diode in the present embodiment will be described with reference to FIG. FIG. 2 is a schematic cross-sectional view of the Schottky barrier diode in the first embodiment.

n型で低抵抗の炭化珪素基板9上に、n型の炭化珪素エピタキシャル層10が形成される。本実施の形態においては、この炭化珪素基板9と炭化珪素エピタキシャル層10を合わせて、炭化珪素基体11と呼ぶ。ここで用いた炭化珪素基板9は、結晶構造が4Hの炭化珪素基板であり、六方晶の(0001)面が炭化珪素基板表面から8°あるいは4°傾いた結晶構造となっている。   N-type silicon carbide epitaxial layer 10 is formed on n-type and low-resistance silicon carbide substrate 9. In the present embodiment, silicon carbide substrate 9 and silicon carbide epitaxial layer 10 are collectively referred to as silicon carbide substrate 11. The silicon carbide substrate 9 used here is a silicon carbide substrate having a crystal structure of 4H, and has a crystal structure in which the hexagonal (0001) plane is inclined by 8 ° or 4 ° from the surface of the silicon carbide substrate.

この炭化珪素エピタキシャル層10の表面に、p型不純物として例えばアルミニウム(Al)を含有するイオン注入領域12がリング状に形成される。また、このイオン注入領域12に囲まれた炭化珪素エピタキシャル層10の表面には、周囲がイオン注入層12の表面の一部を覆うようにショットキー電極13が形成され、このショットキー電極13上にアノード電極14が形成される。   On the surface of silicon carbide epitaxial layer 10, an ion implantation region 12 containing, for example, aluminum (Al) as a p-type impurity is formed in a ring shape. A Schottky electrode 13 is formed on the surface of the silicon carbide epitaxial layer 10 surrounded by the ion implantation region 12 so that the periphery covers a part of the surface of the ion implantation layer 12. An anode electrode 14 is formed on the substrate.

さらに、炭化珪素エピタキシャル層10の表面を覆うように、ポリイミドからなる絶縁層15が形成される。   Further, an insulating layer 15 made of polyimide is formed so as to cover the surface of silicon carbide epitaxial layer 10.

炭化珪素基板9の裏面、つまりn型の炭化珪素エピタキシャル層10を形成した面の反対面にはカソード電極16が形成される。ここでカソード電極16はNi(ニッケル)が用いられ、電極形成後約1000℃に加熱してシリサイド化される。   Cathode electrode 16 is formed on the back surface of silicon carbide substrate 9, that is, the surface opposite to the surface on which n-type silicon carbide epitaxial layer 10 is formed. Here, Ni (nickel) is used for the cathode electrode 16, and after forming the electrode, it is heated to about 1000 ° C. to be silicided.

さらに、本実施の形態の炭化珪素ショットキーバリアダイオードの炭化珪素半導体素子では、炭化珪素基体11の4つの端側面、つまり放電加工機により切断した4つの面に導電層17が形成される。   Furthermore, in the silicon carbide semiconductor element of the silicon carbide Schottky barrier diode of the present embodiment, conductive layer 17 is formed on the four end side surfaces of silicon carbide substrate 11, that is, the four surfaces cut by the electric discharge machine.

<導電層について>
放電加工機により切断した炭化珪素ショットキーバリアダイオードの炭化珪素半導体素子の端側面に形成された導電層17の体積抵抗率は、放電加工機の切断条件により変化するが、主に2〜7Ωcmであり、炭化珪素基体11を構成する炭化珪素基板9や炭化珪素エピタキシャル層10と比べ非常に低抵抗であった。また導電層17の膜厚は15μmであった。
<About conductive layer>
Although the volume resistivity of the conductive layer 17 formed on the side surface of the silicon carbide semiconductor element of the silicon carbide Schottky barrier diode cut by the electric discharge machine varies depending on the cutting conditions of the electric discharge machine, it is mainly 2-7 Ωcm. In other words, the resistance was very low as compared with the silicon carbide substrate 9 and the silicon carbide epitaxial layer 10 constituting the silicon carbide substrate 11. The film thickness of the conductive layer 17 was 15 μm.

また、炭化珪素半導体素子の端側面に形成された導電層17は、炭化珪素基板9や炭化珪素エピタキシャル層10に比べ、珪素元素の比率が低く、炭素リッチ層、言い換えれば、珪素欠乏層であり、結晶構造も端側面以外の炭化珪素が六方晶の4Hであるが、この低抵抗の珪素欠乏層は炭化珪素基板9や炭化珪素エピタキシャル層10よりも結晶性が低下していることが確認された。   Conductive layer 17 formed on the side surface of the silicon carbide semiconductor element has a lower silicon element ratio than silicon carbide substrate 9 and silicon carbide epitaxial layer 10 and is a carbon-rich layer, in other words, a silicon-deficient layer. The crystal structure of the silicon carbide other than the end face is hexagonal 4H, but it has been confirmed that the low resistance silicon-deficient layer has lower crystallinity than the silicon carbide substrate 9 and the silicon carbide epitaxial layer 10. It was.

導電層17についての以上の検討の結果、放電加工により切断した炭化珪素半導体素子の端側面に形成された導電層17は、低抵抗の珪素欠乏層であることが分かった。   As a result of the above examination on the conductive layer 17, it was found that the conductive layer 17 formed on the end side surface of the silicon carbide semiconductor element cut by the electric discharge machining is a low-resistance silicon-deficient layer.

この放電加工法による切断工程においては、切断部分の炭化珪素は非常に高温に加熱され、溶融する。さらに加熱されると、炭素と珪素を比較すると珪素の沸点の方が低いため、珪素が優先的に気化され、炭素は気化することなく溶融状態で残存すると考えられる。   In the cutting process by this electric discharge machining method, silicon carbide in the cut portion is heated to a very high temperature and melted. When heated further, the boiling point of silicon is lower when carbon and silicon are compared, so that silicon is preferentially vaporized, and carbon is considered to remain in a molten state without being vaporized.

この状態で、炭化珪素ショットキーバリアダイオードの炭化珪素半導体素子が切断され、冷却されると、炭化珪素半導体素子の端側部には通常の炭化珪素と比べ、珪素が欠乏するため、炭素リッチとなった低抵抗の珪素欠乏層が形成されたと考えられる。   In this state, when the silicon carbide semiconductor element of the silicon carbide Schottky barrier diode is cut and cooled, the end side portion of the silicon carbide semiconductor element is deficient in silicon as compared with normal silicon carbide. It is thought that the low-resistance silicon-deficient layer was formed.

<低抵抗の珪素欠乏層の効果>
以上のように、炭化珪素半導体素子の端側部に炭化珪素基体の体積抵抗率よりも低い体積抵抗率を有する珪素欠乏層(導電層17)を有する、炭化珪素半導体デバイス基板1aから放電加工法を用いて切り出した炭化珪素ショットキーバリアダイオードの炭化珪素半導体素子は、高電圧を印加した場合でも沿面放電を生じることがなく、放電破壊を生じない高い信頼性を示した。
<Effect of low resistance silicon-deficient layer>
As described above, from the silicon carbide semiconductor device substrate 1a having the silicon deficient layer (conductive layer 17) having a volume resistivity lower than the volume resistivity of the silicon carbide substrate at the end side portion of the silicon carbide semiconductor element, the electric discharge machining method is performed. The silicon carbide semiconductor element of the silicon carbide Schottky barrier diode cut out by using no shows creeping discharge even when a high voltage is applied, and exhibits high reliability without causing discharge breakdown.

さらに、炭化珪素半導体デバイス基板1aから放電加工法を用いて切り出した炭化珪素半導体素子をパッケージ加工し、高電圧を印加して評価しても同様に放電破壊を生じない高い信頼性が得られた。   Furthermore, even when a silicon carbide semiconductor element cut out from the silicon carbide semiconductor device substrate 1a by using an electric discharge machining method is packaged and evaluated by applying a high voltage, high reliability that does not cause discharge breakdown is obtained. .

この導電層17である炭化珪素基体の体積抵抗率よりも低い体積抵抗率を有する珪素欠乏層は、放電加工機により切断する工程中に形成されるため、切断面、つまり炭化珪素半導体素子の端側面に正確に形成することができ、新たな工程を必要としないので簡便に炭化珪素半導体素子の高電圧印加時の沿面放電を防止することができ、高い信頼性を得ることができる。   Since the silicon deficient layer having a volume resistivity lower than the volume resistivity of the silicon carbide substrate, which is the conductive layer 17, is formed during the step of cutting by the electric discharge machine, the cut surface, that is, the end of the silicon carbide semiconductor element is formed. Since it can be accurately formed on the side surface and a new process is not required, creeping discharge when a high voltage is applied to the silicon carbide semiconductor element can be easily prevented, and high reliability can be obtained.

本実施の形態では、ワイヤー線3aの直径50μmとしたが、特に限定するものではなく、直径25μmから500μmのワイヤー線3aであれば用いることができる。ただし、細いワイヤー線では、十分な電流を流すことができず、加工速度が非常に遅くなる場合がある。また太い場合は、一般に切断する時の加工幅(溶融し除去される幅)はワイヤー線の直径よりやや大きくなるため、細かい炭化珪素半導体素子の切り出しには不向きである。このような観点から、ワイヤー線3aの直径は、50μmから100μmが好ましい。   In the present embodiment, the wire wire 3a has a diameter of 50 μm, but is not particularly limited, and any wire wire 3a having a diameter of 25 μm to 500 μm can be used. However, with a thin wire, a sufficient current cannot flow, and the processing speed may be very slow. In the case of being thick, the processing width (the width that is melted and removed) when cutting is generally slightly larger than the diameter of the wire, and is not suitable for cutting out fine silicon carbide semiconductor elements. From such a viewpoint, the diameter of the wire 3a is preferably 50 μm to 100 μm.

本実施の形態では、パルス電圧は80V、パルス幅1μ秒(25%duty)、ワイヤー送り速度0.5mm/分としたが、特に限定されるものではなく、切断する炭化珪素半導体デバイス基板1aの特性、厚み等に基づいて定めることができる。具体的には、パルス電圧50V〜300V、パルス幅0.1〜10μ秒、10〜80%duty、ワイヤー送り速度0.1mm〜10mm/分の範囲で切断の状況に応じて、調整することが好ましい。   In the present embodiment, the pulse voltage is 80 V, the pulse width is 1 μsec (25% duty), and the wire feed speed is 0.5 mm / min. However, the present invention is not particularly limited, and the silicon carbide semiconductor device substrate 1a to be cut It can be determined based on characteristics, thickness, and the like. Specifically, the pulse voltage can be adjusted in the range of 50 V to 300 V, pulse width of 0.1 to 10 μs, 10 to 80% duty, and wire feed speed of 0.1 mm to 10 mm / min according to the cutting condition. preferable.

また、本実施の形態では、ショットキー電極13はTiが用いられたが、特に限定するものではなく、Mo等を用いることができる。また、アノード電極14にはAlが用いられたが、特に限定するものではなく、Cu、Al/Ni/Au等の金属膜を用いることができる。   In this embodiment, Ti is used for the Schottky electrode 13, but it is not particularly limited, and Mo or the like can be used. Further, although Al is used for the anode electrode 14, it is not particularly limited, and a metal film such as Cu or Al / Ni / Au can be used.

さらに、炭化珪素エピタキシャル層10の表面を覆う絶縁膜15はポリイミドを用いたが、特に限定するものではなく、絶縁性を有し、炭化珪素基板面に形成できるものであれば良く、SiO、SOG(Spin on Glass)等の無機膜でも用いることができる。Furthermore, the insulating film 15 covering the surface of the silicon carbide epitaxial layer 10 is polyimide was used, not particularly limited, has an insulating property, as long as it can be formed into a silicon carbide substrate surface, SiO 2, An inorganic film such as SOG (Spin on Glass) can also be used.

炭化珪素半導体素子の端側部に炭化珪素基体の体積抵抗率よりも低い体積抵抗率を有する珪素欠乏層(導電層17)の体積抵抗率は特に限定するものではないが、7Ωcm以下であることが好ましい。7Ωcm以下では蓄積した電荷を局在化させない効果が顕著であり、炭化珪素半導体素子の沿面放電を確実に防止することができる。   The volume resistivity of the silicon-deficient layer (conductive layer 17) having a volume resistivity lower than the volume resistivity of the silicon carbide substrate at the end side portion of the silicon carbide semiconductor element is not particularly limited, but is 7 Ωcm or less. Is preferred. If it is 7 Ωcm or less, the effect of not localizing the accumulated charge is remarkable, and creeping discharge of the silicon carbide semiconductor element can be reliably prevented.

炭化珪素半導体素子の端側部の、炭化珪素基体の体積抵抗率よりも低い体積抵抗率を有する珪素欠乏層(導電層17)の膜厚は特に限定するものではないが、蓄積した電荷を局在化させず、製造工程での傷、衝撃等によっても低抵抗の珪素欠乏層(導電層17)が安定である観点から、10μm以上、20μm以下であることが好ましい。   The film thickness of the silicon-deficient layer (conductive layer 17) having a volume resistivity lower than the volume resistivity of the silicon carbide substrate at the end side portion of the silicon carbide semiconductor element is not particularly limited. From the viewpoint that the low-resistance silicon-deficient layer (conductive layer 17) is stable due to scratches, impacts, and the like in the manufacturing process, it is preferably 10 μm or more and 20 μm or less.

また、本実施の形態においては、炭化珪素半導体デバイス基板1a上に作成した炭化珪素半導体素子である炭化珪素ショットキーバリアダイオードを切断した例を示したが、その他の炭化珪素半導体素子である、電界効果半導体(MOSFET等)、絶縁ゲートバイポーラ半導体(IGBT)であっても同様の効果、具体的には、正確かつ簡便に低抵抗の珪素欠乏層を炭化珪素半導体素子の端側面に作成することができ、高電圧印加時の沿面放電を防止し、この炭化珪素半導体素子を用いた炭化珪素半導体モジュールは高い信頼性を得ることができる。   In the present embodiment, an example is shown in which a silicon carbide Schottky barrier diode, which is a silicon carbide semiconductor element created on silicon carbide semiconductor device substrate 1a, is cut, but an electric field that is another silicon carbide semiconductor element. Even if it is an effect semiconductor (MOSFET etc.) and an insulated gate bipolar semiconductor (IGBT), the same effect, specifically, a low-resistance silicon-deficient layer can be accurately and easily formed on the end side surface of the silicon carbide semiconductor element. The creeping discharge at the time of applying a high voltage can be prevented, and the silicon carbide semiconductor module using the silicon carbide semiconductor element can obtain high reliability.

実施の形態2
<炭化珪素半導体デバイス基板の切断>
図3を用いて、本実施の形態における炭化珪素半導体デバイス基板1bの切断工程を説明する。図3は、実施の形態2で用いたマルチワイヤーカット放電加工機の概略図である。
Embodiment 2
<Cutting of silicon carbide semiconductor device substrate>
The cutting process of silicon carbide semiconductor device substrate 1b in the present embodiment will be described using FIG. FIG. 3 is a schematic view of the multi-wire cut electric discharge machine used in the second embodiment.

実施の形態1においては、1本のワイヤー線3aを用いた放電加工機を用いたが、本実施の形態においては、より炭化珪素半導体デバイス基板1bから炭化珪素半導体素子を効率的に切り出すことができるよう、マルチワイヤー方式の放電加工機が用いられる。   In the first embodiment, an electric discharge machine using one wire 3a is used. However, in this embodiment, a silicon carbide semiconductor element can be more efficiently cut out from silicon carbide semiconductor device substrate 1b. A multi-wire electric discharge machine is used so that it can do.

放電加工制御部8bは、ステージ制御部5b、加工電源6b、ワイヤー制御部7bに信号を送り、それぞれステージ制御部5bによりステージの高さ、位置を、加工電源6bによりワイヤー線3bとステージ4b間に印加するパルス電圧、パルス幅等を、ワイヤー制御部7bによりワイヤー線3bの送り速度を、制御用コンピュータ(図示せず)に入力された加工条件等に従って調整し制御する。   The electric discharge machining control unit 8b sends signals to the stage control unit 5b, the machining power source 6b, and the wire control unit 7b. The wire control unit 7b adjusts and controls the feed voltage of the wire 3b according to the processing conditions and the like input to a control computer (not shown).

まず、ステージ4b上に実施の形態1と同様の炭化珪素ショットキーバリアダイオードを形成した炭化珪素半導体デバイス基板1bが導電性のダイシング保護テープ上に貼り付けて固定される。ステージ4bの高さを調整し、炭化珪素半導体デバイス基板1bとワイヤー線3bが、所定の間隙を保つように調整する。   First, silicon carbide semiconductor device substrate 1b in which a silicon carbide Schottky barrier diode similar to that of the first embodiment is formed on stage 4b is bonded and fixed on a conductive dicing protective tape. The height of the stage 4b is adjusted so that the silicon carbide semiconductor device substrate 1b and the wire wire 3b maintain a predetermined gap.

ワイヤーガイド2bに掛けたワイヤー線3bを一定の送り速度で移動させながら、ワイヤー線3bにパルス電圧を印加し、炭化珪素半導体デバイス基板1bの切断を行なう。炭化珪素半導体デバイス基板1bの表面が溶融し、切断されると、炭化珪素半導体デバイス基板1bとワイヤー線3bの間隙を保持するように、ステージ4bの高さを逐次調整する。この工程を継続して繰り返し、炭化珪素半導体デバイス基板1bの切断を行ない、炭化珪素ショットキーバリアダイオードが個々の炭化珪素半導体素子ごとに切り出される。   While moving wire wire 3b hung on wire guide 2b at a constant feed rate, a pulse voltage is applied to wire wire 3b to cut silicon carbide semiconductor device substrate 1b. When the surface of silicon carbide semiconductor device substrate 1b is melted and cut, the height of stage 4b is sequentially adjusted so as to maintain the gap between silicon carbide semiconductor device substrate 1b and wire wire 3b. This process is continuously repeated to cut silicon carbide semiconductor device substrate 1b, and a silicon carbide Schottky barrier diode is cut out for each individual silicon carbide semiconductor element.

<炭化珪素ショットキーバリアダイオードの構成等>
切り出した炭化珪素ショットキーバリアダイオードの炭化珪素半導体素子は、実施の形態1と同様に図2に示した構成であり、切断面には導電層17である低抵抗の珪素欠乏層が形成される。この低抵抗の珪素欠乏層の体積低効率は5Ωcm、膜厚は約15μmであった。
<Configuration of silicon carbide Schottky barrier diode, etc.>
The silicon carbide semiconductor element of the cut silicon carbide Schottky barrier diode has the configuration shown in FIG. 2 as in the first embodiment, and a low-resistance silicon-deficient layer, which is conductive layer 17, is formed on the cut surface. . This low-resistance silicon-deficient layer had a volume low efficiency of 5 Ωcm and a film thickness of about 15 μm.

<低抵抗の珪素欠乏層の効果>
以上のように、その端側部に導電層17である低抵抗の珪素欠乏層を有する、炭化珪素半導体デバイス基板1bからマルチワイヤーカット放電加工機を用いて切り出した炭化珪素半導体素子である炭化珪素ショットキーバリアダイオードは、高電圧を印加した場合でも沿面放電を生じることがなく、高い信頼性を示した。
<Effect of low resistance silicon-deficient layer>
As described above, silicon carbide, which is a silicon carbide semiconductor element cut out from a silicon carbide semiconductor device substrate 1b using a multi-wire cut electric discharge machine, having a low-resistance silicon-deficient layer as the conductive layer 17 on the end side portion thereof. The Schottky barrier diode did not cause creeping discharge even when a high voltage was applied, and showed high reliability.

さらに、炭化珪素半導体デバイス基板1bから放電加工法を用いて切り出した炭化珪素半導体素子を用いた炭化珪素半導体モジュールは、高電圧を印加して評価しても同様に放電破壊を生じない高い信頼性が得られた。   Further, a silicon carbide semiconductor module using a silicon carbide semiconductor element cut out from the silicon carbide semiconductor device substrate 1b by using an electric discharge machining method has high reliability that does not cause discharge breakdown even when evaluated by applying a high voltage. was gotten.

この低抵抗の珪素欠乏層は、放電加工機により切断する工程中に形成されるため、切断面、つまり炭化珪素半導体素子の端側面に正確に形成することができ、新たな工程を必要としないので簡便に炭化珪素半導体素子の端側面に導電層17である低抵抗の珪素欠乏層を形成することができ、信頼性の高い炭化珪素ショットキーバリアダイオードの炭化珪素半導体素子を得ることができる。また、この炭化珪素半導体素子を用いた炭化珪素半導体モジュールは高い信頼性を得ることができる。   Since this low-resistance silicon-deficient layer is formed during the process of cutting with an electric discharge machine, it can be accurately formed on the cut surface, that is, the end side surface of the silicon carbide semiconductor element, and no new process is required. Therefore, a low-resistance silicon-deficient layer as the conductive layer 17 can be easily formed on the end side surface of the silicon carbide semiconductor element, and a highly reliable silicon carbide semiconductor element of a silicon carbide Schottky barrier diode can be obtained. Moreover, the silicon carbide semiconductor module using this silicon carbide semiconductor element can obtain high reliability.

本実施の形態においては、ワイヤー線3bの直径75μm、パルス電圧150V、パルス幅0.2μ秒(50%duty)の条件で切断を行なったが、特に限定されるものではなく、切断する炭化珪素半導体デバイス基板1bの特性、厚み等に基づいて定めることができる。具体的には、実施の形態1と同様に、パルス電圧50V〜300V、パルス幅0.1〜10μ秒、10〜80%duty、ワイヤー送り速度0.1mm〜10mm/分の範囲で切断の状況に応じて、調整することが好ましい。   In the present embodiment, the wire wire 3b was cut under the conditions of a diameter of 75 μm, a pulse voltage of 150 V, and a pulse width of 0.2 μsec (50% duty), but is not particularly limited, and silicon carbide to be cut It can be determined based on the characteristics, thickness, etc. of the semiconductor device substrate 1b. Specifically, in the same manner as in the first embodiment, the cutting voltage is within a range of a pulse voltage of 50 V to 300 V, a pulse width of 0.1 to 10 μsec, a 10 to 80% duty, and a wire feed speed of 0.1 mm to 10 mm / min. It is preferable to adjust according to.

実施の形態3
実施の形態2のマルチワイヤーカット放電加工機を用いて、実施の形態1と同様の炭化珪素半導体素子である炭化珪素ショットキーバリアダイオードを形成した炭化珪素半導体デバイス基板1cの切断を行なった。本実施の形態においては、図4に示すように、切断する炭化珪素半導体デバイス基板1c上に冷却板19を取り付けた。
Embodiment 3
Using the multi-wire cut electric discharge machine of the second embodiment, silicon carbide semiconductor device substrate 1c on which a silicon carbide Schottky barrier diode that is a silicon carbide semiconductor element similar to that of the first embodiment was formed was cut. In the present embodiment, as shown in FIG. 4, cooling plate 19 is attached on silicon carbide semiconductor device substrate 1c to be cut.

図4は実施の形態3における炭化珪素半導体デバイス基板1cの放電加工時の表面冷却機構を示す上面模式図、図5は実施の形態3における炭化珪素半導体デバイス基板1cの放電加工時の表面冷却機構を示す断面模式図である。マルチワイヤーカット放電加工機では、同時に複数のワイヤー線3cを用いて炭化珪素半導体デバイス基板1cを切断するが、図4においては構成を簡略化するために、1本のワイヤー線3cのみ着目し、ワイヤー線3c、炭化珪素半導体デバイス基板1c、半導体デバイス18と冷却板19との位置関係を図示した。   FIG. 4 is a schematic top view showing a surface cooling mechanism during electric discharge machining of silicon carbide semiconductor device substrate 1c in the third embodiment, and FIG. 5 shows a surface cooling mechanism during electric discharge machining of silicon carbide semiconductor device substrate 1c in the third embodiment. It is a cross-sectional schematic diagram which shows. In the multi-wire cut electric discharge machine, the silicon carbide semiconductor device substrate 1c is cut simultaneously using a plurality of wire wires 3c, but in order to simplify the configuration in FIG. 4, only one wire wire 3c is focused, The positional relationship among the wire 3c, the silicon carbide semiconductor device substrate 1c, the semiconductor device 18 and the cooling plate 19 is illustrated.

冷却板19は、銅からなり、ワイヤー線3cを挟むように、一定の間隙を保持して炭化珪素半導体デバイス基板1c面に取り付けられる。放電加工法により切断する時には、ワイヤー線3cに近接する切断部分は非常に高温に加熱され、溶融されることで切断される。切断後、すぐに冷却しない場合、炭化珪素半導体デバイス基板1c上に形成した半導体デバイス18の絶縁層(図5には図示しないが、図2の絶縁層15に相当する。)等を形成する樹脂膜やアノード電極等の電極材料がその熱の影響で劣化する場合がある。   Cooling plate 19 is made of copper, and is attached to the surface of silicon carbide semiconductor device substrate 1c with a certain gap so as to sandwich wire wire 3c. When cutting by the electric discharge machining method, a cutting portion adjacent to the wire 3c is heated to a very high temperature and is cut by being melted. If not immediately cooled after cutting, a resin that forms an insulating layer (not shown in FIG. 5, but corresponds to the insulating layer 15 in FIG. 2) of the semiconductor device 18 formed on the silicon carbide semiconductor device substrate 1c. An electrode material such as a membrane or an anode electrode may be deteriorated by the influence of the heat.

そこで本実施の形態においては、放電加工法により切断した後に、炭化珪素半導体デバイス基板1cをすぐに冷却できるように、冷却板19を取り付け、実施の形態2と同様の切断条件で、炭化珪素半導体デバイス基板1cの切断を行なった。   Therefore, in the present embodiment, a cooling plate 19 is attached so that silicon carbide semiconductor device substrate 1c can be immediately cooled after being cut by electric discharge machining, and the silicon carbide semiconductor is cut under the same cutting conditions as in the second embodiment. The device substrate 1c was cut.

本実施の形態に示す冷却板19を備えた炭化珪素半導体デバイス基板1cの切断により、切断後に炭化珪素半導体デバイス基板1cが冷却されるため、絶縁膜を形成する樹脂膜や電極材料の劣化のない、炭化珪素ショットキーバリアダイオードの炭化珪素半導体素子を得ることができた。   By cutting silicon carbide semiconductor device substrate 1c provided with cooling plate 19 shown in the present embodiment, silicon carbide semiconductor device substrate 1c is cooled after cutting, so that there is no deterioration of the resin film or electrode material forming the insulating film. Thus, a silicon carbide semiconductor element of a silicon carbide Schottky barrier diode was obtained.

また、炭化珪素ショットキーバリアダイオードの炭化珪素半導体素子の切断面である、炭化珪素半導体素子の端側面には導電層17である低抵抗の珪素欠乏層が形成され、炭化珪素ショットキーバリアダイオードは高電圧を印加した場合でも沿面放電を生じることがなく、高い信頼性を示した。   In addition, a low-resistance silicon-deficient layer, which is the conductive layer 17, is formed on the side surface of the silicon carbide semiconductor element, which is a cut surface of the silicon carbide semiconductor element of the silicon carbide Schottky barrier diode. Even when a high voltage is applied, creeping discharge does not occur and high reliability is exhibited.

さらに、炭化珪素半導体デバイス基板1cから放電加工法を用いて切り出した炭化珪素半導体素子を用いた炭化珪素半導体モジュールも、高電圧を印加して評価しても同様に放電破壊を生じない高い信頼性が得られた。   Further, the silicon carbide semiconductor module using the silicon carbide semiconductor element cut out from the silicon carbide semiconductor device substrate 1c by using the electric discharge machining method also has high reliability that does not cause discharge breakdown even when evaluated by applying a high voltage. was gotten.

この低抵抗の珪素欠乏層は、放電加工機により切断する工程中に形成されるため、切断面、つまり炭化珪素半導体素子の端側面に正確に形成することができ、新たな工程を必要としないので簡便に炭化珪素半導体素子の信頼性を高めることができる。   Since this low-resistance silicon-deficient layer is formed during the process of cutting with an electric discharge machine, it can be accurately formed on the cut surface, that is, the end side surface of the silicon carbide semiconductor element, and no new process is required. Therefore, the reliability of the silicon carbide semiconductor element can be easily increased.

なお、上述した各実施の形態で得た炭化珪素からなる炭化珪素半導体素子は、他の半導体素子、他の電子部品と組み合わせて、炭化珪素半導体モジュールとして使用することもできることは言うまでも無い。   Needless to say, the silicon carbide semiconductor element made of silicon carbide obtained in each of the above-described embodiments can be used as a silicon carbide semiconductor module in combination with other semiconductor elements and other electronic components.

実施の形態4
実施の形態2のマルチワイヤーカット放電加工機を用いて、実施の形態1と同様の炭化珪素半導体素子である炭化珪素ショットキーバリアダイオードを形成した炭化珪素半導体デバイス基板1dの切断を行った。実施の形態1〜3では、炭化珪素半導体デバイス基板を切断した後に、炭化珪素半導体素子の端側面に形成される導電層17の体積抵抗率、放電破壊に対する信頼性を中心に評価してきたが、本実施の形態では、導電層17の表面粗さ(Ra)に着目し、炭化珪素半導体素子表面に形成する樹脂膜の密着性を評価した。
Embodiment 4
Using the multi-wire cut electric discharge machine of the second embodiment, silicon carbide semiconductor device substrate 1d on which a silicon carbide Schottky barrier diode, which is a silicon carbide semiconductor element similar to that of the first embodiment, was formed was cut. In Embodiments 1 to 3, after cutting the silicon carbide semiconductor device substrate, evaluation has been made mainly on the volume resistivity of the conductive layer 17 formed on the end side surface of the silicon carbide semiconductor element, and reliability against discharge breakdown. In the present embodiment, paying attention to the surface roughness (Ra) of the conductive layer 17, the adhesion of the resin film formed on the surface of the silicon carbide semiconductor element was evaluated.

図6(a)は炭化珪素半導体デバイス基板とワイヤー線の間に印加したパルス電圧特性、図6(b)は、その結果得られた導電層の表面粗さのイメージ図を示している。本実施の形態においては、炭化珪素半導体デバイス基板1dの切断を、直径50μmのワイヤ線3aを用い、図6(a)に示すように、パルス電圧80V、パルス幅1μ秒(50%duty)の条件で行い、3パルスに1回の割合でパルス電圧120Vのパルス電圧を印加した。ワイヤー線3aの送り速度は0.5mm/分とした。   FIG. 6A shows a pulse voltage characteristic applied between the silicon carbide semiconductor device substrate and the wire, and FIG. 6B shows an image of the surface roughness of the conductive layer obtained as a result. In the present embodiment, the silicon carbide semiconductor device substrate 1d is cut using a wire wire 3a having a diameter of 50 μm and having a pulse voltage of 80 V and a pulse width of 1 μsec (50% duty) as shown in FIG. Under the condition, a pulse voltage of 120 V was applied at a rate of once every three pulses. The feed rate of the wire 3a was 0.5 mm / min.

図7は本実施の形態で炭化珪素半導体デバイス基板から炭化珪素半導体素子を切断した際の炭化珪素半導体素子の端側面に形成された導電層表面のAFM(Atomic Force Microscope)像である。図7に示したように作製した導電層17の表面のAFM観察を行い、表面粗さ(Ra)を求めた。表面粗さは約0.4μmであり、図6(b)に表面粗さのイメージ図を示したように、パルス電圧を変化させた周期で表面形状が変化した。本実施の形態では、パルス電圧を周期的に変化させることで切断表面の表面粗さを変えることを示したが、パルス電圧だけでなく、ワイヤー線の送り速度、パルス幅、duty比等を同様に周期的に変えることでも表面粗さを変えることができる。また本実施の形態では、図4に示した冷却板19を設置せずに加工したが、冷却板19を用いても同様に切断を行うことができる。   FIG. 7 is an AFM (Atomic Force Microscope) image of the surface of the conductive layer formed on the end side surface of the silicon carbide semiconductor element when the silicon carbide semiconductor element is cut from the silicon carbide semiconductor device substrate in the present embodiment. AFM observation of the surface of the conductive layer 17 produced as shown in FIG. 7 was performed to determine the surface roughness (Ra). The surface roughness was about 0.4 μm, and the surface shape changed with a cycle in which the pulse voltage was changed as shown in the image of the surface roughness in FIG. In this embodiment, it has been shown that the surface roughness of the cutting surface is changed by periodically changing the pulse voltage. However, not only the pulse voltage but also the wire wire feed rate, pulse width, duty ratio, etc. are the same. The surface roughness can also be changed by periodically changing to. Further, in the present embodiment, the processing is performed without installing the cooling plate 19 shown in FIG. 4, but the cutting can be similarly performed using the cooling plate 19.

この切断した炭化珪素ショットキーバリアダイオードの表面に樹脂膜を形成すると高い密着力を示し、優れた信頼性の樹脂膜を得ることができた。上記の切断条件を種々変えて、表面粗さの異なる切断面を形成して樹脂膜の密着性、信頼性を評価したところ、導電層17の表面粗さを0.1μm以上、10μm以下としたとき高い密着力、優れた信頼性を得ることができた。導電層17の表面粗さが0.1μm未満では表面粗さが小さく、良好な密着性を得ることができなかった。また表面粗さが10μmを超える場合は、樹脂膜の密着性は比較的十分であったが、膜表面の凹凸が大きく、段差部分から水分の侵入等が起こり、信頼性を高めることができなかった。   When a resin film was formed on the surface of the cut silicon carbide Schottky barrier diode, high adhesion was exhibited, and an excellent reliability resin film could be obtained. Various cutting conditions were varied to form cut surfaces with different surface roughnesses, and the adhesion and reliability of the resin film were evaluated. The surface roughness of the conductive layer 17 was set to 0.1 μm or more and 10 μm or less. Sometimes high adhesion and excellent reliability could be obtained. When the surface roughness of the conductive layer 17 was less than 0.1 μm, the surface roughness was small and good adhesion could not be obtained. Also, when the surface roughness exceeds 10 μm, the adhesion of the resin film was relatively sufficient, but the film surface has large irregularities, moisture intrusion etc. from the stepped part, and the reliability cannot be improved. It was.

1a 炭化珪素半導体デバイス基板、1b 炭化珪素半導体デバイス基板、1c 炭化珪素半導体デバイス基板、1d 炭化珪素半導体デバイス基板2a ワイヤーガイド、2b ワイヤーガイド、3a ワイヤー線、3b ワイヤー線、3c ワイヤー線、4a ステージ、4b ステージ、5a ステージ制御部、5b ステージ制御部、6a 加工電源、6b 加工電源、7a ワイヤー制御部、7b ワイヤー制御部、8a 放電加工制御部、8b 放電加工制御部、9 炭化珪素基板、10 エピタキシャル炭化珪素層、11 炭化珪素基体、12 イオン注入領域、13 ショットキー電極、14 アノード電極、15 絶縁層、16 カソード電極、17 導電層、18 半導体デバイス、19 冷却板。   1a silicon carbide semiconductor device substrate, 1b silicon carbide semiconductor device substrate, 1c silicon carbide semiconductor device substrate, 1d silicon carbide semiconductor device substrate 2a wire guide, 2b wire guide, 3a wire wire, 3b wire wire, 3c wire wire, 4a stage, 4b stage, 5a stage control unit, 5b stage control unit, 6a machining power source, 6b machining power source, 7a wire control unit, 7b wire control unit, 8a electric discharge machining control unit, 8b electric discharge machining control unit, 9 silicon carbide substrate, 10 epitaxial Silicon carbide layer, 11 Silicon carbide substrate, 12 Ion implantation region, 13 Schottky electrode, 14 Anode electrode, 15 Insulating layer, 16 Cathode electrode, 17 Conductive layer, 18 Semiconductor device, 19 Cooling plate.

本発明の炭化珪素半導体素子の製造方法は、炭化珪素半導体デバイス基板上に形成された複数の半導体デバイスの間を切断してそれぞれ炭化珪素半導体素子として形成する工程と、炭化珪素半導体素子の端側面に炭化珪素半導体デバイス基板の炭化珪素基体の体積抵抗率よりも低い体積抵抗率を有する珪素欠乏層を形成する工程とを、放電加工法を用いて一工程で行うものである。 A method for manufacturing a silicon carbide semiconductor element of the present invention includes a step of cutting a plurality of semiconductor devices formed on a silicon carbide semiconductor device substrate to form each of them as a silicon carbide semiconductor element, and an end of the silicon carbide semiconductor element. The step of forming a silicon deficient layer having a volume resistivity lower than the volume resistivity of the silicon carbide substrate of the silicon carbide semiconductor device substrate on the side surface is performed in one step using an electric discharge machining method .

また、本発明の炭化珪素半導体素子は、炭化珪素半導体デバイス基板上に形成された複数の半導体デバイスの間を放電加工法を用いて切断してそれぞれを炭化珪素半導体素子として形成する工程を行った際に同時に形成され、かつ、炭化珪素半導体デバイス基板の炭化珪素基体の体積抵抗率よりも低い体積抵抗率を有する珪素欠乏層を、端側面に備えたものである。

Moreover, the silicon carbide semiconductor element of the present invention was subjected to a process of cutting each of a plurality of semiconductor devices formed on the silicon carbide semiconductor device substrate using an electric discharge machining method to form each of them as a silicon carbide semiconductor element. A silicon-deficient layer formed at the same time and having a volume resistivity lower than the volume resistivity of the silicon carbide substrate of the silicon carbide semiconductor device substrate is provided on the end surface.

Claims (13)

炭化珪素半導体デバイス基板上に形成された複数の半導体デバイスを放電加工法によりそれぞれの炭化珪素半導体素子に切り出し、前記炭化珪素半導体素子の端側面に前記炭化珪素半導体デバイス基板の炭化珪素基体の体積抵抗率よりも低い体積抵抗率を有する導電層を形成する工程を含む炭化珪素半導体素子の製造方法。   A plurality of semiconductor devices formed on a silicon carbide semiconductor device substrate are cut into respective silicon carbide semiconductor elements by an electric discharge machining method, and volume resistance of a silicon carbide substrate of the silicon carbide semiconductor device substrate is formed on an end side surface of the silicon carbide semiconductor element. The manufacturing method of the silicon carbide semiconductor element including the process of forming the conductive layer which has a volume resistivity lower than a rate. 前記工程で前記炭化珪素半導体素子の端側面に形成された導電層の体積抵抗率が7Ωcm以下である請求項1に記載の炭化珪素半導体素子の製造方法。   The method for manufacturing a silicon carbide semiconductor element according to claim 1, wherein the volume resistivity of the conductive layer formed on the side surface of the silicon carbide semiconductor element in the step is 7 Ωcm or less. 前記工程で前記炭化珪素半導体素子の端側面に形成された導電層の厚みが10μm以上、20μm以下である請求項1に記載の炭化珪素半導体素子の製造方法。   2. The method for manufacturing a silicon carbide semiconductor element according to claim 1, wherein a thickness of the conductive layer formed on the end side surface of the silicon carbide semiconductor element in the step is 10 μm or more and 20 μm or less. 前記工程で前記炭化珪素半導体素子の端側面に形成された導電層の結晶性が炭化珪素基板の結晶性よりも低い請求項1に記載の炭化珪素半導体素子の製造方法。   The method for manufacturing a silicon carbide semiconductor element according to claim 1, wherein the crystallinity of the conductive layer formed on the side surface of the silicon carbide semiconductor element in the step is lower than the crystallinity of the silicon carbide substrate. 前記工程で前記炭化珪素半導体素子の端側面に形成された導電層の表面粗さが0.1μm以上10μm以下である請求項1に記載の炭化珪素半導体素子の製造方法。   2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the surface roughness of the conductive layer formed on the end side surface of the silicon carbide semiconductor device in the step is 0.1 μm or more and 10 μm or less. 前記炭化珪素半導体素子の端側面に形成された導電層が珪素欠乏層である請求項1乃至5のいずれか1項に記載の炭化珪素半導体素子の製造方法。   The method for manufacturing a silicon carbide semiconductor element according to claim 1, wherein the conductive layer formed on the end side surface of the silicon carbide semiconductor element is a silicon-deficient layer. 前記放電加工法において、前記炭化珪素半導体デバイス基板表面に冷却機構を備える請求項1乃至6のいずれか1項に記載の炭化珪素半導体素子の製造方法。   The method for manufacturing a silicon carbide semiconductor element according to claim 1, wherein a cooling mechanism is provided on a surface of the silicon carbide semiconductor device substrate in the electric discharge machining method. 端側面に炭化珪素基体の体積抵抗率よりも低い体積抵抗率を有する珪素欠乏層を備えた炭化珪素半導体素子。   A silicon carbide semiconductor element comprising a silicon deficient layer having a volume resistivity lower than a volume resistivity of a silicon carbide substrate on an end side surface. 前記珪素欠乏層の体積抵抗率が7Ωcm以下である請求項8に記載の炭化珪素半導体素子。   The silicon carbide semiconductor device according to claim 8, wherein the volume resistivity of the silicon-deficient layer is 7 Ωcm or less. 前記珪素欠乏層の厚みが10μm以上、20μm以下である請求項8に記載の炭化珪素半導体素子。   The silicon carbide semiconductor element according to claim 8, wherein the silicon-deficient layer has a thickness of 10 μm or more and 20 μm or less. 前記珪素欠乏層の結晶性が炭化珪素基板の結晶性よりも低い請求項8に記載の炭化珪素半導体素子。   The silicon carbide semiconductor element according to claim 8, wherein the crystallinity of the silicon-deficient layer is lower than the crystallinity of the silicon carbide substrate. 前記珪素欠乏層の表面粗さが0.1μm以上10μm以下である請求項8に記載の炭化珪素半導体素子。   The silicon carbide semiconductor element according to claim 8, wherein a surface roughness of the silicon-deficient layer is 0.1 μm or more and 10 μm or less. 請求項8乃至12のいずれか1項に記載の炭化珪素半導体素子を用いた炭化珪素半導体モジュール。   The silicon carbide semiconductor module using the silicon carbide semiconductor element of any one of Claims 8 thru | or 12.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61295290A (en) * 1985-06-24 1986-12-26 株式会社日立製作所 Laser processing method
JP2006273592A (en) * 2005-03-28 2006-10-12 Sumitomo Electric Ind Ltd Diamond substrate and its manufacturing method
JP2007283412A (en) * 2006-04-13 2007-11-01 Nippon Steel Corp Outline machining method for conductive wafer
JP2009224641A (en) * 2008-03-18 2009-10-01 Denso Corp Silicon carbide semiconductor device and manufacturing method therefor
JP2011236063A (en) * 2010-05-06 2011-11-24 Sumitomo Electric Ind Ltd Method for manufacturing silicon carbide substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61295290A (en) * 1985-06-24 1986-12-26 株式会社日立製作所 Laser processing method
JP2006273592A (en) * 2005-03-28 2006-10-12 Sumitomo Electric Ind Ltd Diamond substrate and its manufacturing method
JP2007283412A (en) * 2006-04-13 2007-11-01 Nippon Steel Corp Outline machining method for conductive wafer
JP2009224641A (en) * 2008-03-18 2009-10-01 Denso Corp Silicon carbide semiconductor device and manufacturing method therefor
JP2011236063A (en) * 2010-05-06 2011-11-24 Sumitomo Electric Ind Ltd Method for manufacturing silicon carbide substrate

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