JP2017135273A - Semiconductor device and manufacturing method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can suppress a reduction in characteristics occurring at the time of semiconductor substrate processing, and a manufacturing method therefor.SOLUTION: A semiconductor device according to one embodiment has a semiconductor substrate, a first electrode and a second electrode. The semiconductor substrate has a first part and a second part provided around the first part. The first part and the second part have a first surface. The first part has a second surface opposite to the first surface. The second part has a third surface opposite to the first surface. A distance between the first surface and the third surface in a third direction perpendicular to the first surface is longer than a distance between the first surface and the second surface in the third direction. The first electrode is provided on the first surface. The second electrode is provided on the second surface and on the third surface.SELECTED DRAWING: Figure 2

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

In a semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), in order to reduce the on-resistance, a process of mechanically polishing the back surface of the semiconductor substrate to reduce the thickness is performed in the manufacturing process. However, when the thickness of the semiconductor substrate is reduced, the mechanical strength is reduced, and the semiconductor substrate may be cracked or the semiconductor substrate may be cracked.
The manufactured semiconductor device is mounted on a ceramic substrate using solder or the like. At this time, when part of the melted solder flows out to the outer periphery of the semiconductor device, the thickness of the solder (hereinafter referred to as solder thickness) is partially reduced between the semiconductor device and the substrate. In portions where the solder thickness is thin, cracks are likely to occur due to repeated thermal expansion and contraction, and the semiconductor device may not operate normally.

JP 2014-120729 A

  The problem to be solved by the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress deterioration in characteristics that occur during processing of a semiconductor substrate.

The semiconductor device according to the embodiment includes a semiconductor substrate, a first electrode, and a second electrode.
The semiconductor substrate includes a first portion and a second portion provided around the first portion. The first portion and the second portion have a first surface. The first portion has a second surface opposite to the first surface. The second portion has a third surface opposite to the first surface. The distance in the third direction perpendicular to the first surface between the first surface and the third surface is greater than the distance in the third direction between the first surface and the second surface. long.
The first electrode is provided on the first surface.
The second electrode is provided on the second surface and the third surface.

It is a top view showing the semiconductor device concerning an embodiment. It is A-A 'sectional drawing of FIG. It is process sectional drawing showing the manufacturing method of the semiconductor device which concerns on embodiment. It is a process top view showing the manufacturing method of the semiconductor device concerning an embodiment. It is process sectional drawing showing the manufacturing method of the semiconductor device which concerns on embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
In the present specification and each drawing, the same elements as those already described are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.
In the description of each embodiment, an XYZ orthogonal coordinate system is used. A direction perpendicular to the surface S1 of the semiconductor substrate S or the surface S4 of the semiconductor substrate Sa is defined as a Z direction (third direction). Two directions parallel to these planes and perpendicular to each other are defined as an X direction (first direction) and a Y direction (second direction).
In the following description, the notation of n ⁺ , n ⁻ and p represents the relative level of the impurity concentration in each conductivity type. That is, the notation with “+” has a relatively higher impurity concentration than the notation without both “+” and “−”, and the notation with “−” It shows that the impurity concentration is relatively lower than the notation.
About each embodiment described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

First, an example of the semiconductor device according to the embodiment will be described with reference to FIGS.
FIG. 1 is a plan view illustrating a semiconductor device 100 according to the embodiment.
2 is a cross-sectional view taken along line AA ′ of FIG.
In FIG. 1, the insulating layer 20 is omitted.

The semiconductor device 100 is, for example, a MOSFET.
As illustrated in FIGS. 1 and 2, the semiconductor device 100 includes a semiconductor substrate S, a drain electrode 31 (second electrode), a source electrode 32 (first electrode), and a gate pad 33.
The semiconductor substrate S includes an n ⁺ -type drain region 4, an n ⁻ -type semiconductor region 1, a p-type base region 2, an n ^{+ -type} source region 3, a gate electrode 10, a gate insulating layer 11, and an insulating layer. 20 is provided.

As shown in FIG. 1, the semiconductor substrate S has a first portion P1 and a second portion P2. The first portion P1 is a portion including the centers in the X direction and the Y direction of the semiconductor substrate S, and the second portion P2 is provided around the first portion P1.
The source electrode 32 and the gate pad 33 are provided on the first portion P1 of the semiconductor substrate S so as to be separated from each other.

As shown in FIG. 2, the first portion P1 and the second portion P2 have a common surface S1 (first surface). Further, the first portion P1 has a surface S2 (second surface) opposite to the surface S1, and the second portion P2 has a surface S3 (third surface) opposite to the surface S1.
The thickness of the second portion P2 is thicker than the thickness of the first portion P1. That is, the distance in the Z direction between the surface S1 and the surface S3 is longer than the distance in the Z direction between the surface S1 and the surface S2.

The drain electrode 31 is provided on the surface S2 and the surface S3.
The n ⁺ -type drain region 4 is provided on the drain electrode 31 and is electrically connected to the drain electrode 31. In the n ⁺ -type drain region 4, the thickness of the second portion P ^< b ^> 2 in the Z direction is larger than the thickness of the first portion P ^< b ^> 1 in the Z direction.

The n ^{− type} semiconductor region 1 is provided on the n ^{+ type} drain region 4.
The p-type base region 2 is selectively provided on the n ⁻ -type semiconductor region 1 in the first portion P1.
The n ^{+ -type} source region 3 is selectively provided on the p-type base region 2.

The gate insulating layer 11 is provided between the n ^{− type} semiconductor region 1, the p type base region 2, the n ^{+ type} source region 3, and the gate electrode 10. The gate electrode 10 faces the p-type base region 2 via the gate insulating layer 11 in the X direction.

A region around the p-type base region 2 in the surface S <b> 1 is covered with the insulating layer 20.
The source electrode 32 is provided on the p-type base region 2, the n ^{+ -type} source region 3, and the insulating layer 20 in the first portion P 1, and is electrically connected to the p-type base region 2 and the n ^{+ -type} source region 3. It is connected. A part of the insulating layer 20 is provided between the gate electrode 10 and the source electrode 32, and these electrodes are electrically separated.

Here, an example of the material of each component will be described.
The n ^{− -type} semiconductor region 1, the p-type base region 2, the n ^{+ -type} source region 3, and the n ⁺ -type drain region 4 contain silicon as a semiconductor material. Arsenic, phosphorus, or antimony can be used as the n-type impurity added to the semiconductor material. Boron can be used as the p-type impurity.
The gate electrode 10 includes a conductive material such as polysilicon.
The gate insulating layer 11 and the insulating layer 20 include an insulating material such as silicon oxide.
The drain electrode 31 and the source electrode 32 include a metal such as aluminum.

Next, the manufacturing method of the semiconductor device according to the embodiment will be described with reference to FIGS.
3 and 5 are process cross-sectional views illustrating the method for manufacturing the semiconductor device according to the embodiment.
FIG. 4 is a process plan view illustrating the method for manufacturing the semiconductor device according to the embodiment.
In FIGS. 3 and 5, only the vicinity of the end of the semiconductor substrate Sa is shown.

First, a semiconductor substrate Sa having an n ^{+ type} semiconductor layer 4a and an n ^{− type} semiconductor layer 1a provided on the n ^{+ type} semiconductor layer 4a is prepared. The semiconductor substrate Sa includes single crystal silicon. The semiconductor substrate Sa has a surface S4 (first surface) on the n ⁻ -type semiconductor layer 1a side and a surface S5 (second surface) on the n ^{+ -type} semiconductor layer 4a side.

Next, as shown in FIG. 3A, a plurality of openings OP are formed on the surface S4 side by using the RIE (Reactive Ion Etching) method. The opening OP penetrates the n ^{− type} semiconductor layer 1a and reaches the n ^{+ type} semiconductor layer 4a.

Next, the semiconductor substrate Sa is heated in a reducing gas atmosphere such as hydrogen gas. At this time, the surface migration of silicon atoms contained in the semiconductor substrate Sa occurs so that the surface energy is minimized. Thereby, the plurality of openings OP are connected in the semiconductor substrate Sa, and the openings are closed. As a result, as shown in FIG. 3B, a space ES is formed in the semiconductor substrate Sa (in the n ^{+ -type} semiconductor layer 4a).

  The space ES extends in parallel with the surface S4. That is, the surface S6 that is the upper surface of the space ES is parallel to the surface S4 of the semiconductor substrate Sa. The space ES is formed on the surface S4 side in the semiconductor substrate Sa. That is, the space ES is formed such that the distance D1 between the surface S4 and the space ES is shorter than the distance D2 between the surface S5 and the space ES.

At this time, as shown in FIG. 4, a plurality of spaces ES are formed apart from each other in the X direction and the Y direction. That is, the space ES is formed such that the support portion P3 that is a part of the semiconductor substrate S remains between the spaces ES.
Note that the width, height, position, and the like of the space ES can be adjusted by changing the width and depth of the opening OP, the interval between the openings OP, and the like.

Next, the p-type base region 2, the n ^{+ -type} source region 3, the gate electrode 10, the gate insulating layer 11, the insulating layer 20, and the source electrode 32 are formed on the surface S4 side of the semiconductor substrate Sa. At this time, the order in which these components are formed is arbitrary. Subsequently, the surface S4 is covered with the protective tape 40.

  Next, a part of the semiconductor substrate Sa is removed from the surface S5 side so that the surface S6 of the space ES is exposed. This step is performed, for example, by grinding the semiconductor substrate Sa from the surface S5 side. Alternatively, a part of the semiconductor substrate Sa may be removed by using an etching process such as the RIE method. At this time, as shown in FIG. 5A, it is desirable to grind the semiconductor substrate Sa so as to leave at least a part of the support part P3 located between the spaces ES.

  Next, the drain electrode 31 is formed on the back surface of the semiconductor substrate Sa including the surface S6. Thereafter, the semiconductor substrate Sa is cut by a dicing line DL sandwiched between broken lines shown in FIG. 5B, and the protective tape 40 is peeled off, whereby a plurality of semiconductor devices 100 are obtained. At this time, the semiconductor substrate Sa is cut so that the width W1 of the dicing line DL is narrower than the width W2 of the support portion P3, so that the semiconductor having the second portion P2 as shown in FIGS. Device 100 is obtained.

In the example shown in FIGS. 3 to 5, the case where the semiconductor substrate Sa including the n ^{+ -type} semiconductor layer 4 a and the n ⁻ -type semiconductor layer 1 a is used has been described. However, the semiconductor substrate Sa includes an n ^{+ -type} semiconductor layer. 4a may be included, and only n ^{− type} semiconductor layer 1a may be included. In this case, after the semiconductor substrate Sa is ground and before the drain electrode 31 is formed, the n ⁺ -type drain region 4 is formed by ion-implanting n-type impurities into the back surface of the semiconductor substrate Sa.

Here, the operation and effect of this embodiment will be described.
In the semiconductor device 100 according to the embodiment, the semiconductor substrate S includes a first portion P1 and a second portion P2 provided around the first portion P1 and thicker than the first portion P1. According to this semiconductor device, when the semiconductor device is mounted on the ceramic substrate using the solder, the molten solder does not easily flow out to the outer periphery of the semiconductor device. This is because the solder flow toward the outer periphery of the semiconductor device is hindered by the second portion P2.
For this reason, according to the present embodiment, when mounting the semiconductor device, it is possible to suppress the solder from flowing out to the outer periphery of the semiconductor device, and there is a possibility that a portion with a thin solder thickness is generated between the semiconductor device and the substrate. It becomes possible to reduce.

In addition, it is desirable to reduce the thickness of the semiconductor device in the Z direction in order to reduce the on-resistance. In this regard, in the method of manufacturing a semiconductor device according to the present embodiment, after forming the space ES in the semiconductor substrate Sa, a part of the semiconductor substrate Sa is removed so as to expose the surface S6 of the space, and the semiconductor substrate Sa is thinned.
According to this manufacturing method, the surface S6 of the space ES can be used as the back surface of the semiconductor substrate Sa after being thinned. That is, the thickness of the semiconductor substrate Sa after being thinned can be easily adjusted by adjusting the depth of the opening OP and adjusting the position where the space ES is formed. Further, since the surface S6 is a single crystal surface formed by surface migration of silicon atoms, the surface S6 is less damaged and has higher flatness than the surface formed by grinding the semiconductor substrate Sa. For this reason, by using the surface S6 as the back surface of the semiconductor substrate Sa and forming the drain electrode 31 on the back surface, it is possible to suppress the occurrence of a leak path in the semiconductor device 100.

When forming the space ES, it is not limited to the examples shown in FIGS. 3 to 5, and it is also possible to form one large space extending along the surface S <b> 4 in the semiconductor substrate Sa. However, as shown in FIG. 3B and FIG. 4, in the manufacturing method according to the present embodiment, a plurality of spaces ES are formed so as to leave the support portions P3 in the semiconductor substrate Sa, and at least the support portions P3 are formed. It is desirable to remove a part of the semiconductor substrate Sa so as to leave a part.
According to this manufacturing method, after the semiconductor substrate Sa is thinned, the support portion P3 extending between the respective surfaces S6 in the X direction and the Y direction remains. Since the semiconductor substrate Sa has such a support portion P3, it is possible to improve the mechanical strength of the semiconductor substrate Sa, and the semiconductor substrate Sa may be cracked in the subsequent process for the semiconductor substrate Sa. Can be reduced.
For example, as shown in FIG. 5B, by dicing the semiconductor substrate Sa in the support portion P3, it is possible to reduce the possibility that the semiconductor substrate Sa is cracked in the dicing process.

In the above description of the embodiment, the case where the semiconductor device 100 is a MOSFET has been described. However, the invention according to this embodiment can also be applied to other semiconductor devices. For example, the semiconductor device 100 may be a diode, an IGBT (Insulated Gate Bipolar Transistor), or the like. When the semiconductor device 100 is an IGBT, a p-type semiconductor region electrically connected to the drain electrode 31 is provided between the drain electrode 31 and the n ⁺ -type drain region 4.

  In the above description of the embodiment, the case where the semiconductor device 100 includes the trench-type gate electrode 10 has been described. However, the semiconductor device 100 may include a planar-type gate electrode.

The relative level of the impurity concentration between the semiconductor regions in each of the embodiments described above can be confirmed using, for example, an SCM (scanning capacitance microscope). The carrier concentration in each semiconductor region can be regarded as being equal to the impurity concentration activated in each semiconductor region. Therefore, the relative level of the carrier concentration between the semiconductor regions can also be confirmed using the SCM.
The impurity concentration in each semiconductor region can be measured by, for example, SIMS (secondary ion mass spectrometry).

As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. For example, n ^{− type} semiconductor region 1, p type base region 2, n ^{+ type} source region 3, n ^{+ type} drain region 4, gate electrode 10, gate insulating layer 11, insulating layer 20, drain electrode included in the embodiment The specific configuration of each element such as 31 and the source electrode 32 can be appropriately selected by those skilled in the art from known techniques. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof. Further, the above-described embodiments can be implemented in combination with each other.

1 ... n ^- type semiconductor region, 2 ... p-type base region, 3 ... ^{n +} -type source region, 4 ... ^{n +} form drain regions, 10 ... gate electrode, 11 ... gate insulating layer, 20: insulating layer, 31 ... drain Electrode, 32 ... Source electrode, 33 ... Gate pad, 100 ... Semiconductor device, S, Sa ... Semiconductor substrate

Claims (8)

Forming a space extending along the first surface in a semiconductor substrate having a first surface and a second surface opposite to the first surface;
A method for manufacturing a semiconductor device, wherein an inner surface of the space is exposed by removing a part of the semiconductor substrate.   In the step of forming the space, a plurality of openings are formed on the first surface of the semiconductor substrate, and the space is formed by heating the semiconductor substrate having the plurality of openings formed in a reducing gas atmosphere. A method for manufacturing a semiconductor device according to claim 1.   In the step of forming the space, the space is formed on the first surface side in the semiconductor substrate, and the semiconductor substrate is ground from the second surface side to remove the part of the semiconductor substrate. A method for manufacturing a semiconductor device according to claim 2.   In the step of forming the space, the space is formed in the semiconductor substrate by a first direction parallel to the first surface and a second direction parallel to the first surface and intersecting the first direction; 4. The method of manufacturing a semiconductor device according to claim 3, wherein a plurality of the semiconductor devices are formed. The semiconductor substrate has a support portion located between the spaces,
The method of manufacturing a semiconductor device according to claim 4, wherein in the step of grinding the semiconductor substrate, the part of the semiconductor substrate is ground so as to leave at least a part of the support portion.   6. The method of manufacturing a semiconductor device according to claim 5, wherein after the semiconductor substrate is ground, the semiconductor substrate is cut at a position where the at least part of the support portion is left.   The method of manufacturing a semiconductor device according to claim 6, wherein, in the step of cutting the semiconductor substrate, a width of a portion to be cut is narrower than a width of the at least part of the support portion. A first portion; and a second portion provided around the first portion, wherein the first portion and the second portion have a first surface, and the first portion is the first surface. A second surface opposite to the first surface, and the second portion has a third surface opposite to the first surface, with respect to the first surface between the first surface and the third surface. A distance in a third direction perpendicular to the semiconductor substrate is longer than a distance in the third direction between the first surface and the second surface;
A first electrode provided on the first surface;
A second electrode provided on the second surface and the third surface;
A semiconductor device comprising:

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