JP7172327B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a silicon carbide semiconductor device.

Conventionally, silicon (Si) has been used as a constituent material of power semiconductor devices that control high voltages and large currents. There are multiple types of power semiconductor devices, including bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). It is

For example, bipolar transistors and IGBTs have higher current densities than MOSFETs and can handle large currents, but cannot be switched at high speed. Specifically, bipolar transistors are limited to use at a switching frequency of about several kHz, and IGBTs are limited to use at a switching frequency of about several tens of kHz. On the other hand, a power MOSFET has a lower current density than a bipolar transistor or an IGBT, making it difficult to increase the current, but it is capable of high-speed switching operation up to several MHz.

However, there is a strong demand in the market for power semiconductor devices that combine large current and high speed, and efforts have been made to improve IGBTs and power MOSFETs. . From the viewpoint of power semiconductor devices, semiconductor materials that can replace silicon are being investigated, and silicon carbide (SiC) is a semiconductor material that can be used to fabricate (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics. is attracting attention.

This is because SiC is a chemically very stable material, has a wide bandgap of 3 eV, and can be used as a semiconductor extremely stably even at high temperatures. Also, the maximum electric field intensity is one order of magnitude higher than that of silicon. Since SiC has a high possibility of exceeding the material limit of silicon, future growth is greatly expected for power semiconductor applications, especially for MOSFETs. In particular, the on-resistance is expected to be small, and a vertical SiC-MOSFET having even lower on-resistance while maintaining high breakdown voltage characteristics can be expected.

FIG. 13 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. FIG. 13 shows the structure of a silicon carbide semiconductor device formed on a silicon carbide semiconductor wafer and before being singulated. As shown in FIG. 13, a MOS gate having a general trench gate structure is provided on the front surface (the surface on the side of p-type silicon carbide epitaxial layer 103) of a semiconductor substrate made of silicon carbide (hereinafter referred to as silicon carbide substrate). Prepare. A silicon carbide substrate (semiconductor chip) comprises an n ⁺ -type support substrate (hereinafter referred to as an n ⁺ -type silicon carbide substrate) 101 made of silicon carbide, an n-type silicon carbide epitaxial layer 102 and an n-type high-concentration current diffusion region. Each silicon carbide layer forming region 106 and p-type silicon carbide epitaxial layer 103 is epitaxially grown in order.

A first p ⁺ -type base region 104 is selectively provided between adjacent trenches 118 (mesa portion) in the n-type high-concentration region 106 . A second p ⁺ -type base region 105 that partially covers the bottom surface of the trench 118 is selectively provided in the n-type high-concentration region 106 . Second p ⁺ -type base region 105 is provided at a depth that does not reach n-type silicon carbide epitaxial layer 102 . The second p ⁺ -type base region 105 and the first p ⁺ -type base region 104 may be formed at the same time. First p ⁺ -type base region 104 is provided so as to be in contact with p-type silicon carbide epitaxial layer 103 .

Numerals 107 to 111 and 113 denote n ⁺ -type source regions, p ⁺⁺ -type contact regions, gate insulating films, gate electrodes, interlayer insulating films and source electrodes, respectively. Here, the source electrode pad (not shown) on the source electrode is made of a material such as aluminum (Al) or an aluminum-silicon alloy (Al--Si) that is difficult to bond with solder. Therefore, a plating film 116 is provided on the source electrode pad. Further, a back surface electrode 114 is provided on the back surface side of n ⁺ -type silicon carbide substrate 101 . After division by dicing or the like, an external terminal electrode is provided on the plating film 116 portion via solder.

Further, in the conventional silicon carbide semiconductor device, an edge termination region 131 that surrounds the active region 130 and retains the breakdown voltage is provided in the outer peripheral portion of the active region 130 through which the main current flows. A dicing area 132 is provided. A JTE structure 120 and an n ⁺ -type semiconductor region 121 are provided in the edge termination region 131 . By cutting (dicing) dicing region 132, the silicon carbide semiconductor device is individualized. An oxide film 122 is provided on the edge termination region 131 and the dicing region 132 .

Here, FIG. 14 is a top view showing a silicon carbide semiconductor element on a silicon carbide semiconductor wafer. A silicon carbide semiconductor device is manufactured by cutting a plurality of silicon carbide semiconductor elements (silicon carbide semiconductor chips) 140 formed on a silicon carbide semiconductor wafer 150 into chips (individualization). Cutting from the silicon carbide semiconductor wafer 150 is performed by cutting, for example, along the dotted line portion (dicing line) in FIG. 14 with a circular rotating diamond dicing blade, laser, or ultrasonic wave.

For example, a front surface opening dicing line region including a predetermined dicing line is formed, an ohmic electrode and a rear surface opening dicing line region are formed on the back surface of the SiC wafer, and divided by the predetermined dicing line into a plurality of wafers. There is a technology that improves the throughput of the dicing process and contributes to the extension of the life of the dicing blade by obtaining a semiconductor chip (see, for example, Patent Document 1 below).

In addition, by forming a voltage relaxation layer along the dicing region and further covering the voltage relaxation layer with an insulating layer, when measuring the electrical characteristics of the semiconductor element structure, the maximum applied voltage ( BV) and lighten the burden of the voltage applied to the air between the dicing region and the surface electrode (for example, see Patent Document 2 below).

JP 2010-118573 A JP 2013-191632 A

Here, since a wide bandgap semiconductor substrate (for example, a silicon carbide substrate) has higher hardness than a silicon substrate, distortion often occurs on the cut surface during dicing. Distortion is cracks (scratches) or chips that occur in the substrate. For example, distortion occurs when the surface cut by the dicing blade is tilted during dicing.

FIG. 15 is a top view showing a singulated silicon carbide semiconductor device. Silicon carbide semiconductor wafer 150 is cut in dicing region 132 to expose singulated cut surface 200 . A gate pad region 212 is also provided in the active region 130 . In the dicing region 132, the strain 220 on the surface side is described as an example of strain.

FIG. 16 is a side view showing an example of strain in a silicon carbide semiconductor device. The distortion includes distortion 220 on the front side, distortion 221 on the back side, and distortion 222 on the cut surface side. Of these, the strain 220 on the front side and the strain 221 on the back side can be identified by an automatic visual inspection device or by visual observation. can be sorted out as ineligible products.

However, it is difficult to identify the distortion 222 on the side of the cut surface inward of the cut surface by an automatic visual inspection device or by visual inspection. In addition, since the strain 222 on the cut surface side often exists in the dicing region 132, it does not significantly affect the characteristics of the silicon carbide semiconductor device at the start of use. is also difficult to detect. However, if the silicon carbide semiconductor device having the strain 222 on the cut surface side is used for a long period of time and stress such as the thermal stress of the implant pin is applied to the strain 222, the strain 222 will grow as an axis, leading to the edge termination region 131 and the active region. A region 130 is reached. FIG. 17 is a top view showing an example of increased strain in a silicon carbide semiconductor device. As shown in FIG. 17, the strain 222 is enlarged by thermal stress and becomes like the strain 240 of the cut surface. Since the portion of the strain 240 has a large electrical resistance, the overall electrical characteristics of the silicon carbide semiconductor device deteriorate when used for a long period of time.

In order to solve the above-described problems of the prior art, the present invention suppresses the distortion caused by the inclination of the dicing blade during dicing, so that the reliability does not deteriorate even after long-term use. An object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device.

In order to solve the above problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. Manufacture of a silicon carbide semiconductor device provided in a silicon carbide semiconductor substrate of a first conductivity type, including an active region through which a main current flows, and a termination region arranged outside the active region and having a breakdown voltage structure formed thereon The method. First, a first step of forming a silicon carbide semiconductor element on the silicon carbide semiconductor substrate is performed. Next, a second step of forming a region where no film is provided at a position where the dicing blade comes into contact with the dicing region outside the termination region is performed. Next, a third step of cutting out the silicon carbide semiconductor element from the silicon carbide semiconductor substrate by cutting the dicing region is performed. In the third step, in a region where the film is not provided, when the blade comes into contact with the film, the blade stops advancing and the blade is positioned so as to cut parallel to the dicing line. and correct the tilt.

Further, in the method of manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the regions in which the film is not provided in the dicing regions have different widths in the direction perpendicular to the dicing lines. It is characterized by forming a plurality .

Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the region where the film is not provided is formed in a direction perpendicular to the dicing line from the dicing start position to the end position . It is characterized in that it is formed so as to have a wider width .

Further, in the method of manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the region where the film is not provided is divided into dicing lines in a first direction and dicing lines in a second direction orthogonal to the first direction. It is characterized in that it is formed at a position where the

Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the region where the film is not provided is a dicing line in a first direction or a dicing line in a second direction orthogonal to the first direction. It is characterized in that it is formed in either one or both of

Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the invention described above, the active region has a striped element structure extending in the same direction as the dicing line in the first direction, and the film is provided. It is characterized in that the non-cut regions are formed only in the dicing lines in the first direction.

Moreover, in the method of manufacturing a silicon carbide semiconductor device according to the present invention, in the invention described above, the film is formed of an oxide film.

According to the invention described above, in the dicing region, there is a region where the oxide film is not formed in the region in contact with the dicing blade. For this reason, if the dicing blade is tilted during dicing of this area and cuts obliquely, the dicing blade scrapes the oxide film. When it is detected that the oxide film has been scraped off, the advance of the dicing blade is stopped, the position of the dicing blade is corrected, the inclination is corrected, and straight cutting is performed again. Therefore, it is possible to suppress the distortion caused by the inclination of the surface cut by the dicing blade during dicing, and the reliability does not deteriorate even after long-term use.

According to the method for manufacturing a silicon carbide semiconductor device according to the present invention, by suppressing the distortion caused by the tilting of the dicing blade during dicing, the reliability can be reduced even after long-term use. It has the effect of not

1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment; FIG. FIG. 11 is a cross-sectional view showing another structure of the silicon carbide semiconductor device according to the embodiment (No. 1); It is a sectional view showing another structure of the silicon carbide semiconductor device according to the embodiment (No. 2). 1 is a top view showing silicon carbide semiconductor elements on a silicon carbide semiconductor wafer according to an embodiment; FIG. 1 is a top view showing the structure of a silicon carbide semiconductor device according to an embodiment; FIG. 1 is a cross-sectional view schematically showing a state in the middle of manufacturing a silicon carbide semiconductor device according to an embodiment (No. 1); FIG. FIG. 2 is a cross-sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 2); FIG. 3 is a cross-sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 3); FIG. 4 is a cross-sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 4); FIG. 5 is a cross-sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 5); FIG. 6 is a cross-sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 6); FIG. 7 is a cross-sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 7); It is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. FIG. 2 is a top view showing silicon carbide semiconductor elements on a silicon carbide semiconductor wafer; 1 is a top view showing a silicon carbide semiconductor device that has been singulated; FIG. FIG. 4 is a side view showing an example of strain in a silicon carbide semiconductor substrate; FIG. 4 is a top view showing an example of increased strain in a silicon carbide semiconductor substrate;

Preferred embodiments of a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p mean that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached, respectively. When the notations of n and p including + and - are the same, it indicates that the concentrations are close, and the concentrations are not necessarily the same. In the following description of the embodiments and the accompanying drawings, the same configurations are denoted by the same reference numerals, and overlapping descriptions are omitted. Also, in this specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after it, and adding "-" before the index indicates a negative index.

(Embodiment)
A semiconductor device according to the present invention is configured using a wide bandgap semiconductor. In the embodiments, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET as an example. FIG. 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment.

FIG. 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 1 shows the structure of a silicon carbide semiconductor device formed on a silicon carbide semiconductor wafer and before being singulated. In addition, the configuration of the active region 30 through which the main current flows in the thickness direction of the substrate when the element structure is formed and in the ON state, the edge termination region 31 surrounding the active region 30 and holding the withstand voltage, and the edge termination region 31 3 shows the configuration of the dicing region 32 outside the . Dicing region 32 is a region that is cut when singulating the silicon carbide semiconductor device.

As shown in FIG. 1, the silicon carbide semiconductor device according to the embodiment includes a first main surface (front surface) of an n ⁺ -type silicon carbide substrate (first conductivity type semiconductor substrate) 1, for example (0001). An n-type silicon carbide epitaxial layer 2 is deposited on the surface (Si surface).

The n ⁺ -type silicon carbide substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). The n-type silicon carbide epitaxial layer 2 is a low-concentration n-type drift layer doped with, for example, nitrogen at an impurity concentration lower than that of the n ⁺ -type silicon carbide substrate 1 . An n-type high-concentration region 6 is formed on the surface of the n-type silicon carbide epitaxial layer 2 opposite to the n ⁺ -type silicon carbide substrate 1 side. The n-type high-concentration region 6 is a high-concentration n-type drift layer doped with nitrogen, for example, at an impurity concentration lower than that of the n ⁺ -type silicon carbide substrate 1 and higher than that of the n-type silicon carbide epitaxial layer 2 . Hereinafter, the n ⁺ -type silicon carbide substrate 1, the n-type silicon carbide epitaxial layer 2, and the later-described p-type silicon carbide epitaxial layer 3 are collectively referred to as a silicon carbide semiconductor substrate.

As shown in FIG. 1 , a back surface electrode 14 is provided on the second main surface of n ⁺ -type silicon carbide substrate 1 (the back surface, that is, the back surface of the silicon carbide semiconductor substrate). The back electrode 14 constitutes a drain electrode. A drain electrode pad (not shown) is provided on the surface of the back electrode 14 .

A trench structure is formed on the first main surface side (p-type silicon carbide epitaxial layer 3 side) of the silicon carbide semiconductor substrate. Specifically, trench 18 extends from the surface of p-type silicon carbide epitaxial layer 3 opposite to n ⁺ -type silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor substrate) from the p-type silicon carbide epitaxial layer. It penetrates the layer 3 and reaches the n-type high concentration region 6 . A gate insulating film 9 is formed on the bottom and sidewalls of trench 18 along the inner wall of trench 18 , and gate electrode 10 is formed inside gate insulating film 9 in trench 18 . Gate electrode 10 is insulated from n-type silicon carbide epitaxial layer 2 and p-type silicon carbide epitaxial layer 3 by gate insulating film 9 . A portion of the gate electrode 10 may protrude from above the trench 18 (source electrode 13 side) toward the source electrode 13 side.

A first p ⁺ -type base region 4 and a second p ⁺ -type base region 4 and a second p ⁺ -type A base region 5 is selectively provided. The second p ⁺ -type base region 5 is formed under the trench 18 and the width of the second p ⁺ -type base region 5 is wider than the width of the trench 18 . The first p ⁺ -type base region 4 and the second p ⁺ -type base region 5 are doped with aluminum (Al), for example.

A structure in which a part of the first p ⁺ -type base region 4 is extended to the trench 18 side and connected to the second p ⁺ -type base region 5 may be employed. In this case, part of the first p ⁺ -type base region 4 is oriented in a direction perpendicular to the direction X in which the first p ⁺ -type base region 4 and the second p ⁺ -type base region 5 are arranged (hereinafter referred to as the first direction). , and the second direction) may have a planar layout in which the n-type high-concentration regions 6 are alternately and repeatedly arranged. For example, a structure in which part of the first p ⁺ -type base region 4 extends to the trench 18 sides on both sides in the first direction X and is connected to part of the second p ⁺ -type base region 5 is periodically arranged in the second direction Y. can be placed in The reason for this is that the holes generated when the avalanche breakdown occurs at the junction of the second p ⁺ -type base region 5 and the n-type silicon carbide epitaxial layer 2 are efficiently evacuated to the source electrode 13 , so that they are transferred to the gate insulating film 9 . This is for reducing the burden and increasing the reliability.

A p-type silicon carbide epitaxial layer 3 is provided on the substrate first main surface side of the n-type silicon carbide epitaxial layer 2 . Inside p-type silicon carbide epitaxial layer 3, n ⁺ -type source region 7 and p ⁺⁺ -type contact region 8 are selectively provided on the first main surface side of the substrate. The n ⁺ -type source region 7 is in contact with the trench 18 . Also, the n ⁺ -type source region 7 and the p ⁺⁺ -type contact region 8 are in contact with each other. Also, a region sandwiched between the first p ⁺ -type base region 4 and the second p ⁺ -type base region 5 in the surface layer of the n-type silicon carbide epitaxial layer 2 on the substrate first main surface side, and the p-type silicon carbide epitaxial layer 3 . An n-type high-concentration region 6 is provided in a region sandwiched between the second p ⁺ -type base regions 5 .

Although only two trench MOS structures are shown in the active region 30 in FIG. 1, more trench MOS gate (metal-oxide-semiconductor insulating gate) structures may be arranged in parallel. good.

Interlayer insulating film 11 is provided all over the first main surface side of the silicon carbide semiconductor substrate so as to cover gate electrode 10 embedded in trench 18 . The source electrode 13 is in contact with the n ⁺ -type source region 7 and the p ⁺⁺ -type contact region 8 through a contact hole opened in the interlayer insulating film 11 . Source electrode 13 is electrically insulated from gate electrode 10 by interlayer insulating film 11 . A source electrode pad (not shown) is provided on the source electrode 13 . A barrier metal (not shown) may be provided between the source electrode 13 and the interlayer insulating film 11 to prevent diffusion of metal atoms from the source electrode 13 to the gate electrode 10 side, for example.

A plated film 16 is selectively provided on the upper portion of the source electrode pad. Although not essential, a protective film 17 may be selectively provided on the surface side of the plated film 16 except for portions where solder is provided.

Next, edge termination region 31 and dicing region 32 will be described. The edge termination region 31 is provided with adjacently arranged JTE structures 20 as a junction termination extension (JTE) structure in order to improve the breakdown voltage of the entire high breakdown voltage semiconductor device by alleviating or dispersing the electric field. ing. An n ⁺ -type semiconductor region 21 functioning as a channel stopper is provided outside the JTE structure 20 (on the dicing region 32 side). An oxide film 22 is provided on the surfaces of the JTE structure 20 and the n ⁺ -type semiconductor region 21 .

In the silicon carbide semiconductor device of the embodiment, dicing region 32 has a region where oxide film 22 is not provided in a portion in contact with a dicing blade. FIG. 1 is a cross section of the portion of the region where the oxide film 22 is not provided. The width of the region where the oxide film 22 is not provided must be less than the width of the dicing region 32 and wider than the width of the dicing blade. For example, if the width of the dicing blade is 20-30 μm, it should be wider than this width.

In the example of FIG. 1 , the width W1 of the region where the oxide film 22 is not provided is approximately the same as the width of the dicing region 32 . For example, if the width of the dicing region 32 is approximately 100 μm, the width W1 is also approximately 100 μm.

2 and 3 are cross-sectional views showing other structures of the silicon carbide semiconductor device according to the embodiment. 2 and 3 are examples in which the widths W2 and W3 of the regions where the oxide film 22 is not provided are narrower than the width W1 of the region in FIG. In the example of FIG. 2, in the area S, the oxide film 22 is not provided in the area of width W2. In this example, the oxide film 22 is not provided in the width W2 which is about 80% of the width of the dicing region 32. FIG. For example, if the width of the dicing region 32 is approximately 100 μm, the width W2 is approximately 80 μm.

In addition, in the example of FIG. 3, the oxide film 22 is not provided in the area of the width W3 in the area S portion. In this example, the oxide film 22 is not provided in the width W3 which is about 60% of the width of the dicing region 32 . For example, if the width of the dicing region 32 is approximately 100 μm, the width W3 is approximately 60 μm.

As described above, in the silicon carbide semiconductor device according to the embodiment, in dicing region 32, there is a region where oxide film 22 is not provided in a portion in contact with the dicing blade. Therefore, when dicing the region where the oxide film 22 is not provided, the dicing blade does not shave the oxide film 22 if the dicing blade cuts straight without being inclined. On the other hand, if the dicing blade tilts and cuts obliquely, the dicing blade scrapes the oxide film 22 . When it is detected that the oxide film 22 has been scraped off, the advance of the dicing blade is stopped, the position and inclination of the dicing blade are corrected, and the advance is restarted to cut straight again. Therefore, it is possible to suppress the distortion caused by the inclination of the surface cut by the dicing blade during dicing, and the reliability does not deteriorate even after long-term use. For example, the fact that the oxide film 22 has been shaved can be identified by pattern recognition or visual observation. Also, the narrower the width of the region where the oxide film 22 is not provided, the smaller the inclination of the dicing blade can be detected.

Here, FIG. 4 is a top view showing a silicon carbide semiconductor element on the silicon carbide semiconductor wafer according to the embodiment. In FIG. 4, dashed lines are dicing lines. In FIG. 4, the region where oxide film 22 is not provided is provided only in part of dicing region 32 . In the example of FIG. 4, the dicing region 32 in the oxide film non-formation region 33 is the region where the oxide film 22 is not provided. 1 to 3 are cross sections taken along line AA' in FIG. 4, and cross sections along line BB' in FIG. , the cross-sectional structure is similar to that of a conventional silicon carbide semiconductor device (see FIG. 13). At this time, it is preferable that a plurality of regions having different widths and not provided with the oxide films 22 are arranged on the dicing line. As a result, it is possible to widen the detection range of the tilt of the dicing blade. More preferably, each dicing line is provided with a plurality of regions in which the oxide films 22 having different widths are not provided.

In FIG. 4, the dicing lines such as DX-DX' do not show the oxide film non-formation region 33, but this is for the sake of clarity. An oxide film non-formation region 33 is provided. Moreover, it is preferable that a plurality of oxide film non-formation regions 33 are provided on the dicing line. In the example of FIG. 4, three or four oxide film non-formation regions 33 are provided on one dicing line. there is

In addition, the width of the region where the oxide film 22 is not provided widens from the dicing start position (one side in the length direction of the dicing line) to the end position (the other side in the length direction of the dicing line). It is preferable to be For example, when dicing starts from AX on a dicing line of AX-AX', the width of the region where no oxide film 22 is provided is narrow as shown in FIG. In the oxide film non-formation region 33 near AX', the width of the region where the oxide film 22 is not provided is preferably wide as shown in FIG. Even if the tilt is small at the start position, the deviation from the dicing line is large at the end position. Also, since the inclination is greater at the end position than at the start position, it is preferable to widen the width of the region.

The oxide film non-formation region 33 is preferably provided at a position where the dicing line in the X direction (for example, AX-AX') and the dicing line in the Y direction (for example, AY-AY') intersect, as shown in FIG. By doing so, it is possible to detect the tilt of the dicing blade in X-direction dicing and the tilt of the dicing blade in Y-direction dicing in one oxide film non-formation region 33 .

FIG. 5 is a top view showing the structure of the silicon carbide semiconductor device according to the embodiment. FIG. 5 is an enlarged view of a portion of area B in FIG. FIG. 5 shows active region 30 and edge termination region 31 of a silicon carbide semiconductor device, and dicing region 32 is between edge termination region 31 . A source pad region 213 and a gate pad region 212 are also described in the active region 30 . The oxide film non-formation region 33 may be provided on the dicing line in the X direction like the oxide film non-formation region 33A, or may be provided on the dicing line in the Y direction like the oxide film non-formation region 33B. . It may be provided on either the dicing line in the X direction or the dicing line in the Y direction, or may be provided on both. When provided only on one side, when the silicon carbide semiconductor device has a stripe-shaped element structure, it is preferable to provide on the dicing line in the same direction as the stripe. For example, the silicon carbide semiconductor device of FIG. 1 has a striped element structure in the depth direction (Y direction) of the trench, and in FIG. 5, the depth direction of the trench is the X direction. It is preferable to have a film non-formation region 33 . This is because the dicing blade is more inclined in the same direction as the stripes than in the direction orthogonal to this direction.

In the above example, the oxide film 22 is used as the film for detecting the inclination of the dicing blade, but this film may be a polysilicon film or a metal film. Any other material may be used as long as it can be detected that the dicing blade is inserted. However, if the dicing blade is tilted and the metal film is scraped, the dicing blade will be greatly damaged, so a soft film such as a polysilicon film is preferable.

(Method for Manufacturing Silicon Carbide Semiconductor Device According to Embodiment)
Next, a method for manufacturing the silicon carbide semiconductor device according to the embodiment will be described. 6 to 12 are cross-sectional views schematically showing states in the process of manufacturing the silicon carbide semiconductor device according to the embodiment.

First, an n ⁺ -type silicon carbide substrate 1 made of n-type silicon carbide is prepared. Then, on the first main surface of this n ⁺ -type silicon carbide substrate 1, a first n-type silicon carbide epitaxial layer 2a made of silicon carbide while being doped with n-type impurities such as nitrogen atoms is formed to a thickness of, for example, about 30 μm. epitaxially grown up to This first n-type silicon carbide epitaxial layer 2 a becomes n-type silicon carbide epitaxial layer 2 . The state up to this point is shown in FIG.

Next, on the surface of first n-type silicon carbide epitaxial layer 2a, an ion implantation mask having a predetermined opening is formed of, for example, an oxide film by photolithography. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film to form a lower first p ⁺ -type base region 4a having a depth of about 0.5 μm. A second p ⁺ -type base region 5 that forms the bottom of the trench 18 may be formed at the same time as the lower first p ⁺ -type base region 4a. The adjacent lower first p ⁺ -type base region 4a and second p ⁺ -type base region 5 are formed so that the distance therebetween is about 1.5 μm. The impurity concentration of the lower first p ⁺ -type base region 4a and the second p ⁺ -type base region 5 is set to about 5×10 ¹⁸ /cm ³ , for example. The state up to this point is shown in FIG.

Next, a portion of the ion implantation mask is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening to implant a portion of the surface region of the first n-type silicon carbide epitaxial layer 2a to a depth of, for example, 0.5 mm. A lower n-type high concentration region 6a having a thickness of about 5 μm is provided. The impurity concentration of the lower n-type high concentration region 6a is set to about 1×10 ¹⁷ /cm ³ , for example.

Next, a second n-type silicon carbide epitaxial layer 2b doped with an n-type impurity such as nitrogen is formed on the surface of first n-type silicon carbide epitaxial layer 2a to a thickness of about 0.5 μm. The impurity concentration of second n-type silicon carbide epitaxial layer 2b is set to about 3×10 ¹⁵ /cm ³ . Thereafter, the n-type silicon carbide epitaxial layer 2 is formed by combining the first n-type silicon carbide epitaxial layer 2a and the second n-type silicon carbide epitaxial layer 2b.

Next, on the surface of second n-type silicon carbide epitaxial layer 2b, an ion implantation mask having a predetermined opening is formed of, for example, an oxide film by photolithography. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film to form an upper first p ⁺ -type base region 4b having a depth of about 0.5 μm so as to overlap the lower first p ⁺ -type base region 4a. do. The lower first p ⁺ -type base region 4 a and the upper first p ⁺ -type base region 4 b form a continuous region to become the first p ⁺ -type base region 4 . The impurity concentration of the upper first p ⁺ -type base region 4b is set to about 5×10 ¹⁸ /cm ³ , for example.

Next, a portion of the ion implantation mask is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening to implant a portion of the surface region of the second n-type silicon carbide epitaxial layer 2b to a depth of, for example, 0.5 mm. An upper n-type high-concentration region 6b having a thickness of about 5 μm is provided. The impurity concentration of the upper n-type high concentration region 6b is set to about 1×10 ¹⁷ /cm ³ , for example. The upper n-type high concentration region 6b and the lower n-type high concentration region 6a are formed so as to be in contact with each other at least partially to form the n-type high concentration region 6. As shown in FIG. However, this n-type high concentration region 6 may or may not be formed over the entire surface of the substrate. The state up to this point is shown in FIG.

Next, on the surface of n-type silicon carbide epitaxial layer 2, p-type silicon carbide epitaxial layer 3 doped with a p-type impurity such as aluminum is formed to a thickness of about 1.3 μm. The impurity concentration of p-type silicon carbide epitaxial layer 3 is set to approximately 4×10 ¹⁷ /cm ³ .

Next, on the surface of p-type silicon carbide epitaxial layer 3, an ion implantation mask having a predetermined opening is formed of, for example, an oxide film by photolithography. An n-type impurity such as phosphorus (P) is ion-implanted into this opening to form n ⁺ -type source region 7 in a portion of the surface of p-type silicon carbide epitaxial layer 3 . The impurity concentration of n ⁺ -type source region 7 is set to be higher than that of p-type silicon carbide epitaxial layer 3 . Next, the ion implantation mask used for forming n ⁺ -type source region 7 is removed, an ion implantation mask having a predetermined opening is formed in the same manner, and the surface of p-type silicon carbide epitaxial layer 3 is removed. A p ⁺⁺ type contact region 8 is provided by ion-implanting a p-type impurity such as aluminum into a part of . The impurity concentration of p ⁺⁺ -type contact region 8 is set to be higher than that of p-type silicon carbide epitaxial layer 3 .

Next, an oxide film having a thickness of 1.5 .mu.m is deposited on the surface of p-type silicon carbide epitaxial layer 3, and an ion implantation mask having a predetermined opening is formed of, for example, an oxide film by photolithography. A p-type impurity such as aluminum is ion-implanted into this opening to form a low impurity concentration JTE structure 20 on the surface of the exposed n-type silicon carbide epitaxial layer 2 . In a similar manner, an ion implantation mask having a predetermined opening is formed of, for example, an oxide film, and an n-type impurity is ion-implanted into a portion of the surface of the n-type silicon carbide epitaxial layer 2 to form an n ⁺ -type semiconductor region. 21 is formed. The state up to this point is shown in FIG.

Next, heat treatment (annealing) is performed in an inert gas atmosphere at about 1700° C. to form the first p ⁺ -type base region 4, the second p ⁺ -type base region 5, the n ⁺ -type source region 7, the p ⁺⁺ -type contact region 8, Activation processing of the JTE structure 20 and the n ⁺ -type semiconductor region 21 is performed. As described above, the ion-implanted regions may be activated collectively by one heat treatment, or may be activated by heat treatment each time ion implantation is performed.

Next, on the surface of p-type silicon carbide epitaxial layer 3, a trench forming mask having a predetermined opening is formed of, for example, an oxide film by photolithography. Next, trenches 18 are formed through p-type silicon carbide epitaxial layer 3 and reaching n-type high-concentration regions 6 by dry etching. The bottom of the trench 18 may reach the first p ⁺ -type base region 4 formed in the n-type heavily doped region 6 . Next, the trench formation mask is removed. The state up to this point is shown in FIG.

Next, an oxide film is formed on the surface of p-type silicon carbide epitaxial layer 3 along the bottom and side walls of trench 18 . Gate insulating film 9 is formed of the surfaces of n ⁺ -type source region 7 and p ⁺⁺ -type contact region 8 and the oxide film formed on the bottom and sidewalls of trench 18 . Oxide layer 22 is formed from the oxide layer formed on edge termination region 31 . In addition, by partially removing the oxide film in the dicing region 23, a region where the film is not provided is formed at the position where the dicing blade comes into contact. This oxide film may be formed by thermal oxidation by heat treatment at a temperature of about 1000° C. in an oxygen atmosphere. Also, the gate insulating film 9 may be formed by a method of depositing by a chemical reaction such as High Temperature Oxide (HTO).

Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9 . This polycrystalline silicon layer may be formed so as to fill the trench 18 . A gate electrode 10 is provided by patterning this polycrystalline silicon layer by photolithography and leaving it inside the trench 18 . A part of the gate electrode 10 may protrude outside the trench 18 . The state up to this point is shown in FIG.

Next, an interlayer insulating film 11 is provided by depositing, for example, phosphorous glass with a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10 . Next, a barrier metal (not shown) made of titanium (Ti) or titanium nitride (TiN) may be formed to cover the interlayer insulating film 11 . Interlayer insulating film 11 and gate insulating film 9 are patterned by photolithography to form contact holes exposing n ⁺ -type source region 7 and p ⁺⁺ -type contact region 8 . Thereafter, heat treatment (reflow) is performed to planarize the interlayer insulating film 11 . The state up to this point is shown in FIG.

Next, a conductive film made of nickel (Ni) or the like that becomes the source electrode 13 is provided in the contact hole and on the interlayer insulating film 11 . This conductive film is patterned by photolithography to leave the source electrode 13 only in the contact hole.

Next, a backside electrode 14 made of nickel or the like is provided on the second main surface of n ⁺ -type silicon carbide substrate 1 . After that, heat treatment is performed in an inert gas atmosphere at about 1000° C., and source electrode 13 and back electrode 14 are in ohmic contact with n ⁺ -type source region 7 , p ⁺⁺ -type contact region 8 , and n ⁺ -type silicon carbide substrate 1 . to form

Next, an aluminum film having a thickness of about 5 μm is deposited on the first main surface of n ⁺ -type silicon carbide substrate 1 by sputtering, and aluminum is deposited by photolithography so as to cover source electrode 13 and interlayer insulating film 11 . removed to form a source electrode pad.

Next, a drain electrode pad (not shown) is formed on the surface of the back electrode 14 by laminating titanium (Ti), nickel and gold (Au) in order, for example. Next, a plating film 16 is selectively formed on the source electrode 13 . As described above, the silicon carbide semiconductor device shown in FIGS. 1 to 3 is completed.

After that, silicon carbide semiconductor wafer 150 is cut (diced) into individual chips, thereby completing silicon carbide semiconductor element 140 . During this dicing, the dicing direction is calibrated according to the contact of the dicing blade with the oxide film 22 .

As described above, according to the silicon carbide semiconductor device according to the embodiment, in the dicing region, there is a region where the oxide film is not formed in the region in contact with the dicing blade. For this reason, if the dicing blade is tilted during dicing of this area and cuts obliquely, the dicing blade scrapes the oxide film. When it is detected that the oxide film has been scraped off, the advance of the dicing blade can be stopped, and the position and inclination of the dicing blade can be corrected so that straight cutting can be performed again. Therefore, it is possible to suppress the distortion caused by the inclination of the surface cut by the dicing blade during dicing, and the reliability does not deteriorate even after long-term use.

In the above description of the present invention, the main surface of the silicon carbide substrate made of silicon carbide is the (0001) plane, and the MOS is formed on the (0001) plane. Various changes can be made to the semiconductor, the plane orientation of the main surface of the substrate, and the like. Further, in each of the above-described embodiments, a trench-type silicon carbide semiconductor device has been described as an example, but the present invention can also be applied to a planar-type silicon carbide semiconductor device and has similar effects.

Further, the present invention can be modified in various ways without departing from the gist of the present invention. In addition, in the above-described embodiments, the case of using silicon carbide as a wide bandgap semiconductor is described as an example, but the present invention can also be applied to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN) and diamond. It is possible. In addition, although the first conductivity type is n-type and the second conductivity type is p-type in the embodiments, the present invention can be similarly applied even if the first conductivity type is p-type and the second conductivity type is n-type. .

INDUSTRIAL APPLICABILITY As described above, the method for manufacturing a silicon carbide semiconductor device according to the present invention is useful for high-voltage semiconductor devices used in power converters, power supply devices for various industrial machines, and the like.

1, 101 n ⁺ -type silicon carbide substrate 2, 102 n-type silicon carbide epitaxial layer 2a first n-type silicon carbide epitaxial layer 2b second n-type silicon carbide epitaxial layer 3, 103 p-type silicon carbide epitaxial layer 4, 104 first p ⁺ -type base region 4a lower first p ⁺ -type base region 4b upper first p ⁺ -type base region 5, 105 second p ⁺ -type base region 6, 106 n-type high concentration region 6a lower n-type high concentration region 6b upper n-type high concentration region 7 , 107 n ⁺ -type source regions 8, 108 p ⁺⁺ -type contact regions 9, 109 gate insulating films 10, 110 gate electrodes 11, 111 interlayer insulating films 13, 113 source electrodes 14, 114 rear electrodes 16, 116 plating films 17, 117 protective films 18, 118 trenches 20, 120 JTE structures 21, 121 n ⁺ -type semiconductor regions 22, 122 oxide films 30, 130 active regions 31, 131 edge termination regions 32, 132 dicing regions 33 oxide-free regions 140 silicon carbide Semiconductor element 150 Silicon carbide semiconductor wafer 200 Individualized cut surface 212 Gate pad region 213 Source pad region 220 Distortion 221 on the front surface side Distortion 222 on the back surface side Distortion 240 on the cut surface side Distortion on the cut surface expanded by thermal stress

Claims (7)

Manufacture of a silicon carbide semiconductor device provided in a silicon carbide semiconductor substrate of a first conductivity type, including an active region through which a main current flows, and a termination region arranged outside the active region and having a breakdown voltage structure formed thereon a method,
a first step of forming a silicon carbide semiconductor element on the silicon carbide semiconductor substrate;
a second step of forming a region where no film is provided at a position where a dicing blade contacts the dicing region outside the termination region;
a third step of cutting out the silicon carbide semiconductor element from the silicon carbide semiconductor substrate by cutting the dicing region;
and in the third step, when the blade comes into contact with the film in a region where the film is not provided, the blade stops moving forward and cuts parallel to the dicing line. A method of manufacturing a silicon carbide semiconductor device, characterized by correcting the position and inclination of a. 2. The manufacturing of a silicon carbide semiconductor device according to claim 1, wherein a plurality of regions not provided with said film are formed in said dicing region so as to have different widths in a direction perpendicular to said dicing line. How . 2. The carbonization according to claim 1, wherein the region where the film is not provided is formed so that the width in the direction perpendicular to the dicing line increases from the dicing start position to the end position . A method for manufacturing a silicon semiconductor device. 4. The method according to any one of claims 1 to 3, wherein the region where the film is not provided is formed at a position where a dicing line in a first direction and a dicing line in a second direction orthogonal to the first direction intersect. A method for manufacturing a silicon carbide semiconductor device according to one aspect. 4. The method according to any one of claims 1 to 3, wherein the region where the film is not provided is formed on one or both of a dicing line in a first direction and a dicing line in a second direction orthogonal to the first direction. A method for manufacturing a silicon carbide semiconductor device according to any one of the above. the active region has a striped element structure extending in the same direction as the dicing line in the first direction;
4. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the region not provided with the film is formed only in the dicing line in the first direction. 7. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein said film is formed of an oxide film.

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