KR100327339B1 - 어닐링을 수반한 반도체 웨이퍼의 제조방법 및 반도체 소자의 제조방법 - Google Patents

어닐링을 수반한 반도체 웨이퍼의 제조방법 및 반도체 소자의 제조방법 Download PDF

Info

Publication number
KR100327339B1
KR100327339B1 KR1019990040652A KR19990040652A KR100327339B1 KR 100327339 B1 KR100327339 B1 KR 100327339B1 KR 1019990040652 A KR1019990040652 A KR 1019990040652A KR 19990040652 A KR19990040652 A KR 19990040652A KR 100327339 B1 KR100327339 B1 KR 100327339B1
Authority
KR
South Korea
Prior art keywords
semiconductor
annealing
wafer
gas
manufacturing
Prior art date
Application number
KR1019990040652A
Other languages
English (en)
Korean (ko)
Other versions
KR20010028418A (ko
Inventor
박정우
송원상
박태서
이한신
박경원
Original Assignee
윤종용
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윤종용, 삼성전자 주식회사 filed Critical 윤종용
Priority to KR1019990040652A priority Critical patent/KR100327339B1/ko
Priority to TW089118203A priority patent/TW554447B/zh
Priority to JP2000287096A priority patent/JP2001144095A/ja
Publication of KR20010028418A publication Critical patent/KR20010028418A/ko
Application granted granted Critical
Publication of KR100327339B1 publication Critical patent/KR100327339B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
KR1019990040652A 1999-09-21 1999-09-21 어닐링을 수반한 반도체 웨이퍼의 제조방법 및 반도체 소자의 제조방법 KR100327339B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019990040652A KR100327339B1 (ko) 1999-09-21 1999-09-21 어닐링을 수반한 반도체 웨이퍼의 제조방법 및 반도체 소자의 제조방법
TW089118203A TW554447B (en) 1999-09-21 2000-09-06 Method of manufacturing semiconductor wafer and semiconductor device including annealing
JP2000287096A JP2001144095A (ja) 1999-09-21 2000-09-21 アニーリングを伴った半導体ウェーハの製造方法及び半導体素子の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990040652A KR100327339B1 (ko) 1999-09-21 1999-09-21 어닐링을 수반한 반도체 웨이퍼의 제조방법 및 반도체 소자의 제조방법

Publications (2)

Publication Number Publication Date
KR20010028418A KR20010028418A (ko) 2001-04-06
KR100327339B1 true KR100327339B1 (ko) 2002-03-06

Family

ID=19612433

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990040652A KR100327339B1 (ko) 1999-09-21 1999-09-21 어닐링을 수반한 반도체 웨이퍼의 제조방법 및 반도체 소자의 제조방법

Country Status (3)

Country Link
JP (1) JP2001144095A (ja)
KR (1) KR100327339B1 (ja)
TW (1) TW554447B (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7026229B2 (en) * 2001-11-28 2006-04-11 Vartan Semiconductor Equipment Associates, Inc. Athermal annealing with rapid thermal annealing system and method
KR100862856B1 (ko) * 2002-12-24 2008-10-09 동부일렉트로닉스 주식회사 실리콘웨이퍼 제조 방법
US10381218B1 (en) * 2018-05-17 2019-08-13 Micron Technology, Inc. Methods of forming a semiconductor structure and methods of forming isolation structures

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152179A (ja) * 1991-11-30 1993-06-18 Toshiba Ceramics Co Ltd シリコンウエハの製造方法
JPH05152235A (ja) * 1991-11-28 1993-06-18 Fujitsu Ltd 半導体基板の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152235A (ja) * 1991-11-28 1993-06-18 Fujitsu Ltd 半導体基板の製造方法
JPH05152179A (ja) * 1991-11-30 1993-06-18 Toshiba Ceramics Co Ltd シリコンウエハの製造方法

Also Published As

Publication number Publication date
TW554447B (en) 2003-09-21
JP2001144095A (ja) 2001-05-25
KR20010028418A (ko) 2001-04-06

Similar Documents

Publication Publication Date Title
US6054363A (en) Method of manufacturing semiconductor article
JP3918565B2 (ja) 半導体装置の製造方法
US6350662B1 (en) Method to reduce defects in shallow trench isolations by post liner anneal
JP2007123875A (ja) 多孔質層を用いてゲルマニウム・オン・インシュレータ半導体構造を形成するための方法及びこれらの方法によって形成される半導体構造
WO2004081982A2 (en) Shallow trench isolation process
JP2002359247A (ja) 半導体部材、半導体装置およびそれらの製造方法
US20030087512A1 (en) Method of manufacturing a semiconductor device
JP2682529B2 (ja) 半導体素子の素子分離絶縁膜形成方法
US6602792B2 (en) Method for reducing stress of sidewall oxide layer of shallow trench isolation
US7391098B2 (en) Semiconductor substrate, semiconductor device and method of manufacturing the same
TW201916251A (zh) 形成絕緣體上矽基底的方法
JP2735407B2 (ja) 半導体装置およびその製造方法
JP2000082804A (ja) 無欠陥領域を有する半導体
KR20020002719A (ko) 반도체 소자의 에피 채널 형성 방법
KR100327339B1 (ko) 어닐링을 수반한 반도체 웨이퍼의 제조방법 및 반도체 소자의 제조방법
US5331193A (en) Semiconductor device resistant to slip line formation
US5970367A (en) Double damascene pattering of silcon-on-insulator transistors
US6274512B1 (en) Method for manufacturing a semiconductor device
KR101077014B1 (ko) 반도체 소자의 소자분리막 제조방법
JP2006190896A (ja) エピタキシャルシリコンウエハとその製造方法および半導体装置とその製造方法
TW202147449A (zh) 半導體結構及其製造方法
US7338870B2 (en) Methods of fabricating semiconductor devices
KR19990085853A (ko) 어닐링을 이용한 트랜치형 소자분리막 형성방법
JP2004179301A (ja) 半導体集積回路装置の製造方法
US11710656B2 (en) Method of forming semiconductor-on-insulator (SOI) substrate

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090202

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee