KR100320648B1 - 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법 - Google Patents
웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법 Download PDFInfo
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- KR100320648B1 KR100320648B1 KR1019990006277A KR19990006277A KR100320648B1 KR 100320648 B1 KR100320648 B1 KR 100320648B1 KR 1019990006277 A KR1019990006277 A KR 1019990006277A KR 19990006277 A KR19990006277 A KR 19990006277A KR 100320648 B1 KR100320648 B1 KR 100320648B1
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- protective layer
- contact
- package
- elastic
- bump
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- 230000008569 process Effects 0.000 title description 13
- 239000011241 protective layer Substances 0.000 claims abstract description 73
- 239000010410 layer Substances 0.000 claims abstract description 71
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
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- 238000000206 photolithography Methods 0.000 description 2
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- 239000004642 Polyimide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Abstract
Description
Claims (5)
- 다수의 도전 패드를 갖는 다이;상기 도전 패드상에 형성된 패시베이션 층으로서, 상기 패시베이션 층은 다수의 패시베이션 비아를 가지며, 각 패시베이션 비아는 상기 도전 패드들 중 연관된 하나의 도전 패드상에 위치하게되는 상기 패시베이션 층;상기 패시베이션 층상에 형성된 탄성 보호층으로서, 상기 탄성 보호층은 다수의 탄성 비아를 가지며, 각 탄성 비아는 연관된 상기 패시베이션 비아와 연결되게되는 상기 탄성 보호층;상기 도전 패드들과 전기적으로 접촉되는 다수의 하부 범프 패드로서, 각 하부 범프 패드가 상기 탄성 비아들중 하나에 연결되게되는 상기 다수의 하부 범프 패드; 및상기 다수의 하부 범프 패드상에 형성된 다수의 콘택 범프로서, 상기 콘택 범프들중 각 하나가 상기 하부 범프 패드들중 선택된 하나에 전기적으로 결합되고, 각 콘택 범프가 상기 도전 패드들중 선택된 하나에 전기적으로 결합되게되는 상기 다수의 콘택 범프를 구비하는 집적회로(IC) 패키지로서,상기 탄성 보호층은 상기 집적회로 패키지가 외부 기판에 부착될 때 상기 콘택 범프에 도입되는 응력을 흡수하도록 배치되고, 상기 콘택 범프는 상기 탄성 보호층에 의한 응력의 흡수를 촉진하는 물질로 형성되며, 상기 탄성 보호층은 상기 다이를 보호하도록 또한 배치되는 것을 특징으로 하는 집적회로(IC) 패키지.
- 제 1 항에 있어서,상기 각 하부 범프 패드가, 상기 탄성 보호층의 일부분상으로 연장되는 립 부분(lip portion)을 포함하는 것을 특징으로 하는 집적회로 패키지.
- 제 1 항에 있어서,상기 탄성 보호층이 약 3.0 GPa 이하의 탄성계수를 갖는 것을 특징으로 하는 집적회로 패키지.
- 제 1 항에 있어서,상기 다이는 바닥 표면에 대향하는 상부 표면을 포함하며,상기 IC 패키지는, 상기 집적회로 패키지가 웨이퍼로부터 절단될 때, 치핑을 감소시키기 위해 상기 다이의 바닥 표면상에 보호 코팅을 더 구비하는 것을 특징으로 하는 집적회로 패키지.
- 각각이 다수의 도전 패드를 갖는 상부 표면, 상기 상부 표면에 대향하는 바닥 표면 및 각 다이의 주변부를 따르는 다수의 스크라이브 라인을 구비하는 다수의 다이를 제공하는 단계;상기 도전 패드상에 패시베이션 층을 제공하는 단계로서, 상기 패시베이션 층은 다수의 비아를 가지며, 각 비아는 상기 도전 패드들중 연관된 하나의 도전 패드상에 위치되도록 하는 단계;상기 패시베이션 층상에 탄성 보호층을 형성하는 단계;상기 패시베이션 층상에 다수의 하부 범프 패드를 형성하는 단계로서, 상기 각 하부 범프 패드가는, 상기 비아들중 연관된 하나의 비아를 통해, 상기 도전 패드들중 연관된 하나의 도전 패드와 전기적으로 결합되는 단계; 및상기 다수의 하부 범프 패드상에 다수의 콘택 범프를 형성하는 단계로서, 상기 콘택 범프들중 각 하나는 상기 하부 범프 패드들중 선택된 하나와 전기적으로 결합되고, 상기 각 콘택 범프가 상기 도전 패드들중 선택된 하나와 전기적으로 결합되는 단계를 구비하고,상기 탄성 보호층은 집적회로 패키지가 외부 기판에 부착될 때 상기 콘택 범프에 도입되는 응력을 흡수하도록 배치되고, 상기 콘택 범프는 상기 탄성 보호층에 의한 응력의 흡수를 촉진하는 물질로 형성되며, 상기 탄성 보호층은 상기 다이를 보호하도록 또한 배치되는 것을 특징으로 하는 반도체 웨이퍼의 제조방법.
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US09/031,167 US6075290A (en) | 1998-02-26 | 1998-02-26 | Surface mount die: wafer level chip-scale package and process for making the same |
US09/031,167 | 1998-02-26 | ||
US9/031,167 | 1998-02-26 |
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