KR100281952B1 - 데이터 전송 메모리 장치 - Google Patents

데이터 전송 메모리 장치 Download PDF

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Publication number
KR100281952B1
KR100281952B1 KR1019980035092A KR19980035092A KR100281952B1 KR 100281952 B1 KR100281952 B1 KR 100281952B1 KR 1019980035092 A KR1019980035092 A KR 1019980035092A KR 19980035092 A KR19980035092 A KR 19980035092A KR 100281952 B1 KR100281952 B1 KR 100281952B1
Authority
KR
South Korea
Prior art keywords
data
memory
output
memory device
memory module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019980035092A
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English (en)
Korean (ko)
Other versions
KR19990044805A (ko
Inventor
야스히로 후지
Original Assignee
아끼구사 나오유끼
후지쯔 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아끼구사 나오유끼, 후지쯔 가부시끼가이샤 filed Critical 아끼구사 나오유끼
Publication of KR19990044805A publication Critical patent/KR19990044805A/ko
Application granted granted Critical
Publication of KR100281952B1 publication Critical patent/KR100281952B1/ko
Assigned to 후지쯔 세미컨덕터 가부시키가이샤 reassignment 후지쯔 세미컨덕터 가부시키가이샤 권리의 전부이전등록 Assignors: 후지쯔 가부시끼가이샤
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
KR1019980035092A 1997-11-14 1998-08-28 데이터 전송 메모리 장치 Expired - Fee Related KR100281952B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP31392797A JP3832947B2 (ja) 1997-11-14 1997-11-14 データ転送メモリ装置
JP97-313927 1997-11-14

Publications (2)

Publication Number Publication Date
KR19990044805A KR19990044805A (ko) 1999-06-25
KR100281952B1 true KR100281952B1 (ko) 2001-03-02

Family

ID=18047200

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980035092A Expired - Fee Related KR100281952B1 (ko) 1997-11-14 1998-08-28 데이터 전송 메모리 장치

Country Status (3)

Country Link
US (2) US6393541B1 (https=)
JP (1) JP3832947B2 (https=)
KR (1) KR100281952B1 (https=)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3832947B2 (ja) * 1997-11-14 2006-10-11 富士通株式会社 データ転送メモリ装置
JP2001035188A (ja) * 1999-07-26 2001-02-09 Fujitsu Ltd 半導体装置の試験方法及び半導体装置
TW482954B (en) * 2000-11-10 2002-04-11 Via Tech Inc Internal operation method of chip set to reduce the power consumption
US7313715B2 (en) 2001-02-09 2007-12-25 Samsung Electronics Co., Ltd. Memory system having stub bus configuration
US6445624B1 (en) * 2001-02-23 2002-09-03 Micron Technology, Inc. Method of synchronizing read timing in a high speed memory system
KR100391990B1 (ko) * 2001-06-14 2003-07-22 삼성전자주식회사 직렬 버스 구조의 메모리 모듈들을 구비한 정보 처리 시스템
JP4308461B2 (ja) * 2001-10-05 2009-08-05 ラムバス・インコーポレーテッド 半導体記憶装置
US6963991B2 (en) * 2002-05-31 2005-11-08 Intel Corporation Synchronizing and aligning differing clock domains
DE60210170T2 (de) * 2002-07-15 2006-11-02 Infineon Technologies Ag Speichersystem
KR100520219B1 (ko) * 2003-01-03 2005-10-11 삼성전자주식회사 고주파수 동작에 적합한 메모리 모듈장치
CN100362854C (zh) * 2003-02-13 2008-01-16 松下电器产业株式会社 固体摄像装置、其驱动方法及使用它的照相机
US7234099B2 (en) * 2003-04-14 2007-06-19 International Business Machines Corporation High reliability memory module with a fault tolerant address and command bus
US8214541B2 (en) * 2006-06-07 2012-07-03 Dell Products L.P. Method and system for uniquely identifying peripheral component devices
KR101373793B1 (ko) * 2006-10-04 2014-03-13 마벨 월드 트레이드 리미티드 플래시 메모리 제어 인터페이스
KR20090074751A (ko) * 2006-10-04 2009-07-07 마벨 테크날러지 재팬 와이.케이. 플래시 메모리 제어 인터페이스
US20090091963A1 (en) * 2007-10-04 2009-04-09 Advanced Micro Devices, Inc. Memory device
JP5025785B2 (ja) * 2010-12-17 2012-09-12 株式会社東芝 半導体記憶装置
KR101977664B1 (ko) 2012-09-14 2019-05-13 삼성전자주식회사 임베디드 멀티미디어 카드와 이를 제어하는 호스트
US10803000B2 (en) * 2017-12-04 2020-10-13 Synopsys, Inc. Phase-aware control and scheduling

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980850A (en) * 1987-05-14 1990-12-25 Digital Equipment Corporation Automatic sizing memory system with multiplexed configuration signals at memory modules
US5243703A (en) 1990-04-18 1993-09-07 Rambus, Inc. Apparatus for synchronously generating clock signals in a data processing system
JP3832947B2 (ja) * 1997-11-14 2006-10-11 富士通株式会社 データ転送メモリ装置

Also Published As

Publication number Publication date
JP3832947B2 (ja) 2006-10-11
JPH11149437A (ja) 1999-06-02
US20020112136A1 (en) 2002-08-15
US6393541B1 (en) 2002-05-21
US6708263B2 (en) 2004-03-16
KR19990044805A (ko) 1999-06-25

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