KR100520219B1 - 고주파수 동작에 적합한 메모리 모듈장치 - Google Patents
고주파수 동작에 적합한 메모리 모듈장치 Download PDFInfo
- Publication number
- KR100520219B1 KR100520219B1 KR10-2003-0000216A KR20030000216A KR100520219B1 KR 100520219 B1 KR100520219 B1 KR 100520219B1 KR 20030000216 A KR20030000216 A KR 20030000216A KR 100520219 B1 KR100520219 B1 KR 100520219B1
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- South Korea
- Prior art keywords
- ports
- data
- command address
- point
- memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Abstract
Description
Claims (7)
- 복수의 디램 메모리 소자들이 칩세트에서 연장된 버스들을 통해 서로 연결된 메모리 모듈 장치에 있어서:하나의 데이터에 대하여 2개의 포트가 각기 할당되어 2포트중 어느 한 포트를 통해 입력된 데이터가 상기 메모리 소자에 전달되는 동시에 나머지 다른 포트를 통해 출력됨에 의해 데이터 버스들이 포인트 대 포인트 구조를 이루도록 한 데이터 버퍼들과;하나의 코멘드 어드레스에 대하여 2개의 포트가 각기 할당되어 2포트중 어느 한 포트를 통해 입력된 코멘드 어드레스가 상기 메모리 소자에 전달되는 동시에 나머지 다른 포트를 통해 출력됨에 의해 코멘드 어드레스 버스들이 포인트 대 포인트 구조를 이루도록 한 코멘드 어드레스 레지스터들을 구비함을 특징으로 하는 메모리 모듈 장치.
- (삭제)
- 복수의 반도체 메모리 소자들이 칩세트에서 연장된 버스들을 통해 서로 연결된 메모리 모듈 장치에 있어서:하나의 데이터에 대하여 2개의 포트가 각기 할당되어 2포트중 어느 한 포트를 통해 입력되어진 데이터가 상기 메모리 소자에 전달되는 동시에 나머지 다른 포트를 통해 출력되는 것에 의해 데이터 버스들이 포인트 대 포인트 구조를 이루도록 하고, 하나의 코멘드 어드레스에 대하여 1개의 포트가 각기 할당되어 한 포트를 통해 입력되어진 코멘드 어드레스가 상기 메모리 소자에 전달됨에 의해 코멘드 어드레스 버스들이 스터브 구조를 이루도록 한 통합 버퍼들을 구비함을 특징으로 하는 메모리 모듈 장치.
- 제3항에 있어서, 상기 메모리 소자들은 디램들임을 특징으로 하는 메모리 모듈 장치.
- 제3항에 있어서, 상기 코멘드 어드레스의 전송 주파수는 데이터 전송 주파수의 1/N(여기서 N은 자연수)로 설정됨을 특징으로 하는 메모리 모듈 장치.
- 복수의 휘발성 메모리 소자들이 버스들을 통해 서로 연결된 메모리 모듈 장치에 있어서:하나의 데이터에 대하여 2개의 포트가 각기 할당되어 2포트중 어느 한 포트를 통해 입력된 데이터가 상기 메모리 소자에 전달되는 동시에 나머지 다른 포트를 통해 출력됨에 의해 데이터 버스들이 포인트 대 포인트 구조를 이루도록 하고, 하나의 코멘드 어드레스에 대하여도 2개의 포트가 각기 할당되어 2포트중 어느 한 포트를 통해 입력된 코멘드 어드레스가 상기 메모리 소자에 전달되는 동시에 나머지 다른 포트를 통해 출력됨에 의해 코멘드 어드레스 버스들도 포인트 대 포인트 구조를 이루도록 한 통합 버퍼들을 구비함을 특징으로 하는 메모리 모듈 장치.
- (삭제)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0000216A KR100520219B1 (ko) | 2003-01-03 | 2003-01-03 | 고주파수 동작에 적합한 메모리 모듈장치 |
US10/739,991 US7124250B2 (en) | 2003-01-03 | 2003-12-18 | Memory module device for use in high-frequency operation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR10-2003-0000216A KR100520219B1 (ko) | 2003-01-03 | 2003-01-03 | 고주파수 동작에 적합한 메모리 모듈장치 |
Publications (2)
Publication Number | Publication Date |
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KR20040062717A KR20040062717A (ko) | 2004-07-09 |
KR100520219B1 true KR100520219B1 (ko) | 2005-10-11 |
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KR10-2003-0000216A KR100520219B1 (ko) | 2003-01-03 | 2003-01-03 | 고주파수 동작에 적합한 메모리 모듈장치 |
Country Status (2)
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US (1) | US7124250B2 (ko) |
KR (1) | KR100520219B1 (ko) |
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2003
- 2003-01-03 KR KR10-2003-0000216A patent/KR100520219B1/ko active IP Right Grant
- 2003-12-18 US US10/739,991 patent/US7124250B2/en not_active Expired - Lifetime
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Publication number | Publication date |
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US7124250B2 (en) | 2006-10-17 |
KR20040062717A (ko) | 2004-07-09 |
US20040133736A1 (en) | 2004-07-08 |
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