KR100276572B1 - 집적 회로 장치 - Google Patents
집적 회로 장치 Download PDFInfo
- Publication number
- KR100276572B1 KR100276572B1 KR1019980009593A KR19980009593A KR100276572B1 KR 100276572 B1 KR100276572 B1 KR 100276572B1 KR 1019980009593 A KR1019980009593 A KR 1019980009593A KR 19980009593 A KR19980009593 A KR 19980009593A KR 100276572 B1 KR100276572 B1 KR 100276572B1
- Authority
- KR
- South Korea
- Prior art keywords
- circuit
- clock
- reference clock
- phase
- timing
- Prior art date
Links
- 230000003111 delayed effect Effects 0.000 claims abstract description 15
- 230000000630 rising effect Effects 0.000 claims description 16
- 230000010363 phase shift Effects 0.000 claims description 10
- 230000001360 synchronised effect Effects 0.000 abstract description 5
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 abstract 3
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 abstract 3
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 abstract 1
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 abstract 1
- 238000001514 detection method Methods 0.000 description 30
- 238000005070 sampling Methods 0.000 description 17
- 230000004044 response Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 230000001934 delay Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Pulse Circuits (AREA)
- Dram (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28722497A JP3717290B2 (ja) | 1997-10-20 | 1997-10-20 | 集積回路装置 |
| JP97-287224 | 1997-10-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990036456A KR19990036456A (ko) | 1999-05-25 |
| KR100276572B1 true KR100276572B1 (ko) | 2000-12-15 |
Family
ID=17714660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980009593A KR100276572B1 (ko) | 1997-10-20 | 1998-03-20 | 집적 회로 장치 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3717290B2 (ja) |
| KR (1) | KR100276572B1 (ja) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4190662B2 (ja) | 1999-06-18 | 2008-12-03 | エルピーダメモリ株式会社 | 半導体装置及びタイミング制御回路 |
| KR100521418B1 (ko) * | 1999-12-30 | 2005-10-17 | 주식회사 하이닉스반도체 | 지연고정루프에서 짧은 록킹 시간과 높은 잡음 제거를갖는 딜레이 제어기 |
| JP4446070B2 (ja) | 2000-04-11 | 2010-04-07 | エルピーダメモリ株式会社 | Ｄｌｌ回路、それを使用する半導体装置及び遅延制御方法 |
| KR100410632B1 (ko) * | 2001-06-30 | 2003-12-18 | 주식회사 하이닉스반도체 | 소비전류와 레이아웃 면적의 감소를 위한 지연고정루프 |
| KR20030064524A (ko) * | 2002-01-28 | 2003-08-02 | 엘지이노텍 주식회사 | 데이터 전송의 타이밍 동기 회로 |
| KR100507877B1 (ko) * | 2002-03-28 | 2005-08-18 | 주식회사 하이닉스반도체 | 면적 축소용 알디엘엘 회로 |
| KR100875651B1 (ko) | 2007-08-14 | 2008-12-26 | 주식회사 하이닉스반도체 | 지연고정루프회로 및 그의 동작방법 |
-
1997
- 1997-10-20 JP JP28722497A patent/JP3717290B2/ja not_active Expired - Fee Related
-
1998
- 1998-03-20 KR KR1019980009593A patent/KR100276572B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11127063A (ja) | 1999-05-11 |
| JP3717290B2 (ja) | 2005-11-16 |
| KR19990036456A (ko) | 1999-05-25 |
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| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
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| LAPS | Lapse due to unpaid annual fee |