KR100260345B1 - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR100260345B1
KR100260345B1 KR1019970023724A KR19970023724A KR100260345B1 KR 100260345 B1 KR100260345 B1 KR 100260345B1 KR 1019970023724 A KR1019970023724 A KR 1019970023724A KR 19970023724 A KR19970023724 A KR 19970023724A KR 100260345 B1 KR100260345 B1 KR 100260345B1
Authority
KR
South Korea
Prior art keywords
input
layer
wiring
output cell
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1019970023724A
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English (en)
Korean (ko)
Other versions
KR19980024049A (ko
Inventor
마사토시 와타나베
Original Assignee
아끼구사 나오유끼
후지쯔 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 아끼구사 나오유끼, 후지쯔 가부시끼가이샤 filed Critical 아끼구사 나오유끼
Publication of KR19980024049A publication Critical patent/KR19980024049A/ko
Application granted granted Critical
Publication of KR100260345B1 publication Critical patent/KR100260345B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019970023724A 1996-09-24 1997-06-10 반도체 장치 Expired - Lifetime KR100260345B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP96-251765 1996-09-24
JP25176596A JP3962441B2 (ja) 1996-09-24 1996-09-24 半導体装置

Publications (2)

Publication Number Publication Date
KR19980024049A KR19980024049A (ko) 1998-07-06
KR100260345B1 true KR100260345B1 (ko) 2000-07-01

Family

ID=17227590

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970023724A Expired - Lifetime KR100260345B1 (ko) 1996-09-24 1997-06-10 반도체 장치

Country Status (4)

Country Link
US (1) US5903019A (enExample)
JP (1) JP3962441B2 (enExample)
KR (1) KR100260345B1 (enExample)
TW (1) TW337614B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3989038B2 (ja) * 1996-04-17 2007-10-10 株式会社ルネサステクノロジ 半導体集積回路装置
JP3914649B2 (ja) * 1999-02-10 2007-05-16 株式会社東芝 半導体装置
US6696712B1 (en) * 2000-08-11 2004-02-24 Seiko Epson Corporation Semicustom IC having adjacent macrocells
JP2001339047A (ja) * 2000-05-29 2001-12-07 Matsushita Electric Ind Co Ltd 半導体装置
JP4798881B2 (ja) * 2001-06-18 2011-10-19 富士通セミコンダクター株式会社 半導体集積回路装置
US7217966B1 (en) * 2005-02-18 2007-05-15 National Semiconductor Corporation Self-protecting transistor array
US7594198B2 (en) * 2007-02-27 2009-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Ultra fine pitch I/O design for microchips
US9786663B2 (en) * 2013-08-23 2017-10-10 Qualcomm Incorporated Layout construction for addressing electromigration
US9972624B2 (en) * 2013-08-23 2018-05-15 Qualcomm Incorporated Layout construction for addressing electromigration

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300796A (en) * 1988-06-29 1994-04-05 Hitachi, Ltd. Semiconductor device having an internal cell array region and a peripheral region surrounding the internal cell array for providing input/output basic cells
JPH02152254A (ja) * 1988-12-02 1990-06-12 Mitsubishi Electric Corp 半導体集積回路装置
JP3185271B2 (ja) * 1991-09-13 2001-07-09 日本電気株式会社 半導体集積回路
JP3228583B2 (ja) * 1992-03-31 2001-11-12 株式会社東芝 半導体集積回路装置
JP2822781B2 (ja) * 1992-06-11 1998-11-11 三菱電機株式会社 マスタスライス方式半導体集積回路装置
JPH06326194A (ja) * 1993-05-17 1994-11-25 Mitsubishi Electric Corp 半導体集積回路装置

Also Published As

Publication number Publication date
JPH1098108A (ja) 1998-04-14
US5903019A (en) 1999-05-11
JP3962441B2 (ja) 2007-08-22
TW337614B (en) 1998-08-01
KR19980024049A (ko) 1998-07-06

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