KR100258898B1 - 메모리와 로직의 통합 칩 및 그 테스트 방법 - Google Patents

메모리와 로직의 통합 칩 및 그 테스트 방법 Download PDF

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Publication number
KR100258898B1
KR100258898B1 KR1019970081276A KR19970081276A KR100258898B1 KR 100258898 B1 KR100258898 B1 KR 100258898B1 KR 1019970081276 A KR1019970081276 A KR 1019970081276A KR 19970081276 A KR19970081276 A KR 19970081276A KR 100258898 B1 KR100258898 B1 KR 100258898B1
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KR
South Korea
Prior art keywords
dram
signal
test
mode
processor
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KR1019970081276A
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English (en)
Korean (ko)
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KR19990061022A (ko
Inventor
김미양
Original Assignee
김영환
현대전자산업주식회사
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Application filed by 김영환, 현대전자산업주식회사 filed Critical 김영환
Priority to KR1019970081276A priority Critical patent/KR100258898B1/ko
Priority to TW087121615A priority patent/TW544720B/zh
Priority to JP10370580A priority patent/JPH11260100A/ja
Publication of KR19990061022A publication Critical patent/KR19990061022A/ko
Application granted granted Critical
Publication of KR100258898B1 publication Critical patent/KR100258898B1/ko

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)
KR1019970081276A 1997-12-31 1997-12-31 메모리와 로직의 통합 칩 및 그 테스트 방법 KR100258898B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019970081276A KR100258898B1 (ko) 1997-12-31 1997-12-31 메모리와 로직의 통합 칩 및 그 테스트 방법
TW087121615A TW544720B (en) 1997-12-31 1998-12-24 Method of testing a memory device in a merged memory and logic apparatus
JP10370580A JPH11260100A (ja) 1997-12-31 1998-12-25 Ｍｍｌ装置内のメモリ素子テスト方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970081276A KR100258898B1 (ko) 1997-12-31 1997-12-31 메모리와 로직의 통합 칩 및 그 테스트 방법

Publications (2)

Publication Number Publication Date
KR19990061022A KR19990061022A (ko) 1999-07-26
KR100258898B1 true KR100258898B1 (ko) 2000-06-15

Family

ID=19530537

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970081276A KR100258898B1 (ko) 1997-12-31 1997-12-31 메모리와 로직의 통합 칩 및 그 테스트 방법

Country Status (3)

Country Link
JP (1) JPH11260100A (zh)
KR (1) KR100258898B1 (zh)
TW (1) TW544720B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020049386A (ko) * 2000-12-19 2002-06-26 윤종용 테스트시 기입 데이터의 마스킹 동작이 가능한 반도체메모리 장치 및 데이터 마스킹 방법

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Publication number Publication date
TW544720B (en) 2003-08-01
JPH11260100A (ja) 1999-09-24
KR19990061022A (ko) 1999-07-26

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