KR100257953B1 - 반도체 집적 회로 - Google Patents

반도체 집적 회로 Download PDF

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Publication number
KR100257953B1
KR100257953B1 KR1019920007690A KR920007690A KR100257953B1 KR 100257953 B1 KR100257953 B1 KR 100257953B1 KR 1019920007690 A KR1019920007690 A KR 1019920007690A KR 920007690 A KR920007690 A KR 920007690A KR 100257953 B1 KR100257953 B1 KR 100257953B1
Authority
KR
South Korea
Prior art keywords
polysilicon
gate
layer
semiconductor integrated
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1019920007690A
Other languages
English (en)
Korean (ko)
Other versions
KR920022535A (ko
Inventor
리 쿠오-후아
존 내기 윌리암
숭 잔미에
Original Assignee
죤 제이. 키세인
아메리칸 텔리폰 앤드 텔레그라프 컴퍼니
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 죤 제이. 키세인, 아메리칸 텔리폰 앤드 텔레그라프 컴퍼니 filed Critical 죤 제이. 키세인
Publication of KR920022535A publication Critical patent/KR920022535A/ko
Application granted granted Critical
Publication of KR100257953B1 publication Critical patent/KR100257953B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435Cross-sectional shapes or dispositions of interconnections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices
    • H10B10/15Static random access memory [SRAM] devices comprising a resistor load element

Landscapes

  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1019920007690A 1991-05-16 1992-05-07 반도체 집적 회로 Expired - Lifetime KR100257953B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/701,270 US5128738A (en) 1991-05-16 1991-05-16 Integrated circuit
US701,270 1991-05-16

Publications (2)

Publication Number Publication Date
KR920022535A KR920022535A (ko) 1992-12-19
KR100257953B1 true KR100257953B1 (ko) 2000-06-01

Family

ID=24816679

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920007690A Expired - Lifetime KR100257953B1 (ko) 1991-05-16 1992-05-07 반도체 집적 회로

Country Status (7)

Country Link
US (1) US5128738A (https=)
EP (1) EP0514095B1 (https=)
JP (1) JP2662144B2 (https=)
KR (1) KR100257953B1 (https=)
DE (1) DE69222973T2 (https=)
ES (1) ES2109311T3 (https=)
TW (1) TW198131B (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5213990A (en) * 1992-04-01 1993-05-25 Texas Instruments, Incorporated Method for forming a stacked semiconductor structure
JPH05283654A (ja) * 1992-04-03 1993-10-29 Toshiba Corp マスクromとその製造方法
US5721445A (en) * 1995-03-02 1998-02-24 Lucent Technologies Inc. Semiconductor device with increased parasitic emitter resistance and improved latch-up immunity
US5631112A (en) * 1995-11-16 1997-05-20 Vanguard International Semiconductor Corporation Multiple exposure method for photo-exposing photosensitive layers upon high step height topography substrate layers
US5707765A (en) * 1996-05-28 1998-01-13 Microunity Systems Engineering, Inc. Photolithography mask using serifs and method thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5736844A (en) * 1980-08-15 1982-02-27 Hitachi Ltd Semiconductor device
JPS59201461A (ja) * 1983-04-28 1984-11-15 Toshiba Corp 読み出し専用半導体記憶装置およびその製造方法
JPS59231851A (ja) * 1983-06-14 1984-12-26 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリセル
JPH0628302B2 (ja) * 1984-02-28 1994-04-13 富士通株式会社 半導体記憶装置
JPS63126270A (ja) * 1986-11-14 1988-05-30 Mitsubishi Electric Corp 半導体記憶装置
JPH0831533B2 (ja) * 1988-10-21 1996-03-27 セイコーエプソン株式会社 半導体記憶装置
EP0365690B1 (en) * 1988-05-07 1999-12-22 Seiko Epson Corporation Semiconductor device and semiconductor memory device
JPH0735399Y2 (ja) * 1989-05-12 1995-08-09 ソニー株式会社 半導体メモリ

Also Published As

Publication number Publication date
US5128738A (en) 1992-07-07
KR920022535A (ko) 1992-12-19
EP0514095B1 (en) 1997-11-05
DE69222973D1 (de) 1997-12-11
ES2109311T3 (es) 1998-01-16
TW198131B (https=) 1993-01-11
JP2662144B2 (ja) 1997-10-08
JPH05160369A (ja) 1993-06-25
DE69222973T2 (de) 1998-03-05
EP0514095A3 (en) 1992-12-30
EP0514095A2 (en) 1992-11-19

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