KR100239099B1 - 전자 플립-플롭 회로 - Google Patents

전자 플립-플롭 회로 Download PDF

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Publication number
KR100239099B1
KR100239099B1 KR1019920009109A KR920009109A KR100239099B1 KR 100239099 B1 KR100239099 B1 KR 100239099B1 KR 1019920009109 A KR1019920009109 A KR 1019920009109A KR 920009109 A KR920009109 A KR 920009109A KR 100239099 B1 KR100239099 B1 KR 100239099B1
Authority
KR
South Korea
Prior art keywords
flip
flop circuit
clock signal
storage element
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019920009109A
Other languages
English (en)
Korean (ko)
Other versions
KR920022676A (ko
Inventor
요세피우스 마리아 벤드릭 헨드리쿠스
안토니우스 요한네스 마리아 반 덴 엘슈트 안드레아스
마리누스 후이저 코르넬리스
Original Assignee
요트.게.아. 롤페즈
코닌클리케 필립스 일렉트로닉스 엔.브이.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 요트.게.아. 롤페즈, 코닌클리케 필립스 일렉트로닉스 엔.브이. filed Critical 요트.게.아. 롤페즈
Publication of KR920022676A publication Critical patent/KR920022676A/ko
Application granted granted Critical
Publication of KR100239099B1 publication Critical patent/KR100239099B1/ko
Anticipated expiration legal-status Critical
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Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the primary-secondary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the primary-secondary type
    • H03K3/35625—Bistable circuits of the primary-secondary type using complementary field-effect transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
KR1019920009109A 1991-05-31 1992-05-28 전자 플립-플롭 회로 Expired - Fee Related KR100239099B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP91201316.6 1991-05-31
EP91201316 1991-05-31

Publications (2)

Publication Number Publication Date
KR920022676A KR920022676A (ko) 1992-12-19
KR100239099B1 true KR100239099B1 (ko) 2000-01-15

Family

ID=8207681

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920009109A Expired - Fee Related KR100239099B1 (ko) 1991-05-31 1992-05-28 전자 플립-플롭 회로

Country Status (5)

Country Link
US (1) US5264738A (enExample)
JP (1) JPH05160681A (enExample)
KR (1) KR100239099B1 (enExample)
DE (1) DE69229696T2 (enExample)
TW (1) TW198159B (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2764360B2 (ja) * 1992-05-18 1998-06-11 三菱電機株式会社 並／直列変換回路、直／並列変換回路およびそれらを含むシステム
JPH07183771A (ja) * 1993-12-22 1995-07-21 Fujitsu Ltd フリップフロップ回路
US5467038A (en) * 1994-02-15 1995-11-14 Hewlett-Packard Company Quick resolving latch
DE69533604T2 (de) * 1994-07-05 2005-02-10 Matsushita Electric Industrial Co., Ltd., Kadoma Verriegelungsschaltung
EP0713292A3 (en) * 1994-11-21 1997-10-01 Motorola Inc Feedback interlock circuit and its operating method
US5684422A (en) * 1995-01-25 1997-11-04 Advanced Micro Devices, Inc. Pipelined microprocessor including a high speed single-clock latch circuit
US5789956A (en) * 1995-05-26 1998-08-04 Texas Instruments Incorporated Low power flip-flop
US5656953A (en) * 1995-05-31 1997-08-12 Texas Instruments Incorporated Low overhead memory designs for IC terminals
US5654660A (en) * 1995-09-27 1997-08-05 Hewlett-Packard Company Level shifted high impedance input multiplexor
KR100466457B1 (ko) * 1995-11-08 2005-06-16 마츠시타 덴끼 산교 가부시키가이샤 신호전송회로,신호수신회로및신호송수신회로,신호전송방법,신호수신방법및신호송수신방법과반도체집적회로및그제어방법
JP3382144B2 (ja) * 1998-01-29 2003-03-04 株式会社東芝 半導体集積回路装置
US6188260B1 (en) * 1999-01-22 2001-02-13 Agilent Technologies Master-slave flip-flop and method
JP2000286696A (ja) * 1999-03-30 2000-10-13 Mitsubishi Electric Corp 分周回路
US20020000858A1 (en) 1999-10-14 2002-01-03 Shih-Lien L. Lu Flip-flop circuit
RU2212094C2 (ru) * 2001-11-02 2003-09-10 Российский Федеральный Ядерный Центр - Всероссийский Научно-Исследовательский Институт Экспериментальной Физики Генератор импульсов
RU2235417C2 (ru) * 2001-12-06 2004-08-27 Российский федеральный ядерный центр - Всероссийский научно-исследовательский институт технической физики им. акад. Е.И. Забабахина Генератор прямоугольных импульсов
DE10163884A1 (de) * 2001-12-22 2003-07-10 Henkel Kgaa Neue Alkalische Protease aus Bacillus sp. (DSM 14392) und Wasch- und Reinigungsmittel enthaltend diese neue Alkalische Protease
US6901570B2 (en) 2002-03-12 2005-05-31 International Business Machines Corporation Method of generating optimum skew corners for a compact device model
JP4130329B2 (ja) * 2002-04-18 2008-08-06 松下電器産業株式会社 スキャンパス回路および当該スキャンパス回路を備えた半導体集積回路
US7091742B2 (en) * 2002-12-19 2006-08-15 Tellabs Operations, Inc. Fast ring-out digital storage circuit
RU2237352C1 (ru) * 2003-03-03 2004-09-27 Российский Федеральный Ядерный Центр - Всероссийский Научно-Исследовательский Институт Экспериментальной Физики Мультивибратор
US6831494B1 (en) * 2003-05-16 2004-12-14 Transmeta Corporation Voltage compensated integrated circuits
JP4279620B2 (ja) * 2003-07-11 2009-06-17 Ｏｋｉセミコンダクタ株式会社 レベルシフト回路
DE102004008757B4 (de) * 2004-02-23 2006-04-06 Infineon Technologies Ag Paritätsprüfungs-Schaltung zur kontinuierlichen Prüfung der Parität einer Speicherzelle
US7142018B2 (en) 2004-06-08 2006-11-28 Transmeta Corporation Circuits and methods for detecting and assisting wire transitions
US7304503B2 (en) * 2004-06-08 2007-12-04 Transmeta Corporation Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability
US7635992B1 (en) 2004-06-08 2009-12-22 Robert Paul Masleid Configurable tapered delay chain with multiple sizes of delay elements
US7405597B1 (en) 2005-06-30 2008-07-29 Transmeta Corporation Advanced repeater with duty cycle adjustment
US7656212B1 (en) 2004-06-08 2010-02-02 Robert Paul Masleid Configurable delay chain with switching control for tail delay elements
US7498846B1 (en) 2004-06-08 2009-03-03 Transmeta Corporation Power efficient multiplexer
US7173455B2 (en) 2004-06-08 2007-02-06 Transmeta Corporation Repeater circuit having different operating and reset voltage ranges, and methods thereof
US7336103B1 (en) * 2004-06-08 2008-02-26 Transmeta Corporation Stacked inverter delay chain
US7071747B1 (en) * 2004-06-15 2006-07-04 Transmeta Corporation Inverting zipper repeater circuit
US7330080B1 (en) 2004-11-04 2008-02-12 Transmeta Corporation Ring based impedance control of an output driver
US7592842B2 (en) * 2004-12-23 2009-09-22 Robert Paul Masleid Configurable delay chain with stacked inverter delay elements
US7634749B1 (en) * 2005-04-01 2009-12-15 Cadence Design Systems, Inc. Skew insensitive clocking method and apparatus
JP5086993B2 (ja) 2005-06-01 2012-11-28 テクラテック・アクティーゼルスカブ 複数の回路にタイミング信号を提供するための方法及び装置、集積回路並びにノード
US7663408B2 (en) * 2005-06-30 2010-02-16 Robert Paul Masleid Scannable dynamic circuit latch
US20070013425A1 (en) * 2005-06-30 2007-01-18 Burr James B Lower minimum retention voltage storage elements
US7394681B1 (en) 2005-11-14 2008-07-01 Transmeta Corporation Column select multiplexer circuit for a domino random access memory array
US7642866B1 (en) 2005-12-30 2010-01-05 Robert Masleid Circuits, systems and methods relating to a dynamic dual domino ring oscillator
US7414485B1 (en) 2005-12-30 2008-08-19 Transmeta Corporation Circuits, systems and methods relating to dynamic ring oscillators
US8067970B2 (en) * 2006-03-31 2011-11-29 Masleid Robert P Multi-write memory circuit with a data input and a clock input
US7495466B1 (en) * 2006-06-30 2009-02-24 Transmeta Corporation Triple latch flip flop system and method
US7710153B1 (en) * 2006-06-30 2010-05-04 Masleid Robert P Cross point switch
US7995618B1 (en) * 2007-10-01 2011-08-09 Teklatech A/S System and a method of transmitting data from a first device to a second device
US9985611B2 (en) * 2015-10-23 2018-05-29 Intel Corporation Tunnel field-effect transistor (TFET) based high-density and low-power sequential

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4473760A (en) * 1982-12-13 1984-09-25 Western Digital Corporation Fast digital sample resolution circuit
US4663546A (en) * 1986-02-20 1987-05-05 Motorola, Inc. Two state synchronizer
US4929850A (en) * 1987-09-17 1990-05-29 Texas Instruments Incorporated Metastable resistant flip-flop
JPH0229124A (ja) * 1988-07-19 1990-01-31 Toshiba Corp スタンダードセル
JP2621993B2 (ja) * 1989-09-05 1997-06-18 株式会社東芝 フリップフロップ回路
US5132577A (en) * 1991-04-11 1992-07-21 National Semiconductor Corporation High speed passgate, latch and flip-flop circuits

Also Published As

Publication number Publication date
DE69229696D1 (de) 1999-09-09
DE69229696T2 (de) 2000-02-17
US5264738A (en) 1993-11-23
KR920022676A (ko) 1992-12-19
TW198159B (enExample) 1993-01-11
JPH05160681A (ja) 1993-06-25

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