KR100237824B1 - Method for forming mosfet - Google Patents
Method for forming mosfet Download PDFInfo
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- KR100237824B1 KR100237824B1 KR1019960020676A KR19960020676A KR100237824B1 KR 100237824 B1 KR100237824 B1 KR 100237824B1 KR 1019960020676 A KR1019960020676 A KR 1019960020676A KR 19960020676 A KR19960020676 A KR 19960020676A KR 100237824 B1 KR100237824 B1 KR 100237824B1
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- gas
- etching
- film
- gate
- tungsten silicide
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- 238000000034 method Methods 0.000 title abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 66
- 239000007789 gas Substances 0.000 claims abstract description 57
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 47
- 229920005591 polysilicon Polymers 0.000 claims abstract description 47
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 35
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims abstract description 18
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910001882 dioxygen Inorganic materials 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000001307 helium Substances 0.000 claims abstract description 12
- 229910052734 helium Inorganic materials 0.000 claims abstract description 12
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229960000909 sulfur hexafluoride Drugs 0.000 claims abstract description 10
- 229910018503 SF6 Inorganic materials 0.000 claims abstract description 9
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims abstract description 7
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 239000000460 chlorine Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000000203 mixture Substances 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract 1
- 229920000642 polymer Polymers 0.000 description 7
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 206010010144 Completed suicide Diseases 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- 241000243321 Cnidaria Species 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Ceramic Engineering (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 MOS트랜지스터의 게이트 패턴 형성 방법에 관한 것이다.The present invention relates to a method of forming a gate pattern of a MOS transistor.
본 발명은, 반도체기판 상에 게이트산화막, 폴리실리콘막, 텅스텐실리사이드막 및 마스크산화막을 순차적으로 형성한 후, 상기 마스크산화막을 사진식각함으로서 게이트마스크를 형성하는 단계, 상기 게이트마스크를 식각마스크로하여 상기 텅스텐실리사이드막을 육불화황가스, 염소가스 및 헬륨가스 속에 희석된 산소가스로 이루어진 혼합가스를 사용하여 식각하는 단계, 상기 폴리실리콘막을 상기 텅스텐실리사이드막의 식각시에 사용된 동일한 혼합가스를 상기 폴리실리콘막에 대한 상기 텅스텐실리사이드막의 식각선택비가 0.6:1~0.8:1가 되도록 조절하여 식각하는 단계 및 상기 게이트산화막을 상기 게이트마스크와 염소가스, 브롬화수소가스 및 헬륨가스 속에 희석된 산소가스로 이루어진 혼합가스 또는 염소가스와 산소가스로 이루어진 혼합가스를 사용하여 오버식각하는 단계를 구비하여 이루어진다.The present invention provides a method of manufacturing a semiconductor device, comprising: sequentially forming a gate oxide film, a polysilicon film, a tungsten silicide film, and a mask oxide film on a semiconductor substrate and then photo-etching the mask oxide film to form a gate mask; Etching the tungsten silicide film using a mixed gas composed of sulfur hexafluoride gas, chlorine gas, and helium gas diluted with oxygen gas; depositing the same mixed gas used for etching the tungsten silicide film on the polysilicon film, Etching the tungsten silicide film so that the etching selectivity ratio of the tungsten silicide film to the film is 0.6: 1 to 0.8: 1; and etching the gate oxide film to a mixture of the gate mask and the oxygen gas diluted with chlorine gas, hydrogen bromide gas, and helium gas A mixture of gas or chlorine gas and oxygen gas And performing over-etching using the etching gas.
따라서, 본 발명은 게이트패턴 식각공정에서 텅스텐실리사이드와 폴리실리콘찌꺼기를 완전히 제거하고 반도체기판의 피팅 등의 손상을 방지하여 반도체소자의 신뢰성을 향상시키는 효과가 있다.Therefore, the present invention has the effect of completely removing the tungsten silicide and polysilicon residue in the gate pattern etching process and preventing damage to the fittings of the semiconductor substrate, thereby improving the reliability of the semiconductor device.
Description
본 발명은 모스(Metal Oxide Semiconductor:이하, ‘MOS’라 함)트랜지스터의 게이트 형성 방법에 관한 것으로서, 보다 상세하게는 게이트막 도포 후 게이트 패턴을 형성하는 건식식각공정에서 발생하는 문제를 해결할 수 있는 MOS트랜지스터의 게이트 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate forming method of a MOS (Metal Oxide Semiconductor) transistor, and more particularly, to a method of forming a gate pattern To a method of forming a gate of a MOS transistor.
반도체가 고집적화되고 MOS트랜지스터의 채널 길이가 짧아짐에 따라 트랜지스터의 게이트는 폴리실리콘막을 사용하게 되었는 데, 폴리실리콘막은 소스/드레인 접합을 형성하는데 필요한 고온공정에 적합하고 폴리실리콘-게이트산화막 계면특성이 우수한 반면, 면저항이 상대적으로 크기 때문에 게이트를 통한 신호의 전송이 지연되는 단점을 갖고 있다. 이러한 단점을 해결하기 위해 제안된 방법이 폴리실리콘게이트의 상부에 내화금속실리사이드를 사용하는 방법이다.As the semiconductor becomes highly integrated and the channel length of the MOS transistor becomes shorter, the gate of the transistor uses the polysilicon film. The polysilicon film is suitable for the high temperature process necessary for forming the source / drain junction and is excellent in the interfacial polysilicon- On the other hand, since the sheet resistance is relatively large, the transmission of the signal through the gate is delayed. To overcome this disadvantage, the proposed method is to use a refractory metal silicide on top of the polysilicon gate.
그런데, 상기와 같이 MOS트랜지스터의 게이트를 폴리실리콘과 금속실리사이드의 이중막으로 형성하는 경우 게이트 패턴을 형성하는 건식식각공정에서 이중막을 차례로 식각해야 하기 때문에 바람직한 식각공정조건을 맞추기가 어렵게 된다.However, when the gate of the MOS transistor is formed of a double layer of polysilicon and metal silicide as described above, it is difficult to meet the desired etching process conditions because the double layer must be etched in sequence in the dry etching process for forming the gate pattern.
종래의 MOS트랜지스터의 게이트 형성 방법에 있어서, 게이트 패턴형성공정은 게이트마스크산화막을 형성한 후 금속실리사이드막과 폴리실리콘막을 차례로 식각하는 주식각공정(Main Etching Process)와 게이트산화막 위에 잔존하는 폴리실리콘 등의 찌꺼기를 제거하기 위한 오버식각공정(Over Etching Process)으로 이루어지며, 이때 주로 사용되는 식각가스로는 염소가스(Cl2)/질소가스(N2) 또는 염소가스/산소가스(O2)가 있다.In the conventional method of forming a gate of a MOS transistor, the gate pattern forming process includes a main etching process for sequentially etching the metal silicide film and the polysilicon film after the gate mask oxide film is formed, polysilicon remaining on the gate oxide film (Cl 2 ) / nitrogen gas (N 2 ) or chlorine gas / oxygen gas (O 2 ) are used as etch gases mainly used for the etching process. .
그러나 상기 가스를 사용하여 식각을 진행하면 산화막에 대한 식각선택비가 우수하여, 식각 후 기판의 손상을 줄일 수 있으나 식각 중에 폴리머가 과다하게 형성되어 많은 파티클이 발생하는 문제점이 있었다.However, if the etching is performed using the above-mentioned gas, the etching selectivity to the oxide film is excellent, so that the damage of the substrate after etching can be reduced, but the polymer is excessively formed in the etching process.
이에 대해서 상기 파티클의 발생을 방지하기 위하여 육불화황가스(SF6)/염소가스를 이용한 식각공정을 수행하면 산화막에 대한 식각선택도가 불량하여 하부막에 피팅(Pitting)이 발생하는 문제점이 있었다.On the other hand, if an etching process using sulfur hexafluoride gas (SF 6 ) / chlorine gas is performed in order to prevent the generation of the particles, there is a problem that the etching selectivity to the oxide film is poor and pitting occurs in the bottom film .
본 발명의 목적은, MOS트랜지스터의 게이트 패턴을 형성하는 건식식각공정에서 금속실리사이드막 식각시 파티클이 과다하게 발생하는 것을 방지할 수 있는 MOS트랜지스터의 게이트 형성 방법을 제공하는 것이다.It is an object of the present invention to provide a method of forming a gate of a MOS transistor which can prevent excessive generation of particles during etching of a metal silicide film in a dry etching process for forming a gate pattern of a MOS transistor.
본 발명의 다른 목적은, MOS트랜지스터의 게이트 패턴을 형성하는 건식식각공정에서 폴리실리콘막 식각시 폴리실리콘막 표면에 잔존하는 금속실리사이드 찌꺼기를 신속하게 제거하여 하부막에 피팅이 발생하는 것을 방지할 수 있는 MOS트랜지스터의 게이트 형성 방법을 제공하는 것이다.It is another object of the present invention to provide a method of manufacturing a semiconductor device capable of quickly removing metal silicide remnants remaining on the surface of a polysilicon film during a dry etching process for forming a gate pattern of a MOS transistor, A method of forming a gate of a MOS transistor is provided.
본 발명의 또 다른 목적은 MOS트랜지스터의 게이트 패턴을 형성하는 건식식각공정에서 폴리실리콘막을 식각한 후 소스/드레인 영역의 산화막 위에 잔존하는 폴리실리콘 찌꺼기 및 스트링어(Stringer)를 제거하고 하부기판의 피팅을 방지할 수 있는 MOS트랜지스터의 게이트 형성 방법을 제공하는 것이다.It is still another object of the present invention to provide a method of manufacturing a semiconductor device, which comprises etching a polysilicon film in a dry etching process for forming a gate pattern of a MOS transistor, removing polysilicon residue and stringer remaining on the oxide film of the source / drain region, A gate electrode, and a gate electrode.
제1도는 본 발명에 따른 모스트랜지스터의 게이트 형성 방법을 나타내는 웨이퍼 단면도로서,FIG. 1 is a cross-sectional view of a wafer showing a method of forming a gate of a MOS transistor according to the present invention,
제1(a)도는 게이트가 형성될 영역에 산화막마스크가 형성된 상태를 나타내는 액티브영역의 단면도이고,1 (a) is a cross-sectional view of an active region showing a state in which an oxide film mask is formed in a region where a gate is to be formed,
제1(b)도는 텅스텐실리사이드 식각공정을 진행한 후의 액티브영역을 나타내는 단면도이며,FIG. 1 (b) is a cross-sectional view showing an active region after the tungsten silicide etching process,
제1(c)도는 폴리실리콘 식각공정을 진행한 후의 액티브영역을 나타내는 단면도이고,1 (c) is a cross-sectional view showing an active region after the polysilicon etching process is performed,
제1(d)도는 오버식각공정을 진행한 후의 액티브영역을 나타내는 단면도이다.Fig. 1 (d) is a cross-sectional view showing the active region after the over-etching process.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
10 : 반도체 기판 12 : 게이트산화막10: semiconductor substrate 12: gate oxide film
14 : 폴리실리콘막 16 : 텅스텐실리사이드막14: polysilicon film 16: tungsten silicide film
18 : 산화막 20 : 텅스텐실리사이드 찌꺼기18: oxide film 20: tungsten silicide residue
22 : 폴리실리콘 찌꺼기22: Polysilicon residue
상기 목적을 달성하기 위한 본 발명에 따른 MOS트랜지스터의 게이트 형성방법은, 반도체기판 상에 게이트산화막, 폴리실리콘막, 텅스텐실리사이드막 및 마스크산화막을 순차적으로 형성한 후, 상기 마스크산화막을 사진식각함으로서 게이트마스크를 형성하는 단계; 상기 게이트마스크를 식각마스크로하여 상기 텅스텐실리사이드막을 육불화황가스(SF6), 염소가스(Cl2) 및 헬륨가스 속에 희석된 산소가스(O2)로 이루어진 혼합가스를 사용하여 식각하는 단계; 상기 폴리실리콘막을 상기 텅스텐실리사이드막의 식각시에 사용된 동일한 혼합가스를 상기 폴리실리콘막에 대한 상기 텅스텐실리사이드막의 식각선택비가 0.6:1~0.8:1가 되도록 조절하여 식각하는 단계; 및 상기 게이트산화막을 상기 게이트마스크와 염소가스(Cl2), 브롬화수소가스(HBr) 및 헬륨가스(He) 속에 희석된 산소가스(O2)로 이루어진 혼합가스를 사용하여 오버식각하는 단계; 를 구비하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a gate of a MOS transistor, comprising: sequentially forming a gate oxide film, a polysilicon film, a tungsten silicide film and a mask oxide film on a semiconductor substrate, Forming a mask; Etching the tungsten silicide film using a mixed gas of sulfur hexafluoride gas (SF 6 ), chlorine gas (Cl 2 ), and oxygen gas (O 2 ) diluted in helium gas using the gate mask as an etching mask; Etching the polysilicon film such that the same mixed gas used when the tungsten silicide film is etched is etched so that the etch selectivity ratio of the tungsten silicide film to the polysilicon film becomes 0.6: 1 to 0.8: 1; And over-etching the gate oxide using a gate gas and a mixed gas of oxygen gas (O 2 ) diluted in chlorine gas (Cl 2 ), hydrogen bromide gas (HBr) and helium gas (He); And a control unit.
본 발명에 따른 다른 MOS트랜지스터의 게이트 형성 방법은, 반도체기판상에 게이트산화막, 폴리실리콘막, 텅스텐실리사이드 및 마스크산화막을 순차적으로 형성한 후, 상기 마스크산화막을 사진식각함으로서 게이트마스크를 형성하는 단계; 상기 게이트마스크를 식각마스크로하여 상기 턴스텐실리사이드막을 육불화황가스(SF6), 염소가스(Cl2) 및 헬륨가스 속에 희석된 산소가스(O2)로 이루어진 혼합가스를 사용하여 식각하는 단계; 상기 폴리실리콘막을 상기 텅스텐실리사이드의 식각시에 사용된 동일한 혼합가스를 상기 폴리실리콘막에 대한 상기 텅스텐실리사이드의 식각선택비가 0.6:1~0.8:1가 되도록 조절하여 식각하는 단계; 및 상기 게이트산화막을 상기 게이트마스크와 염소가스(Cl2)와 산소가스(O2)로 이루어진 혼합가스를 사용하여 오버식각하는 단계; 를 구비하여 이루어지는 것을 특징으로 한다.Another gate forming method of a MOS transistor according to the present invention comprises: sequentially forming a gate oxide film, a polysilicon film, a tungsten silicide film and a mask oxide film on a semiconductor substrate, and then photo-etching the mask oxide film to form a gate mask; Etching the turnsten silicide film using a mixed gas composed of sulfur hexafluoride gas (SF 6 ), chlorine gas (Cl 2 ) and oxygen gas (O 2 ) diluted in helium gas using the gate mask as an etching mask ; Etching the polysilicon film such that the etch selectivity ratio of the tungsten silicide to the polysilicon film is from 0.6: 1 to 0.8: 1; and etching the polysilicon film with the same mixed gas used for etching the tungsten silicide; And over-etching the gate oxide film using the gate mask and a mixed gas of chlorine gas (Cl 2 ) and oxygen gas (O 2 ); And a control unit.
이하, 본 발명의 구체적인 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.
먼저, 공지된 바와 같이, MOS트랜지스터의 게이트를 형성하기 위해 반도체 기판(10)에 MOS트랜지스터가 형성될 액티브영역을 형성한 후 게이트산화막(12)을 약 1000Å 성장시키고 그 위에 게이트전극으로 사용되는 폴리실리콘막(14)과 텅스텐실리사이드(16)을 각각 약 100Å과 1500Å 도포한다.First, as is known, an active region in which a MOS transistor is to be formed is formed in a semiconductor substrate 10 to form a gate of a MOS transistor, and then a gate oxide film 12 is grown to a thickness of about 1000 angstroms, The silicon film 14 and the tungsten silicide 16 are applied to about 100 Å and 1500 Å, respectively.
그 다음, 제1(a)도에 도시된 바와 같이, 마스크로 사용될 산화막(18)을 텅스텐실리사이드(16) 상에 약 5,000Å 정도 도포한 후 포토레지스트를 이용한 사진 및 식각공정을 진행하여 상기 산화막(18)으로 게이트마스크를 형성한다.Next, as shown in FIG. 1 (a), an oxide film 18 to be used as a mask is coated on the tungsten silicide 16 to a thickness of about 5,000 Å, and then a photolithography and etching process is performed, (18).
상기한 바와 같이 산호막(18)을 게이트마스크로 사용하는 이유는 후속공정의 수행에 의해서 게이트를 형성하기 위한 상기 폴리실리콘막(14)과 텅스텐실리사이드(16)의 식각시 그 하부에 있는 게이트산화막(12)이 과다하게 식각되는 것을 방지하기 위해 산화막에 대한 식각선택비가 높은 공정조건을 사용하기 위함이다.The reason why the coral film 18 is used as a gate mask as described above is that the polysilicon film 14 and the tungsten silicide 16 for forming the gate by the subsequent process are etched, In order to prevent the oxide film 12 from being excessively etched.
다음으로, 제1(b)도와 같이, 상기 게이트마스크를 이용하여 텅스텐실리사이드(16)을 식각하게 되는 데, 이때의 공정조건은 패턴 프로파일과 패턴임계치수를 제어하기 위해 폴리실리콘에 대한 텅스텐실리사이드의 식각선택비가 낮도록 유지되어야 하며, 본 발명의 일 실시예에서의 식각가스는 육불화황가스(SF6)와 염소가스(Cl2)로 이루어지는 주식각가스와 헬륨(He)가스속에 희석된 산소가스(O2)로 이루어지는 보조가스로 이루어진 혼합가스이며, 상기 육불화황가스의 불소(F)성분은 폴리머에 대한 반응성이 높아 폴리머의 식각특성이 우수함으로서 폴리머 생성율이 낮고, 상기 헬륨가스는 플라즈마를 활성화시키는 특성이 있으며, 상기 산소가스는 산화막의 식각율은 낮게 하는 특성이 있다.Next, as shown in FIG. 1 (b), the tungsten silicide 16 is etched by using the gate mask. At this time, the process conditions include a tungsten suicide to polysilicon should be maintained etch selection ratio to be lower, the etching gas in one embodiment of the present invention is oxygen diluted in a sulfur hexafluoride gas (SF 6) and chlorine gas (Cl 2) CO respective gas and helium (He) gas consisting of gas and a gas mixture consisting of a secondary gas consisting of (O 2), fluorine (F) component of the sulfur hexafluoride gas is low and the polymer production rate by reactive high excellent etching properties of the polymer for the polymer, wherein the helium gas plasma And the oxygen gas has a characteristic of lowering the etching rate of the oxide film.
따라서, 본 발명에 의해서 텅스텐실리사이드막(16)의 폴리머의 발생을 최소화할 수 있는 상기 식각가스를 사용하여 식각함으로서 파티클에 의한 공정불량을 최소화할 수 있다.Therefore, by using the etching gas that minimizes the generation of the polymer of the tungsten silicide film 16 according to the present invention, it is possible to minimize process defects due to particles.
텅스텐실리사이드(16)의 식각이 진행된 후 노출된 폴리실리콘막(14) 위에는 텅스텐실리사이드 찌꺼기(20)가 잔존하게 된다. 그러므로 텅스텐실리사이드막(16)을 식각하는 공정조건을 사용하여 폴리실리콘막(14)을 식각하게 되면, 상기 공정조건은 폴리실리콘막(14)에 대한 텅스텐실리사이드(16)의 식각선택비가 낮으므로, 식각이 진행되면서 상기 폴리실리콘막(14)이 모두 식각되기 전에 소스/드레인 영역 상의 게이트산화막(12)이 노출되고 상기 산화막(18)이 부분적으로 폴리실리콘막(14)과 함께 식각되어 반도체기판(10)에 피팅이 발생할 확률이 높아지게 된다. 만일, 이러한 피팅이 발생하는 것을 방지하기 위해 산화막(18)에 대한 식각선택비가 매우 높은 염소가스/산소가스를 사용하는 공정조건을 사용하면 텅스텐실리사이드의 제거능력이 떨어져 게이트전극들 사이에 미세한 브리지가 형성된다.The tungsten suicide residue 20 remains on the exposed polysilicon film 14 after the tungsten silicide 16 is etched. Therefore, if the polysilicon film 14 is etched using the process conditions for etching the tungsten silicide film 16, the etching conditions for the tungsten suicide 16 to the polysilicon film 14 are low, The gate oxide film 12 on the source / drain regions is exposed and the oxide film 18 is partially etched together with the polysilicon film 14 before the polysilicon film 14 is etched as the etching proceeds. 10) is increased. If process conditions using a chlorine gas / oxygen gas with a very high etch selectivity for the oxide film 18 are used to prevent such fittings from occurring, the tungsten suicide removal capability will be poor and a fine bridge between the gate electrodes .
따라서, 폴리실리콘막(14)의 식각공정은 반도체기판(10) 상의 게이트산화막(12)의 피팅을 방지할 수 있고 텅스텐실리사이드 찌꺼기(20)에 대한 제거능력도 뛰어난 공정조건을 사용하여 식각이 이루어져야 하는데, 이러한 공정조건은 상기 텅스텐실리사이드막(16)을 식각할 때와 동일한 구성의 식각가스 즉, 육불화황가스와 염소가스 및 헬륨가스 속에 희석된 산소가스가 혼합된 식각가스를 사용하고 식각챔버 내에 인가되는 파워(Power), 압력, 식각가스량, 및 식각가스 조성비 등의 공정조건을 조절하여 상기 폴리실리콘막(14)에 대한 상기 텅스텐실리사이드(16)의 식각선택비가 0.6:1 내지 0.8:1인 것이 바람직하다.The etching process of the polysilicon film 14 should be etched using process conditions that can prevent fitting of the gate oxide film 12 on the semiconductor substrate 10 and also have excellent removal capability for the tungsten silicide remnant 20 The etching conditions are the same as those used for etching the tungsten silicide film 16, that is, etching gas mixed with sulfur hexafluoride gas, chlorine gas, and oxygen gas diluted in helium gas, The etching selectivity ratio of the tungsten silicide 16 to the polysilicon film 14 is controlled to be in a range of 0.6: 1 to 0.8: 1 (inclusive) by controlling process conditions such as power, pressure, etching gas amount, .
본 발명에 의한 상기 폴리실리콘막(14)의 식각공정은 플라즈마를 이용한 건식식각공정이며, 상기 식각공정조건은 식각공정이 진행되는 공정챔버의 내부압력이 25mTorr 내지 35mTorr로 유지되고, 상기 공정챔버 내부에 플라즈마 형성을 위해서 인가되는 파워(Power)가 100W 내지 275W로 이루어지고, 육불화황가스와 염소가스의 공급량의 비율이 15:20으로 이루어질 수 있다.The etching process of the polysilicon film 14 according to the present invention is a dry etching process using plasma, and the etching process conditions are such that the internal pressure of the process chamber in which the etching process is performed is maintained at 25 mTorr to 35 mTorr, The power applied for forming the plasma is 100 W to 275 W, and the ratio of the amount of the hexafluorosulfur gas to the supply amount of the chlorine gas is 15:20.
제1(c)도와 같이, 상기한 바와 같은 공정조건을 사용하여 폴리실리콘막(14)을 식각하게 되면, 텅스텐실리사이드 찌꺼기(20) 및 폴리실리콘막(14)은 제거되나 게이트산화막(12) 위에는 폴리실리콘막 찌꺼기(22)가 남아 있게 된다. 이러한 폴리실리콘 찌꺼기(22)를 제거하기 위하여 오버식각을 수행하며, 이때 게이트산화막(12)의 소모를 최소화하기 위해서 산화막에 대한 폴리실리콘막(14)의 식각선택비가 매우 높아 게이트산화막(12)에 피팅이 발생하지 않는 공정조건을 필요로 한다. 본 발명의 일 실시예의 오버식각가스로 염소가스(Cl2)와 브롬화수소가스(HBr) 및 헬륨(He)가스 속에 희석된 산소가스(O2)로 구성된 혼합가스를 사용하며, 다른 예로 염소가스와 산소가스로 이루어진 혼합가스를 사용할 수도 있다.The tungsten silicide remnant 20 and the polysilicon film 14 are removed while the polysilicon film 14 is etched using the above process conditions as in the first process (c), but on the gate oxide film 12 The polysilicon film residue 22 remains. In order to minimize the consumption of the gate oxide film 12, an etching selectivity of the polysilicon film 14 to the oxide film is very high, so that the gate oxide film 12 is formed on the gate oxide film 12 A process condition in which no fitting occurs is required. A mixed gas composed of chlorine gas (Cl 2 ), hydrogen bromide gas (HBr) and oxygen gas (O 2 ) diluted in helium (He) gas is used as the over etch gas of one embodiment of the present invention, And oxygen gas may be used.
제1(d)도와 같이, 상기와 같은 식각가스를 사용하여 오버식각공정을 진행하게 되면, 폴리실리콘 찌꺼기(22)가 완전 제거된 게이트산화막(12)이 드러나는 게이트 패턴이 형성된다.As shown in FIG. 1 (d), when the over-etching process is performed using the etching gas as described above, a gate pattern is formed to expose the gate oxide film 12 from which the polysilicon residue 22 has been completely removed.
따라서, 본 발명의 MOS트랜지스터의 게이트 형성 방법에 의하면, 게이트패턴 식각공정에서 텅스텐실리사이드막을 식각하는 과정에 폴리머의 발생이 방지되고, 폴리실리콘막을 식각하는 과정에 게이트산화막을 피팅시키는 것을 방지하며 텅스텐실리사이드 찌꺼기 및 폴리실리콘막을 식각하고, 이후 폴리실리콘막 찌꺼기를 효과적으로 제거할 수 있다.Therefore, according to the gate forming method of the MOS transistor of the present invention, the generation of polymer is prevented in the process of etching the tungsten silicide film in the gate pattern etching process, the gate oxide film is prevented from fitting in the process of etching the polysilicon film, The residue and the polysilicon film can be etched, and the polysilicon film residue can be effectively removed thereafter.
따라서, 폴리머에 의한 파티클 발생을 최소화하고, 게이트산화막의 피팅을 방지하여 게이트 패턴을 형성함으로서 완성된 반도체소자의 신뢰성을 향상시킬 수 있는 효과가 있다.Therefore, it is possible to minimize the generation of particles by the polymer, prevent the gate oxide film from being fitted, and improve the reliability of the completed semiconductor device by forming the gate pattern.
이상에서 본 발명은 기재된 구체예에 대해서만 상세히 설명되었지만 본 발명의 기술사상 범위 내에서 다양한 변형 및 수정이 가능함은 당업자에게 있어서 명백한 것이며, 이러한 변형 및 수정이 첨부된 특허청구범위에 속함은 당연한 것이다.While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims.
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| KR1019960020676A KR100237824B1 (en) | 1996-06-10 | 1996-06-10 | Method for forming mosfet |
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| Country | Link |
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| KR (1) | KR100237824B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100642903B1 (en) * | 1999-10-20 | 2006-11-03 | 매그나칩 반도체 유한회사 | Forming method of gate electrode in semiconductor device |
| KR100632644B1 (en) * | 1999-12-27 | 2006-10-11 | 주식회사 하이닉스반도체 | Method of etching a polysilicon layer in a semiconductor device |
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1996
- 1996-06-10 KR KR1019960020676A patent/KR100237824B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR980005875A (en) | 1998-03-30 |
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