KR980005875A - Gate forming method of MOS transistor - Google Patents

Gate forming method of MOS transistor Download PDF

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KR980005875A
KR980005875A KR1019960020676A KR19960020676A KR980005875A KR 980005875 A KR980005875 A KR 980005875A KR 1019960020676 A KR1019960020676 A KR 1019960020676A KR 19960020676 A KR19960020676 A KR 19960020676A KR 980005875 A KR980005875 A KR 980005875A
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gas
etching
gate
polysilicon
film
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KR100237824B1 (en
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석종욱
정연해
전병구
문경섭
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김광호
삼성전자 주식회사
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    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

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Abstract

MOS트랜지스터의 게이트패턴을 형성하는 식각공정에서 발생하는 게이트막 찌꺼기 잔류문제, 기판의 손상문제 등을 해결하기 위한 MOS트랜지스터의 게이트 형성 방법이 개시되어 있다. 본 발명은, MOS트랜지스터의 게이트 형성 방법에 있어서, 상기 금속 실리사이드막의 식각공정은 상기 폴리실리콘막에 대한 상기 금속실리사이드막의 식각선택비가 낮은 공정조건으로 수행하며, 상기 폴리실리콘막의 식각공정은 폴리 실리콘과 상기 산화막에 대한 금속 실리사이드의 식각선택비가 높은 공정조건으로 수행하며, 상기 소스/드레인 영역상의 상기 게이트산화막을 산화막에 대한 폴리실리콘의 식각선택비가 높은 공정조건으로 오버식각을 수행함을 특징으로 하여 이루어진다. 따라서 본발명은 게이트패턴 식각공정에서 텅스텐실리사이드와 폴리실리콘 찌꺼기를 완전히 제거하고 반도체기판의 피팅 등의 손상을 방지하여 반도체소자의 신뢰성을 향상시키는 효과가 있다.Disclosed is a gate forming method of a MOS transistor for solving a gate film residue problem, a substrate damage problem, and the like, which occur in an etching process of forming a gate pattern of a MOS transistor. In the method of forming a gate of a MOS transistor, the etching process of the metal silicide layer is performed under a process condition having a low etching selectivity of the metal silicide layer relative to the polysilicon layer, and the etching process of the polysilicon layer is performed using polysilicon. The etching selectivity of the metal silicide with respect to the oxide film is performed under a high process condition, and the gate oxide film on the source / drain region is overetched under a process condition with a high etching selectivity of polysilicon with respect to an oxide film. Therefore, the present invention has the effect of completely removing the tungsten silicide and polysilicon residues in the gate pattern etching process and preventing damages such as fitting of the semiconductor substrate to improve the reliability of the semiconductor device.

Description

모스(MOS)트랜지스터의 게이트 형성 방법Gate forming method of MOS transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 모스트랜지스터의 게이트 형성방법을 나타내는 웨이퍼 단면도.1 is a sectional view of a wafer showing a gate forming method of a MOS transistor according to the present invention.

제1a도는 게이트가 형성될 영역에 산화막마스크가 형성된 상태를 나타내는 액티브영역의 단면도.1A is a cross-sectional view of an active region showing a state in which an oxide film mask is formed in a region where a gate is to be formed.

제1b도는 텅스텐실리사이드 식각공정을 진행한 후의 액티브영역을 나타내는 단면도.1B is a cross-sectional view showing an active region after a tungsten silicide etching process is performed.

제1c도는 폴리실리콘 식각공정을 진행한 후의 액티브영역을 나타내는 단면도.1C is a cross-sectional view showing an active region after a polysilicon etching process is performed.

제1d도는 오버식각공정을 진행한 후의 액티브 영역을 나타내는 단면도.1D is a cross-sectional view showing an active region after an overetch process is performed.

Claims (19)

게이트산화막 위에 게이트전극으로 사용될 폴리실리콘막과 금속실리사이드막 및 마스크로 사용될 마스크산화막을 차례로 도포하고 사진공정을 수행하여 포토레지스트로 게이트 패턴을 형성한 후 상기 마스크산화막을 식각하여 산화막으로 게이트마스크를 형성하고 소스/드레인 영역상의 상기 금속실리사이드막과 폴리실리콘막을 식각함으로써 이루어지는 MOS트랜지스터의 게이트 형성 방법에 있어서, 상기 금속실리사이드막의 식각공정은 상기 폴리실리콘막에 대한 상기 금속실리사이드막의 식각선택비가 낮은 공정으로 수행됨을 특징으로 하는 MOS트랜지스터의 게이트 형성 방법.A polysilicon film to be used as a gate electrode, a metal silicide film, and a mask oxide film to be used as a mask are sequentially applied on the gate oxide film, a photo process is performed to form a gate pattern using a photoresist, and the mask oxide film is etched to form a gate mask using an oxide film. And etching the metal silicide layer and the polysilicon layer on the source / drain region, wherein the etching process of the metal silicide layer is performed by a process in which the etch selectivity of the metal silicide layer with respect to the polysilicon layer is low. A method of forming a gate of a MOS transistor, characterized in that. 게이트산화막 위에 게이트전극으로 사용될 폴리실리콘막과 금속실리사이드막 및 마스크로 사용될 마스크산화막을 차례로 도포하고 사진공정을 수행하여 포토래지스트로 게이트 패턴을 형성한 후 상기 마스크산화막을 식각하여 산화막으로 게이트마스크를 형성하고 소스/드레인 영역상의 상기 금속실리사이드막과 폴리실리콘막을 식각함으로써 이루어지는 MOS트랜지스터의 게이트 형성 방법에 있어서, 상기 폴리실리콘막의 식각공정은 폴리실리콘과 상기 산화막에 대한 금속실리사이드의 식각선택비가 높은 공정조건으로 수행함을 특징으로 하는 MOS트랜지스터의 게이트 형성 방법.A polysilicon film to be used as a gate electrode, a metal silicide film, and a mask oxide film to be used as a mask are coated on the gate oxide film, and a photo process is performed to form a gate pattern using a photoresist. The mask oxide film is then etched to form a gate mask using an oxide film. In the method of forming a gate of a MOS transistor formed by forming and etching the metal silicide film and the polysilicon film on the source / drain region, the etching process of the polysilicon film is a process condition with a high etching selectivity of the metal silicide with respect to the polysilicon and the oxide film The method of forming a gate of a MOS transistor, characterized in that performed by. 게이트산화막 위에 게이트전극으로 사용될 폴리실리콘막과 금속실리사이드막 및 마스크로 사용될 마스크산화막을 차례로 도포하고 사진공정을 수행하여 포토레지스트로 게이트 패턴을 형성한 후 상기 마스크 산화막을 식각하여 산화막으로 게이트마스크를 형성하고 소스/드레인 영역상의 상기 금속 실리사이드막과 폴리실리콘막을 식각함으로써 이루어지는 MOS트랜지스터의 게이트 형성 방법에 있어서, 상기 소스/드레인 영역상의 상기 게이트산화막을 산화막에 대한 폴리실리콘의 식각선택비가 높은 공정조건으로 오버식각으로 수행함을 특징으로 하는 MOS트랜지스터의 게이트 형성 방법.A polysilicon layer to be used as a gate electrode, a metal silicide layer, and a mask oxide layer to be used as a mask are coated on the gate oxide layer, and a photo process is performed to form a gate pattern using a photoresist. The mask oxide layer is etched to form a gate mask using an oxide layer. And etching the metal silicide film and the polysilicon film on the source / drain region, wherein the gate oxide film on the source / drain region is over the process conditions with high etching selectivity of polysilicon to an oxide film. A method of forming a gate of a MOS transistor, characterized in that performed by etching. 제1항에 있어서, 상기 폴리실리콘막의 식각공정은 폴리실리콘과 상기 산화막에 대한 금속실리사이드의 식각선택비가 높은 공정조건으로 수행함을 특징으로 하는 상기 MOS트랜지스터의 게이트 형성 방법.The method of claim 1, wherein the etching process of the polysilicon layer is performed under a process condition in which the etching selectivity of the polysilicon and the metal silicide with respect to the oxide layer is high. 제1항에 있어서, 상기 소스/드레인 영역상의 상기 게이트산화막을 산화막에 대한 폴리실리콘의 식각선택비가 높은 공정조건으로 오버식각을 수행함을 특징으로 하는 상기 MOS트랜지스터의 형성 방법.The method of claim 1, wherein the gate oxide layer on the source / drain regions is overetched under a process condition in which an etching selectivity of polysilicon is higher than that of an oxide layer. 제4항에 있어서, 상기 소스/드레인 영역상의 상기 게이트산화막을 산화막에 대한 폴리실리콘의 식각선택비가 높은 공정조건으로 오버식각을 수행함을 특징으로 하는 상기 MOS트랜지스터의 게이트 형성 방법.The method of claim 4, wherein the gate oxide layer on the source / drain regions is over-etched under a process condition in which an etching selectivity of polysilicon is higher than that of an oxide layer. 제2항에 있어서, 상기 소스/드레인 영역상의 상기 게이트산화막을 산화막에 대한 폴리실리콘의 식각선택비가 높은 공정조건으로 오버식각을 수행함을 특징으로 하는 상기 MOS트랜지스터의 게이트 형성 방법.The method of claim 2, wherein the gate oxide layer on the source / drain region is overetched under a process condition in which an etching selectivity of polysilicon is higher than that of an oxide layer. 제1항, 제4항, 제5항 또는 제6항 중 어느 하나에 있어서, 상기 금속실리사이드막 식각공정은 육불화황가스(SF6), 염소가스(Cl2), 및 헬륨(He)가스 속에 희석된 산소가스(O2)가 혼합된 식각가스를 사용함을 특징으로 하는 상기 MOS트랜지스터의 게이트 형성 방법.The metal silicide film etching process of claim 1, 4, 5, or 6, wherein the metal silicide film etching process includes sulfur hexafluoride gas (SF 6 ), chlorine gas (Cl 2 ), and helium (He) gas. The method of forming a gate of the MOS transistor, characterized in that using an etching gas mixed with oxygen gas (O 2 ) diluted in the inside. 제1항, 제4항, 제5항 또는 제6항 중 어느 하나에 있어서, 상기 금속실리사이드막 식각공정은 육불화황(SF6)가스, 산불화메탄(CHF3)가스, 불화탄소(CF2)가스, 삼불화질소(NF3)가스 및 염소가스(Cl2)가 혼합된 식각가스를 사용함을 특징으로 하는 상기 MOS트랜지스터의 게이트 형성 방법.The method of claim 1, wherein the metal silicide film etching process comprises sulfur hexafluoride (SF 6 ) gas, acid fluoride methane (CHF 3 ) gas, and carbon fluoride (CF). 2 ) A method of forming a gate of the MOS transistor, characterized in that the etching gas is a mixture of gas, nitrogen trifluoride (NF 3 ) gas and chlorine gas (Cl 2 ). 제4항 또는 제6항에 있어서, 상기 폴리실리콘막 식각공정은 육불화황가스(SF6), 염소가스(Cl2), 및 헬륨(He)가스 속에 희석된 산소가스(O2)가 혼합된 식각가스를 사용함을 특징으로 하는 상기 MOS트랜지스터의 게이트 형성 방법.The method of claim 4 or 6, wherein the polysilicon film etching process is a mixture of oxygen gas (O 2 ) diluted in sulfur hexafluoride gas (SF 6 ), chlorine gas (Cl 2 ), and helium (He) gas. The method of forming a gate of the MOS transistor, characterized in that using the etching gas. 제4항 또는 제6항에 있어서, 상기 폴리실리콘막 식각공정은 육불화황(SF6), 삼불화메탄가스(CHF3), 사불화탄소가스(CF4) 삼불화질소(NF3)가스 및 염소가스(Cl|2)가 혼합된 식각가스를 사용함을 특징으로 하는 상기 MOS트랜지스터의 게이트 형성 방법.The method of claim 4 or 6, wherein the polysilicon film etching process is sulfur hexafluoride (SF 6 ), methane trifluoride gas (CHF 3 ), carbon tetrafluoride gas (CF 4 ) nitrogen trifluoride (NF 3 ) gas and The method of forming a gate of the MOS transistor, characterized in that using the etching gas mixed with chlorine gas (Cl | 2 ). 제5항 또는 제6항에 있어서, 상기 오버식각공정은 염소가스(Cl2), 브롬화수소가스(HBr) 및 헬륨(He)가스 속에 희석된 산소가스(O2)가 혼합된 식각가스를 사용함을 특징으로 하는 상기 MOS트랜지스터의 게이트 형성 방법.The method of claim 5 or 6, wherein the over-etching process uses an etching gas in which oxygen gas (O 2 ) diluted in chlorine gas (Cl 2 ), hydrogen bromide gas (HBr) and helium (He) gas is mixed. And forming a gate of the MOS transistor. 제5항 또는 제6항에 있어서, 상기 오버식가공정은 염소가스(Cl2)와 산소가스(O2)가 혼합된 식각가스를 사용함을 특징으로 하는 상기 MOS트랜지스터의 게이트 형성 방법.The gate forming method of the MOS transistor according to claim 5 or 6, wherein the over-addition process uses an etching gas in which chlorine gas (Cl 2 ) and oxygen gas (O 2 ) are mixed. 제4항 또는 제6항에 있어서, 상기 폴리실리콘막 식각공정은 상기 폴리실리콘막에 대한 상기 금속실리사이드막의 식각선택비가 0.6:1 내지 0.8:1인 식각가스를 사용함을 특징으로 하는 상기 MOS트랜지스터의 형성 방법.The MOS transistor of claim 4, wherein the polysilicon film etching process uses an etching gas having an etching selectivity of 0.6: 1 to 0.8: 1 with respect to the polysilicon film. Forming method. 제2항 또는 7항에 있어서, 상기 폴리실리콘 식각공정은 육불화황가스(SF6),염소가스(Cl2) 및 헬륨(He)가스 속에 희석된 산소가스(O2)가 혼합된 식각가스를 사용함을 특징으로 하는 상기 MOS트랜지스터의 게이트 형성 방법.The etching method of claim 2 or 7, wherein the polysilicon etching process is an etching gas in which oxygen gas (O 2 ) diluted in sulfur hexafluoride gas (SF 6 ), chlorine gas (Cl 2 ) and helium (He) gas is mixed. The gate forming method of the MOS transistor, characterized in that using. 제2항 또는 제7항에 있어서, 상기 폴리실리콘막 식각공정은 육불화황(SF6)가스, 삼불화메탄가스(CHF3), 사불화탄소가스(CF4), 삼불화질소가스(NF3)및 염소가스(Cl2)가 혼합된 식각가스를 사용함을 특징으로 하는 상기 MOS트랜지스터의 게이트 형성 방법.The method of claim 2, wherein the polysilicon film etching process includes sulfur hexafluoride (SF 6 ) gas, methane trifluoride gas (CHF 3 ), carbon tetrafluoride gas (CF 4 ), and nitrogen trifluoride gas (NF 3). And an etching gas containing chlorine gas (Cl 2 ) mixed therein. 제2항에 있어서, 상기 폴리실리콘막 식각공정은 상기 폴리실리콘막에 대한 상기 금속실리사이드막의 식각선택비가 0.6:1 내지 0.8:1인 식각가스를 사용함을 특징으로 하는 상기 MOS트랜지스터의 형성 방법.The method of claim 2, wherein the polysilicon film etching process uses an etching gas having an etching selectivity ratio of the metal silicide film to the polysilicon film in a range of 0.6: 1 to 0.8: 1. 제3항에 있어서, 상기 오버식각공정은 염소가스(Cl2), 브롬화수소가스(HBr) 및 헬륨(He) 속에 희석된 산소가스(O2)가 혼합된 식각가스를 사용함을 특징으로 하는 상기 MOS트랜지스터의 게이트 형성 방법.The method of claim 3, wherein the over-etching process comprises using an etching gas in which chlorine gas (Cl 2 ), hydrogen bromide gas (HBr), and oxygen gas (O 2 ) diluted in helium (He) are mixed. A method of forming a gate of a MOS transistor. 제3항에 있어서, 상기 오버식각공정은 염소가스(Cl2)와 산소가스(O2)가 혼합된 식각가스를 사용함을 특징으로 하는 상기 MOS트랜지스터의 게이트 형성 방법.The method of claim 3, wherein the over-etching process uses an etching gas in which chlorine gas (Cl 2 ) and oxygen gas (O 2 ) are mixed. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960020676A 1996-06-10 1996-06-10 Method for forming mosfet KR100237824B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100632644B1 (en) * 1999-12-27 2006-10-11 주식회사 하이닉스반도체 Method of etching a polysilicon layer in a semiconductor device
KR100642903B1 (en) * 1999-10-20 2006-11-03 매그나칩 반도체 유한회사 Forming method of gate electrode in semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100642903B1 (en) * 1999-10-20 2006-11-03 매그나칩 반도체 유한회사 Forming method of gate electrode in semiconductor device
KR100632644B1 (en) * 1999-12-27 2006-10-11 주식회사 하이닉스반도체 Method of etching a polysilicon layer in a semiconductor device

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