KR100194571B1 - 반도체 메모리 및 그 기입 방법 - Google Patents

반도체 메모리 및 그 기입 방법 Download PDF

Info

Publication number
KR100194571B1
KR100194571B1 KR1019960033322A KR19960033322A KR100194571B1 KR 100194571 B1 KR100194571 B1 KR 100194571B1 KR 1019960033322 A KR1019960033322 A KR 1019960033322A KR 19960033322 A KR19960033322 A KR 19960033322A KR 100194571 B1 KR100194571 B1 KR 100194571B1
Authority
KR
South Korea
Prior art keywords
data
input
address
address signal
internal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019960033322A
Other languages
English (en)
Korean (ko)
Other versions
KR970012754A (ko
Inventor
마모루 후지따
Original Assignee
가네꼬 히사시
닛본 덴기 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가네꼬 히사시, 닛본 덴기 가부시끼가이샤 filed Critical 가네꼬 히사시
Publication of KR970012754A publication Critical patent/KR970012754A/ko
Application granted granted Critical
Publication of KR100194571B1 publication Critical patent/KR100194571B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
KR1019960033322A 1995-08-11 1996-08-10 반도체 메모리 및 그 기입 방법 Expired - Fee Related KR100194571B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP95-206094 1995-08-11
JP7206094A JP2817672B2 (ja) 1995-08-11 1995-08-11 半導体メモリ

Publications (2)

Publication Number Publication Date
KR970012754A KR970012754A (ko) 1997-03-29
KR100194571B1 true KR100194571B1 (ko) 1999-06-15

Family

ID=16517712

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960033322A Expired - Fee Related KR100194571B1 (ko) 1995-08-11 1996-08-10 반도체 메모리 및 그 기입 방법

Country Status (7)

Country Link
US (1) US5768212A (enExample)
EP (1) EP0762427B1 (enExample)
JP (1) JP2817672B2 (enExample)
KR (1) KR100194571B1 (enExample)
CN (1) CN1106019C (enExample)
DE (1) DE69616710T2 (enExample)
TW (1) TW318904B (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5978281A (en) * 1999-01-04 1999-11-02 International Business Machines Corporation Method and apparatus for preventing postamble corruption within a memory system
US6081479A (en) * 1999-06-15 2000-06-27 Infineon Technologies North America Corp. Hierarchical prefetch for semiconductor memories
US6775759B2 (en) 2001-12-07 2004-08-10 Micron Technology, Inc. Sequential nibble burst ordering for data
US20040194500A1 (en) * 2003-04-03 2004-10-07 Broadway Entertainment, Inc. Article of jewelry
US7652922B2 (en) * 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
KR101293365B1 (ko) 2005-09-30 2013-08-05 모사이드 테크놀로지스 인코퍼레이티드 출력 제어 메모리
US20070076502A1 (en) 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
US11948629B2 (en) 2005-09-30 2024-04-02 Mosaid Technologies Incorporated Non-volatile memory device with concurrent bank operations
US7688652B2 (en) * 2007-07-18 2010-03-30 Mosaid Technologies Incorporated Storage of data in memory via packet strobing
US8825967B2 (en) 2011-12-08 2014-09-02 Conversant Intellectual Property Management Inc. Independent write and read control in serially-connected devices
US9384851B2 (en) * 2014-02-06 2016-07-05 SK Hynix Inc. Semiconductor devices and semiconductor systems including the same
JP6468763B2 (ja) * 2014-09-08 2019-02-13 ラピスセミコンダクタ株式会社 データ処理装置
CN109745693A (zh) * 2018-12-08 2019-05-14 郑州工业应用技术学院 一种跳高高度自动显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4775990A (en) * 1984-01-18 1988-10-04 Sharp Kabushiki Kaisha Serial-to-parallel converter
JPS6139297A (ja) * 1984-07-30 1986-02-25 Nec Corp 半導体集積回路
JP2696026B2 (ja) * 1991-11-21 1998-01-14 株式会社東芝 半導体記憶装置
US5610864A (en) * 1994-12-23 1997-03-11 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing

Also Published As

Publication number Publication date
EP0762427B1 (en) 2001-11-07
JP2817672B2 (ja) 1998-10-30
CN1106019C (zh) 2003-04-16
EP0762427A1 (en) 1997-03-12
JPH0955089A (ja) 1997-02-25
US5768212A (en) 1998-06-16
CN1147135A (zh) 1997-04-09
TW318904B (enExample) 1997-11-01
DE69616710T2 (de) 2002-08-22
KR970012754A (ko) 1997-03-29
DE69616710D1 (de) 2001-12-13

Similar Documents

Publication Publication Date Title
US5835443A (en) High speed semiconductor memory with burst mode
US7178001B2 (en) Semiconductor memory asynchronous pipeline
US6539454B2 (en) Semiconductor memory asynchronous pipeline
KR100194571B1 (ko) 반도체 메모리 및 그 기입 방법
US11467965B2 (en) Processing-in-memory (PIM) device
JP3183159B2 (ja) 同期型ｄｒａｍ
KR20070108293A (ko) 반도체기억장치
US6166970A (en) Priority determining apparatus using the least significant bit and CAS latency signal in DDR SDRAM device
JP2817685B2 (ja) 半導体メモリ
US6178139B1 (en) Semiconductor memory device comprised of a double data rate-synchronous dynamic random access memory
US6834015B2 (en) Semiconductor memory device for reducing data accessing time
US7143257B2 (en) Method and apparatus of a smart decoding scheme for fast synchronous read in a memory system
KR20000034386A (ko) 에스 디 램 콘트롤러의 메모리 액세스 방법

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

FPAY Annual fee payment

Payment date: 20040120

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20050210

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20050210

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000