KR100190385B1 - 2스테이지 래치회로를 이용한 페이지 모드 마스크롬 및 그 제어방법 - Google Patents

2스테이지 래치회로를 이용한 페이지 모드 마스크롬 및 그 제어방법 Download PDF

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Publication number
KR100190385B1
KR100190385B1 KR1019950014967A KR19950014967A KR100190385B1 KR 100190385 B1 KR100190385 B1 KR 100190385B1 KR 1019950014967 A KR1019950014967 A KR 1019950014967A KR 19950014967 A KR19950014967 A KR 19950014967A KR 100190385 B1 KR100190385 B1 KR 100190385B1
Authority
KR
South Korea
Prior art keywords
signal
latch
address
output
response
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019950014967A
Other languages
English (en)
Korean (ko)
Other versions
KR970003259A (ko
Inventor
윤찬수
Original Assignee
김영환
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업주식회사 filed Critical 김영환
Priority to KR1019950014967A priority Critical patent/KR100190385B1/ko
Priority to GB9611798A priority patent/GB2301917B/en
Priority to TW085106862A priority patent/TW300998B/zh
Priority to US08/659,837 priority patent/US5691943A/en
Priority to JP14612996A priority patent/JP2887108B2/ja
Publication of KR970003259A publication Critical patent/KR970003259A/ko
Application granted granted Critical
Publication of KR100190385B1 publication Critical patent/KR100190385B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
KR1019950014967A 1995-06-07 1995-06-07 2스테이지 래치회로를 이용한 페이지 모드 마스크롬 및 그 제어방법 Expired - Fee Related KR100190385B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019950014967A KR100190385B1 (ko) 1995-06-07 1995-06-07 2스테이지 래치회로를 이용한 페이지 모드 마스크롬 및 그 제어방법
GB9611798A GB2301917B (en) 1995-06-07 1996-06-06 A memory device and method of operation
TW085106862A TW300998B (enExample) 1995-06-07 1996-06-07
US08/659,837 US5691943A (en) 1995-06-07 1996-06-07 Page mode mask ROM using a two-stage latch circuit and a method for controlling the same
JP14612996A JP2887108B2 (ja) 1995-06-07 1996-06-07 ２ステージラッチ回路を利用したページモードマスクロム及びその制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950014967A KR100190385B1 (ko) 1995-06-07 1995-06-07 2스테이지 래치회로를 이용한 페이지 모드 마스크롬 및 그 제어방법

Publications (2)

Publication Number Publication Date
KR970003259A KR970003259A (ko) 1997-01-28
KR100190385B1 true KR100190385B1 (ko) 1999-06-01

Family

ID=19416613

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950014967A Expired - Fee Related KR100190385B1 (ko) 1995-06-07 1995-06-07 2스테이지 래치회로를 이용한 페이지 모드 마스크롬 및 그 제어방법

Country Status (5)

Country Link
US (1) US5691943A (enExample)
JP (1) JP2887108B2 (enExample)
KR (1) KR100190385B1 (enExample)
GB (1) GB2301917B (enExample)
TW (1) TW300998B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5644538A (en) * 1996-03-01 1997-07-01 Micron Technology, Inc. Circuit and method for controllng the duration of pulses in a control signal from an electronic system
KR100247064B1 (ko) * 1997-04-10 2000-03-15 윤종용 콤팩트디스크-롬 드라이브의 디코딩장치에서 에러정정을 위한 메모리 리드회로
EP0913829A1 (en) * 1997-10-31 1999-05-06 STMicroelectronics S.r.l. Memory circuit with improved address signal generator
US6065066A (en) * 1998-06-02 2000-05-16 Adaptec, Inc. System for data stream packer and unpacker integrated circuit which align data stored in a two level latch
US6873707B1 (en) * 2000-09-28 2005-03-29 Cisco Technology, Inc. Hardware-based encryption/decryption employing cycle stealing
US7006634B1 (en) * 2000-09-28 2006-02-28 Cisco Technology, Inc. Hardware-based encryption/decryption employing dual ported key storage
KR100431331B1 (ko) * 2002-08-21 2004-05-12 삼성전자주식회사 반도체 메모리장치의 입출력 센스 앰프 구동방법 및 그구동제어회로
KR100498186B1 (ko) * 2003-03-11 2005-07-01 주식회사 엑셀반도체 데이터 리드의 오동작을 방지하기 위한페이지액티브회로를 구비한 의사 에스램
CN103177767B (zh) * 2013-04-08 2015-09-23 中国兵器工业集团第二一四研究所苏州研发中心 一种用于一次编程存储器的简化存储方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0748307B2 (ja) * 1989-06-08 1995-05-24 株式会社東芝 半導体メモリ装置
EP0505653A1 (en) * 1991-03-29 1992-09-30 International Business Machines Corporation Combined sense amplifier and latching circuit for high speed ROMs
JP2696026B2 (ja) * 1991-11-21 1998-01-14 株式会社東芝 半導体記憶装置
KR950004854B1 (ko) * 1992-10-08 1995-05-15 삼성전자 주식회사 반도체 메모리 장치
WO2016147730A1 (ja) 2015-03-19 2016-09-22 高崎 将紘 決済処理装置、方法、及びコンピュータプログラム

Also Published As

Publication number Publication date
JP2887108B2 (ja) 1999-04-26
TW300998B (enExample) 1997-03-21
GB9611798D0 (en) 1996-08-07
KR970003259A (ko) 1997-01-28
GB2301917B (en) 1999-09-01
JPH09129824A (ja) 1997-05-16
US5691943A (en) 1997-11-25
GB2301917A (en) 1996-12-18

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