KR0148617B1 - 다층배선을 갖는 고집적회로의 포토레지스트 체크 패턴 - Google Patents
다층배선을 갖는 고집적회로의 포토레지스트 체크 패턴 Download PDFInfo
- Publication number
- KR0148617B1 KR0148617B1 KR1019940029962A KR19940029962A KR0148617B1 KR 0148617 B1 KR0148617 B1 KR 0148617B1 KR 1019940029962 A KR1019940029962 A KR 1019940029962A KR 19940029962 A KR19940029962 A KR 19940029962A KR 0148617 B1 KR0148617 B1 KR 0148617B1
- Authority
- KR
- South Korea
- Prior art keywords
- photoresist
- pattern
- check pattern
- check
- photoresist check
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229920002120 photoresistant polymer Polymers 0.000 title claims abstract description 75
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000012360 testing method Methods 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 238000013461 design Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 21
- 238000009792 diffusion process Methods 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 238000011161 development Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 31
- 230000008569 process Effects 0.000 description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 229920005591 polysilicon Polymers 0.000 description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 12
- 230000007547 defect Effects 0.000 description 9
- 238000000059 patterning Methods 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 6
- 238000001459 lithography Methods 0.000 description 5
- 230000002950 deficient Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Automation & Control Theory (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (6)
- 다수의 불순물 확산층을 내부에 포함하는 반도체 기판과, 상기 반도체 기판의 표면에 절연막을 사이에 개재하여 층상으로 형성되고 상기 반도체기판의 표면으로부터 복수의 높이를 갖는 다수의 전도성 배선층을 갖는 반도체 집적회로의 포토레지스트 체크 패턴 구조에 있어서, 상기 반도체 장치를 제조하기 위한 각 공정 단계 중에 형성되는 표면 스텝에 대응하여 복수의 스텝영역을 갖는 패턴 테스트 영역 및, 상기 패턴 테스트 영역에서 하나이상의 상기 표면 스텝을 가로지르고 연속하여 연장되며 편평한 레지스트 표면을 갖는 포토레지스트 체크 패턴으로 이루어지며, 상기 표면 스텝은 평면형상에서 한 쪽이 오목하게 형성되는 것을 특징으로 하는 포토레지스트 체크 패턴 구조.
- 제1항에 있어서, 상기 포토레지스트 체크 패턴 아래의 하지층의 평면형상은 한쪽이 오목한 형상으로 형성되는 것을 특징으로 하는 포토레지스트 체크 패턴 구조.
- 제1항에 있어서, 다수개의 포토레지스트 체크 패턴이 상기 표면스텝의 한쪽이 오목한 영역을 가로질러 신장되는 것을 특징으로 하는 포토레지스트 체크 패턴 구조.
- 제3항에 있어서, 상기 포토레지스트 체크 패턴은 반도체 기판 상에서 반도체 회로 요소를 위한 디자인 룰에 의한 치수보다 더욱 엄격한 치수에서 형성되는 패턴을 포함하는 것을 특징으로 하는 포토레지스트 체크 패턴 구조.
- 제1항에 있어서, 상기 포토레지스트 체크 패턴은 노광 표면의 4 코너 각각에 배설되는 것을 특징으로 하는 포토레지스트 패턴 체크 구조.
- 제1항에 있어서, 상기 포토레지스트 체크 패턴 아래의 하지층인 게이트 전극의 평면 형상은 한 쪽이 오목한 형상으로 형성되는 것을 특징으로 하는 포토레지스트 체크 패턴 구조.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5308579A JP2658841B2 (ja) | 1993-11-16 | 1993-11-16 | フォトレジストチェックパターン |
JP93-308579 | 1993-11-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950015552A KR950015552A (ko) | 1995-06-17 |
KR0148617B1 true KR0148617B1 (ko) | 1998-12-01 |
Family
ID=17982733
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940029962A Expired - Lifetime KR0148617B1 (ko) | 1993-11-16 | 1994-11-15 | 다층배선을 갖는 고집적회로의 포토레지스트 체크 패턴 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5981114A (ko) |
JP (1) | JP2658841B2 (ko) |
KR (1) | KR0148617B1 (ko) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040175525A1 (en) * | 2002-02-28 | 2004-09-09 | Scimed Life Systems, Inc. | Catheter incorporating an improved polymer shaft |
JP4511220B2 (ja) * | 2004-03-10 | 2010-07-28 | ルネサスエレクトロニクス株式会社 | 断面形状検査用パターン及び半導体装置 |
JP6278978B2 (ja) * | 2013-01-23 | 2018-02-14 | シーエスエムシー テクノロジーズ エフエイビー2 カンパニー リミテッド | スクライビングスロットのストリップ幅を検査するための構造及び方法 |
CN112614915B (zh) * | 2020-12-29 | 2022-03-08 | 江苏宜兴德融科技有限公司 | 太阳能电池测试方法和太阳能电池测试中间结构 |
JP7291766B2 (ja) * | 2021-11-22 | 2023-06-15 | Towa株式会社 | 検査システム、制御方法、電子部品の製造方法及び切断装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56137632A (en) * | 1980-03-28 | 1981-10-27 | Nec Corp | Pattern forming |
US4679942A (en) * | 1984-02-24 | 1987-07-14 | Nippon Kogaku K. K. | Method of aligning a semiconductor substrate and a photomask |
JPH0652701B2 (ja) * | 1985-10-01 | 1994-07-06 | 沖電気工業株式会社 | 回路パタ−ニング判定方法 |
US4806457A (en) * | 1986-04-10 | 1989-02-21 | Nec Corporation | Method of manufacturing integrated circuit semiconductor device |
US4704027A (en) * | 1986-06-19 | 1987-11-03 | Compact Spindle Bearing Corporation | Dark field alignment and alignment mark systems |
-
1993
- 1993-11-16 JP JP5308579A patent/JP2658841B2/ja not_active Expired - Fee Related
-
1994
- 1994-11-15 KR KR1019940029962A patent/KR0148617B1/ko not_active Expired - Lifetime
-
1996
- 1996-12-30 US US08/773,615 patent/US5981114A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2658841B2 (ja) | 1997-09-30 |
JPH07142368A (ja) | 1995-06-02 |
KR950015552A (ko) | 1995-06-17 |
US5981114A (en) | 1999-11-09 |
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