KR0137543B1 - Mosfet fabrication method - Google Patents
Mosfet fabrication methodInfo
- Publication number
- KR0137543B1 KR0137543B1 KR1019940037518A KR19940037518A KR0137543B1 KR 0137543 B1 KR0137543 B1 KR 0137543B1 KR 1019940037518 A KR1019940037518 A KR 1019940037518A KR 19940037518 A KR19940037518 A KR 19940037518A KR 0137543 B1 KR0137543 B1 KR 0137543B1
- Authority
- KR
- South Korea
- Prior art keywords
- gate electrode
- forming
- insulating film
- spacer insulating
- spacer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title description 3
- 125000006850 spacer group Chemical group 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000001039 wet etching Methods 0.000 claims abstract description 4
- 150000004767 nitrides Chemical class 0.000 claims description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Weting (AREA)
Abstract
본 발명은 기존의 농광기 및 감광물질을 사용하면서도 0.2㎛ 이하의 초미세 패턴을 형성하기 위한 반도체 소자의 게이트전극 형성방법에 관한 것으로, 예정된 게이트전극 형성부위에 게이트전극층을 형성하는 단계; 상기 게이트전극층 상부에 제1절연막 패턴, 스페이서 절연막을 형성하는 단계; 상기 구조 전체 상부에 제2절연막을 형성하는 단계; CMP방법으로 평탄화한 다음, 상기 스페이서 절연막을 선택적으로 제거하는 단계; 상기 제1 및 제2절연막을 습식식각법으로 제거하는 단계; 상기 잔류하는 스페이서 절연막을 식각마스크로 게이트전극층을 과도식각한 다음, 상기 스페이서 절연막을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method of forming a gate electrode of a semiconductor device for forming an ultrafine pattern of 0.2 μm or less while using a conventional concentrator and a photosensitive material, comprising: forming a gate electrode layer on a predetermined gate electrode forming portion; Forming a first insulating layer pattern and a spacer insulating layer on the gate electrode layer; Forming a second insulating film over the entire structure; Planarizing by a CMP method, and then selectively removing the spacer insulating film; Removing the first and second insulating layers by a wet etching method; And over-etching the gate electrode layer with the remaining spacer insulating film as an etch mask, and then removing the spacer insulating film.
Description
제1a도 내지 제1f도는 본 발명의 일실시예에 따른 게이트전극 형성 공정 단며도.1A through 1F are schematic diagrams of a gate electrode forming process according to an exemplary embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
2:게이트산화막3:도핑된 폴리실리콘막2: gate oxide film 3: doped polysilicon film
4,.6:질화막5,5':산화막스페이서4, .6: nitride film 5, 5 ': oxide spacer
본 발명은 반도체 소자의 게이트전극 형성방법에 관한 것으로, 특히 고집적 소자에 적합한 초미세 게이트 전극을 형성하기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode of a semiconductor device, and more particularly to a method for forming an ultrafine gate electrode suitable for a highly integrated device.
반도체 소자의 고집적화 추세에 따라 게이트전극의 임계치수도 0.2㎛ 이하를 필요로 하게 되었으나, 이를 구현하기 위해서는 새로운 노광기나 감광물질의 개발이 필수적으로 선행되어야만 한다. 결국, 막대한 개발비가 소모될 뿐만 아니라 개발기간이 길어질수록 반도체 소자의 제품화에도 지장을 초래하게 된다.According to the trend toward higher integration of semiconductor devices, the critical dimension of the gate electrode needs to be 0.2 μm or less, but in order to realize this, the development of a new exposure machine or a photosensitive material must be preceded. As a result, not only a huge development cost is consumed, but also a longer development period causes a problem in the commercialization of semiconductor devices.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 기존의 노광기 및 감광물질을 사용하면서도 0.2㎛ 이하의 초미세 패턴을 형성하기 위한 반도체 소자의 게이트전극 형성방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method of forming a gate electrode of a semiconductor device for forming an ultra-fine pattern of 0.2 ㎛ or less while using a conventional exposure machine and a photosensitive material.
상기 목적을 달성하기 위하여 본 발명은 반도체소자의 게이트전극 형성방법에 있어서, 예정된 게이트전극 형성부위에 게이트전극층을 형성하는 단계; 상기 게이트전극층 상부에 제1절연막 패턴, 스페이서 절연막을 형성하는 단계; 상기 구조 전체 상부에 제2절연막을 형성하는 단계; CMP방법으로 평탄화한 다음, 상기 스페이서 절연막을 선택적으로 제거하는 단계; 상기 제1 및 제2절연막을 습식식각법으로 제거하는 단계; 상기 잔류하는 스페이서 절연막을 식각마스크로 게이트전극층을 과도식각한 다음, 상기 스페이서 절연막을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a gate electrode of a semiconductor device, the method comprising: forming a gate electrode layer on a predetermined gate electrode forming portion; Forming a first insulating layer pattern and a spacer insulating layer on the gate electrode layer; Forming a second insulating film over the entire structure; Planarizing by a CMP method, and then selectively removing the spacer insulating film; Removing the first and second insulating layers by a wet etching method; And over-etching the gate electrode layer with the remaining spacer insulating film as an etch mask, and then removing the spacer insulating film.
이하, 첨부된 도면 제1a도 내지 제1f도를 참조하여 본 발명의 일실시예를 상술한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1F.
먼저, 제1a도에 도시된 바와 같이 실리콘기판(1)상에 게이트산화막(2), 도핑된 폴리실리콘(3), 질화막을 증착한 다음, 상기 질화막을 사진식각하여 질화막패턴(4)을 형성한다.First, as shown in FIG. 1A, a gate oxide film 2, a doped polysilicon 3, and a nitride film are deposited on the silicon substrate 1, and then the nitride film is photo-etched to form a nitride film pattern 4. do.
이어서, 상기 구조 전체 상부에 CVD 산화막을 증착한 다음, 상기 폴리실리콘막(3)이 노출되도록 비등방성 식각하여 제1b도에서와 같이 산화막스페이서(5)를 형성한다.Subsequently, a CVD oxide film is deposited over the entire structure, and then anisotropically etched to expose the polysilicon film 3 to form an oxide film spacer 5 as shown in FIG.
계속해서, 제1c도에서 상기 구조 전체 상부에 질화막(6)을 증착한다.Subsequently, in FIG. 1C, a nitride film 6 is deposited over the entire structure.
다음으로, 상기 질화막(6)의 하단부를 연마정지점으로 하여 CMP(Chemical Mechanical Polishing)방법으로 평탄화한 다음, 불필요한 부분의 상기 산화막스페이서(5)를 사진식각법으로 제거한다.Next, the lower end portion of the nitride film 6 is planarized by a chemical mechanical polishing (CMP) method, and then the oxide film spacers 5 of unnecessary portions are removed by photolithography.
이어서, 인산(H3PO4) 용액을 사용하여 상기 질화막패턴(4, 6)을 제거함으로써 제1e에서와 같이 산화막스페이서(5')만 잔류시킨다.Subsequently, the nitride film patterns 4 and 6 are removed using a solution of phosphoric acid (H 3 PO 4 ) to leave only the oxide film spacer 5 'as in the first e.
끝으로, 제1f도에 도시된 바와 같이 상기 잔류하는 산화막 스페이서(5')를 식각마스크로 하여 폴리실리콘막(3)을 과도식각한 다음, 산화막 스페이서(5')를 건식식각으로 제거한다.Finally, as shown in FIG. 1f, the polysilicon film 3 is excessively etched using the remaining oxide film spacer 5 'as an etch mask, and then the oxide film spacer 5' is removed by dry etching.
상기와 같이 이루어지는 본 발명은 간단한 공정으로 초미세 게이트전극을 형성함으로써 제조비용 절감 및 제조수율 향상의 효과를 얻을 수 있다.The present invention made as described above can achieve the effect of reducing the manufacturing cost and manufacturing yield by forming the ultra-fine gate electrode in a simple process.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940037518A KR0137543B1 (en) | 1994-12-27 | 1994-12-27 | Mosfet fabrication method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940037518A KR0137543B1 (en) | 1994-12-27 | 1994-12-27 | Mosfet fabrication method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960026475A KR960026475A (en) | 1996-07-22 |
| KR0137543B1 true KR0137543B1 (en) | 1998-06-01 |
Family
ID=19404009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940037518A KR0137543B1 (en) | 1994-12-27 | 1994-12-27 | Mosfet fabrication method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0137543B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100607732B1 (en) * | 2002-10-09 | 2006-08-01 | 동부일렉트로닉스 주식회사 | Method for forming gate pole of semiconductor |
| US7732341B2 (en) | 2006-10-17 | 2010-06-08 | Samsung Electronics Co., Ltd. | Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same |
-
1994
- 1994-12-27 KR KR1019940037518A patent/KR0137543B1/en not_active IP Right Cessation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100607732B1 (en) * | 2002-10-09 | 2006-08-01 | 동부일렉트로닉스 주식회사 | Method for forming gate pole of semiconductor |
| US7732341B2 (en) | 2006-10-17 | 2010-06-08 | Samsung Electronics Co., Ltd. | Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same |
| US8003543B2 (en) | 2006-10-17 | 2011-08-23 | Samsung Electronics Co., Ltd. | Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same |
| US8278221B2 (en) | 2006-10-17 | 2012-10-02 | Samsung Electronics Co., Ltd. | Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960026475A (en) | 1996-07-22 |
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