KR930009130B1 - Method of fabricating memory cell - Google Patents

Method of fabricating memory cell Download PDF

Info

Publication number
KR930009130B1
KR930009130B1 KR1019910005968A KR910005968A KR930009130B1 KR 930009130 B1 KR930009130 B1 KR 930009130B1 KR 1019910005968 A KR1019910005968 A KR 1019910005968A KR 910005968 A KR910005968 A KR 910005968A KR 930009130 B1 KR930009130 B1 KR 930009130B1
Authority
KR
South Korea
Prior art keywords
polysilicon
layer
etching
anisotropically
oxide layer
Prior art date
Application number
KR1019910005968A
Other languages
Korean (ko)
Other versions
KR920020711A (en
Inventor
전영권
Original Assignee
금성일렉트론 주식회사
문정환
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사, 문정환 filed Critical 금성일렉트론 주식회사
Priority to KR1019910005968A priority Critical patent/KR930009130B1/en
Publication of KR920020711A publication Critical patent/KR920020711A/en
Application granted granted Critical
Publication of KR930009130B1 publication Critical patent/KR930009130B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The method forms a capacitor node by magnetic matching to enhance overlay accuracy and increase storage capacity for the cell, and the method includes the steps of: forming a polysilicon plug (4), a bit line (5), an oxide layer (6) and a nitride layer (7) on a substrate (1) having a field oxide layer (2) and a gate (3) to pattern; depositing a doped silicon on the whole surface of the product of the foregoing step to form an oxide layer (9) and a nitride layer (10) and then pattern them to form a doped polysilicon layer (11); anisotropically dry-etching the polysilicon (11) to form side walls; removing the nitride layer (10) by wet etching to anisotropically dry etch the oxide layer (9) and then form a doped polysilicon layer (12); dry-etching the polysilicon (12) primarily and anisotropically and dry etching the oxide layer (9) anisotropically and executing the secondary anisotropic dry etching to the poly silicon layer (12) to connect the upper node to the lower node and remove the oxide layer (9) by wet etching; and forming a capacitor dielectric layer (13) and a polysilicon plate layer (14) to execute patterning.

Description

메모리 셀 제조방법Memory Cell Manufacturing Method

제 1 도는 종래 메모리 셀의 공정단면도.1 is a process cross-sectional view of a conventional memory cell.

제 2 도는 본 발명 메모리 셀의 공정단면도.2 is a process cross-sectional view of a memory cell of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 필드산화막1 substrate 2 field oxide film

3 : 게이트 4 : 폴리실리콘 플러그3: gate 4: polysilicon plug

5 : 비트라인 6, 9 : 산화막5: bit line 6, 9: oxide film

7, 10 : 질화막 8, 11, 12 : 폴리실리콘7, 10: nitride film 8, 11, 12: polysilicon

13 : 유전막 14 : 플레이트 폴리실리콘13: dielectric film 14: plate polysilicon

본 발명은 메로리 셀 제조방법에 관한 것으로, 특히 자기정합에 의해 커패시터 노드를 형성하여 오버레이어큐러시(Overlay Accuracy)를 향상시키고 축적용량을 증가시킬 수 있도록 한 것이다.The present invention relates to a method for manufacturing a memory cell, and in particular, to form a capacitor node by self-matching to improve the overlay accuracy and increase the storage capacity.

종래의 메모리 셀 제조방법은 제 1 도에 도시된 바와같이 기판(21)위에 게이트(22)와 산화막(23)을 형성하고 매몰 콘택을 위한 식각을 한후 마스크용 질화막(24)을 형성하고 패터닝한다.In the conventional method of manufacturing a memory cell, as shown in FIG. 1, a gate 22 and an oxide film 23 are formed on a substrate 21, and etching is performed for a buried contact. Then, a mask nitride film 24 is formed and patterned. .

그리고 (b)와 같이 폴리실리콘(25)을 형성하고 패터닝하여 폴리 실리콘 패드를 형성한 후(c)와 같이 산화막(26)을 화학증착법으로 형성하고 패터닝한 후 노드용 폴리실리콘(27)을 화학증착법으로 퇴적한다.Then, as shown in (b), polysilicon 25 is formed and patterned to form polysilicon pads, and as shown in (c), the oxide layer 26 is formed by chemical vapor deposition and patterned, and then the polysilicon 27 for nodes is chemically formed. It deposits by a vapor deposition method.

다음에 (d)와 같이 노드용 폴리실리콘(27)을 증착두께만큼 이방성 건식식각한 후 스토리지 노드를 형성한다.Next, as shown in (d), the node polysilicon 27 is anisotropically dry-etched by the deposition thickness, and then a storage node is formed.

또한, (e) (f)와 같이 유전막과 플레이트 폴리실리콘(28)을 형성하고 패터닝한 후 절연막(29)을 증착하고 콘택 식각한 다음 텅스텐 플러그를 형성하여 비트라인(30)을 만든다.In addition, as shown in (e) and (f), after forming and patterning the dielectric film and the plate polysilicon 28, the insulating film 29 is deposited, contact etched, and a tungsten plug is formed to form the bit line 30.

그러나 상기와 같은 종래 메모리 셀 제조 방법에 있어서는 폴리실리콘 패드(25)와 노드용 폴리실리콘(27)을 따라 식각함으로 오정합(Misalign)에 의하여 오버레이 어큐러시가 악화되기 쉬우며 포토리지스트 공정을 거쳐야함으로 공정이 복작해지는 결점이 있다.However, in the conventional method of manufacturing a memory cell as described above, by overlaying the polysilicon pad 25 and the polysilicon 27 for the node by etching, it is easy to deteriorate the overlay acuity by misalignment and undergo a photoresist process. As a result, the process is complicated.

본 발명은 이와같은 종래의 결점을 해결하기 위한 것으로 폴리실리콘 패드와 스토리지 노드 폴리실리콘을 자기정합적으로 패터닝하여 오버레이 어큐러시를 향상시킬 수 있는 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a manufacturing method that can improve overlay security by patterning polysilicon pads and storage node polysilicon in a self-aligned manner.

이하에서 이와같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면 제 2 도에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings.

먼저(a)와 같이 기판(1)에 필드산화막(2), 게이트(3)를 형성하고 폴리실리콘 플러그(4)와 비트라인(5) 그리고 산화막(6)과 질화막(7)을 형성한다.First, as shown in (a), the field oxide film 2 and the gate 3 are formed on the substrate 1, and the polysilicon plug 4, the bit line 5, the oxide film 6, and the nitride film 7 are formed.

그리고 (b)와 같이 상기 전표면에 도우핑된 노드폴리실리콘(8)을 형성하고 (c)와 같이 노드폴리실리콘(8)위에 산화막(9)과 질화막(10)을 형성하며 이 질화막(10)을 패터닝한 후 다시 도우핑된 폴리 실리콘(11)을 형성한다.And forming a doped polysilicon 8 doped on the entire surface as shown in (b), and forming an oxide film 9 and a nitride film 10 on the nodal polysilicon 8 as shown in (c). ) And then doped polysilicon (11) again.

다음에 (d)와 같이 상기 폴리실리콘(11)을 이방성 건식식각하여 측벽을 형성한 후 습식식각으로 질화막(10)을 제거한다.Next, as shown in (d), the polysilicon 11 is anisotropically dry etched to form sidewalls, and then the nitride film 10 is removed by wet etching.

이어서 (e)와 같이 폴리실리콘을 마스크로 사용하여 산화막(9)을 이방성 건식식각한 후 (f)와 같이 전표면에 도핑된 폴리실리콘(12)을 형성하고 (G)와 같이 폴리실리콘(12)을 1차 이방성 건식식각하여 산화막(9)이 드러나도록 한다.Subsequently, anisotropic dry etching of the oxide film 9 is performed using polysilicon as a mask as shown in (e), and then doped polysilicon 12 is formed on the entire surface as shown in (f), and polysilicon 12 as shown in (G). ) Is anisotropically dry etched so that the oxide film 9 is exposed.

다음에 폴리실리콘(12)을 마스크로 이용하여 산화막(9)을 이방성 건식식각하고 드러난 폴리실리콘(8)을 이방성 건식식각 한 후 산화막(9)을 습식식각으로 한다.Next, the oxide film 9 is anisotropically dry-etched using the polysilicon 12 as a mask, and the exposed polysilicon 8 is anisotropically dry-etched, and then the oxide film 9 is wet-etched.

또한, (h)와 같이 커패시터 유전막(13)과 플레이트 폴리실리콘(14)을 형성하고 패터닝한다.In addition, as shown in (h), the capacitor dielectric film 13 and the plate polysilicon 14 are formed and patterned.

이상에서 설명한 바와같이 본 발명은 패트폴리실리콘(8)과 패드와 스토리지 노드 폴리실리콘(12)을 자기정합적으로 패터닝함에 따라 오버레이 어큐러시를 향상시킬 수 있으며 기존의 메모리 셀 공정보다 공정이 단순화되며 커패시터 축적용량을 더욱 증대시킬 수 있는 효과가 있다.As described above, the present invention can improve the overlay acuity by self-patterning the patterned polysilicon 8, the pad and the storage node polysilicon 12, and the process is simplified compared to the conventional memory cell process. There is an effect that can further increase the capacitor storage capacity.

Claims (1)

반도체 집적회로의 메모리 셀 제조방법에 있어서, 필드산화막(2)과 게이트(3)가 형성된 통상의 기판(1)위에 폴리실리콘 플러그(4), 비트라인(5), 산화막(6) 및 질화막(7)을 형성하여 패터닝하는 공정과, 상기 전 표면위에 도우핑된 폴리실리콘(8)을 퇴적하고 그위에 산화막(9), 질화막(10)을 형성한 후 패터닝한 상태에서 도우핑된 폴리실리콘(11)을 형성하는 공정과, 상기 폴리실리콘(11)을 이방성 건식식각하여 측벽을 형성하는 공정과, 상기 질화막(10)을 습식식각으로 제거하고 산화막(9)을 이방성 건식식각한 후 도우핑된 폴리실리콘(12)을 형성하는 공정과, 상기 폴리실리콘(12)을 1차 이방성 건식식각하고 산화막(9)을 이방성 건식식각한 후 폴리실리콘(12)을 2 차 이방성 건식식각하여 상부노드와 하부노드가 연결되게 하고 산화막(9)을 습식식각으로 제거하는 공정과, 커패시터 유전막(13)과 플레이트 폴리실리콘(14)을 형성하고 패터닝하는 공정을 차례로 실시하여서 이루어짐을 특징으로 하는 메모리 셀 제조 방법.In the method of manufacturing a memory cell of a semiconductor integrated circuit, a polysilicon plug 4, a bit line 5, an oxide film 6, and a nitride film (i.e., a film) on a normal substrate 1 on which a field oxide film 2 and a gate 3 are formed. 7) forming and patterning the doped polysilicon (8) on the entire surface and depositing the doped polysilicon in the patterned state after forming an oxide film (9) and a nitride film (10) thereon; 11) forming a sidewall by anisotropic dry etching the polysilicon 11, and removing the nitride film 10 by wet etching and anisotropic dry etching the oxide film 9 and then doped After the polysilicon 12 is formed, the polysilicon 12 is primaryly anisotropically dry-etched and the oxide film 9 is anisotropically dry-etched, and the polysilicon 12 is secondaryly anisotropically dry-etched to form an upper node and a lower portion. Balls that allow nodes to be connected and wet-etch oxide oxide (9) And a process of forming and patterning the capacitor dielectric film (13) and the plate polysilicon (14) in this order.
KR1019910005968A 1991-04-13 1991-04-13 Method of fabricating memory cell KR930009130B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910005968A KR930009130B1 (en) 1991-04-13 1991-04-13 Method of fabricating memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910005968A KR930009130B1 (en) 1991-04-13 1991-04-13 Method of fabricating memory cell

Publications (2)

Publication Number Publication Date
KR920020711A KR920020711A (en) 1992-11-21
KR930009130B1 true KR930009130B1 (en) 1993-09-23

Family

ID=19313261

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910005968A KR930009130B1 (en) 1991-04-13 1991-04-13 Method of fabricating memory cell

Country Status (1)

Country Link
KR (1) KR930009130B1 (en)

Also Published As

Publication number Publication date
KR920020711A (en) 1992-11-21

Similar Documents

Publication Publication Date Title
KR100207302B1 (en) Method of manufacturing semiconductor device
JPH10303392A (en) Manufacture of semiconductor device
KR930009130B1 (en) Method of fabricating memory cell
KR100226778B1 (en) The manufacturing method of semiconductor device
KR930008584B1 (en) Method of fabricating semiconductor memory cell
KR940003590B1 (en) Method of fabricating a memory cell
KR100345067B1 (en) Manufacturing method of semiconductor device
KR19990039110A (en) Contact hole formation method of semiconductor device
KR20010008839A (en) Method of forming self-aligned contacts in semiconductor device
KR100612554B1 (en) Capacitor of semiconductor device and method for fabricating the same
KR930009584B1 (en) Method for manufacturing a capacitor
KR100356475B1 (en) Method of manufacturing a transistor
KR100490299B1 (en) Method of manufacturing flash memory device
KR950013900B1 (en) Dram cell manufacturing process
KR100339418B1 (en) Method for fabricating of semiconductor device
KR940007387B1 (en) Method of fabricating a trench capacitor for semiconductor device
KR960005560B1 (en) Method for manufacturing a cavity capacitor of semiconductor device
KR100277883B1 (en) Manufacturing Method of Semiconductor Device
KR930008585B1 (en) Method for fabricating semiconductor memory cell
KR100196525B1 (en) Semiconductor device & manufacturing method
KR100252929B1 (en) Method for fabricating of memory cell
KR100328824B1 (en) Manufacturing method for capacitor
KR20000003342A (en) Self-align contact hole forming method of semiconductor apparatus
KR0151376B1 (en) Manufacture of semiconductor memory device
JP2694777B2 (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20020820

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee