KR0124803B1 - Fabrication method of gate electrode - Google Patents

Abstract

forming a gate insulating film, a first polysilicon film and an oxide film on a silicon substrate in sequence, and patterning by etching the oxide film selectively; forming a second polysilicon film to form a gate electrode and defining the length of the gate electrode by etching the second polysilicon film selectively; forming a planarization film on top of the whole structure; forming a silicide film on top of the second polysilicon film after revealing a part of the second polysilicon film by etch back of the planarization film; removing the planarization film and the oxide film, and etching the second polysilicon film, the first polysilicon film and the gate insulating film selectively using the silicide film as an etching mask.

Description

Semiconductor device manufacturing method

1 is a cross-sectional view of a gate electrode formed according to the prior art,

2 is a process diagram of forming a gate electrode according to an embodiment of the present invention,

3 is a process diagram for forming a gate electrode according to another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

27 photoresist 33,35 doped polysilicon film

34 oxide film 36 O ₃ -TEOS oxide film

38: silicide film

TECHNICAL FIELD The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method of forming a gate electrode of a MOS transistor having an ultrafine line width during a semiconductor device manufacturing process.

FIG. 1 is a cross sectional view of a process of manufacturing a gate electrode having a line width w according to a conventional method, in which reference numeral 1 denotes a silicon substrate, 2 a gate oxide film, 3 a gate electrode, and 4 a photoresist pattern.

As shown in the figure, the lower layer is etched using the photoresist pattern 4 as an etch barrier. The minimum line width of the gate electrode 3 is determined according to the performance of the exposure apparatus used at this time.

Therefore, as the performance of the exposure machine is improved, the exposure cost of the exposure machine is greatly increased, and nevertheless, it is difficult to form an ultrafine pattern in terms of exposure characteristics.

The present invention devised to solve the above problems is to manufacture a semiconductor device to form a gate electrode having a line width of 0.1㎛ or less by adjusting the minimum line width according to the deposition thickness of the conductive film for the gate electrode without using an expensive high-performance exposure machine The purpose is to provide a method.

In order to achieve the above object, a method of manufacturing a semiconductor device of the present invention includes forming a gate insulating film, a first polysilicon film, and an oxide film on a silicon substrate, and then selectively etching and patterning the oxide film; Forming a second polysilicon layer on the entire structure to form a gate electrode, and selectively etching at least the second polysilicon layer to define a length of the gate electrode; Forming a planarization film on the entire structure; Etching back the planarization layer to expose a portion of the second polysilicon layer, and then forming a silicide layer on the second polysilicon layer; And removing the planarization layer and the oxide layer, and selectively etching the second polysilicon layer, the first polysilicon layer, and the gate insulating layer using the silicide layer as an etching mask.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, FIGS. 2A to 2E are diagrams illustrating a process of manufacturing a gate electrode according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, doping of 200 Å to 500 Å is performed on the silicon substrate 21 to prevent plasma damage to the gate oxide film 22 having a thickness of 200 Å or less and later in the process. The polysilicon film 23 is formed in turn, and then the oxide film 24, which is a sacrificial film, is deposited on the entire structure, and the oxide film 24 is selectively etched by a photolithography method to remove predetermined portions of the polysilicon film 23. Expose

Subsequently, as shown in FIG. 2B, a doped polysilicon film 25 of 1000 Å or less is formed on the entire structure, and then the length L of the gate electrode is defined by selective etching using a photolithography method. .

Next, as shown in FIG. 2C, a chemical vapor deposition (CVD) oxide film 26 is deposited on the entire structure, and the photoresist 27 is embedded in the recess groove. At this time, it is also possible to use a spin on glass (SOG) film in place of the photoresist 27.

Subsequently, as shown in FIG. 2D, etching back is performed to expose the oxide film 26, the photoresist 27 is removed, and the silicide film is formed on the polysilicon film 25 using a selective deposition method. Form 28. In this case, tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), or the like may be used as the transition metal used for selective deposition.

Finally, in FIG. 2E, the oxide films 24 and 26 are removed by wet etching, and the entire surface is etched using the silicide film 28 as an etching mask to selectively remove unnecessary polysilicon films to have an ultrafine line width of 0.1 μm or less. A gate electrode is formed.

3A to 3C are diagrams illustrating a process of forming a gate electrode according to another exemplary embodiment of the present invention. First, FIG. 3A is an anisotropic etching process after the process of FIG. ) Is exposed, and then a cross-sectional view of the O ₃ -TEOS oxide film 36 is planarized. Reference numeral 31 denotes a silicon substrate, 32 a gate oxide film, and 33 and 35 a doped polysilicon film, respectively.

Then, dry etching the O ₃ -TEOS oxide film 36 for planarization until the polysilicon film 35 is exposed, as shown in FIG. 3B, and then selectively depositing it on top of the exposed polysilicon film 35. The silicide film 38 is formed in a manner. In this case, tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), or the like may be used as the transition metal used for selective deposition.

Finally, as shown in FIG. 3C, the oxide films 34 and 36 are removed using wet etching, and the entire surface is etched using the silicide film 38 as an etching mask to selectively remove unnecessary polysilicon films, thereby providing an ultrafine line width. To form a gate electrode.

According to the present invention as described above, a gate electrode having a thickness of 0.1 μm or less, in which the line width of the gate electrode is determined according to the deposition thickness of the conductive film for the gate electrode, can be easily manufactured. Reduction in production costs can be expected.

Claims (5)

Forming a gate insulating film, a first polysilicon film, and an oxide film sequentially on a silicon substrate, and then selectively etching and patterning the oxide film; Forming a second polysilicon layer on the entire structure to form a gate electrode, and selectively etching at least the second polysilicon layer to define a length of the gate electrode; Forming a planarization film on the entire structure; Etching back the planarization layer to expose a portion of the second polysilicon layer, and then forming a silicide layer on the second polysilicon layer; And selectively etching the second polysilicon film, the first polysilicon film, and the gate insulating film by removing the planarization film and the oxide film and using the silicide film as an etching mask. The method of claim 1, wherein the forming of the planarization film comprises forming an oxide film of a chemical vapor deposition method, and forming a planarization by filling a recess groove using a photoresist or SOG film. A semiconductor device manufacturing method characterized by the above-mentioned. The method of claim 1, wherein the planarization film comprises an O ₃ -TEOS oxide film. The method of claim 1, wherein the first polysilicon film is formed to a thickness of 200 kV to 500 kV. The semiconductor device manufacturing method according to claim 1 or 2, wherein the second polysilicon film is formed so that its thickness does not exceed 1000 GPa.