JPWO2023203764A5 - - Google Patents
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- Publication number
- JPWO2023203764A5 JPWO2023203764A5 JP2024516044A JP2024516044A JPWO2023203764A5 JP WO2023203764 A5 JPWO2023203764 A5 JP WO2023203764A5 JP 2024516044 A JP2024516044 A JP 2024516044A JP 2024516044 A JP2024516044 A JP 2024516044A JP WO2023203764 A5 JPWO2023203764 A5 JP WO2023203764A5
- Authority
- JP
- Japan
- Prior art keywords
- hybrid bonding
- insulating film
- semiconductor
- component
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2022/018580 WO2023203764A1 (ja) | 2022-04-22 | 2022-04-22 | 半導体装置、及び、半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2023203764A1 JPWO2023203764A1 (https=) | 2023-10-26 |
| JPWO2023203764A5 true JPWO2023203764A5 (https=) | 2025-04-22 |
| JP7827136B2 JP7827136B2 (ja) | 2026-03-10 |
Family
ID=88419484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024516044A Active JP7827136B2 (ja) | 2022-04-22 | 2022-04-22 | 半導体装置、及び、半導体装置の製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20250273610A1 (https=) |
| JP (1) | JP7827136B2 (https=) |
| CN (1) | CN119096341A (https=) |
| WO (1) | WO2023203764A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2025145600A (ja) * | 2024-03-22 | 2025-10-03 | Rapidus株式会社 | 半導体システムおよび半導体システムの製造方法 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012222038A (ja) * | 2011-04-05 | 2012-11-12 | Elpida Memory Inc | 半導体装置の製造方法 |
| JP2014063974A (ja) * | 2012-08-27 | 2014-04-10 | Ps4 Luxco S A R L | チップ積層体、該チップ積層体を備えた半導体装置、及び半導体装置の製造方法 |
| JP6496389B2 (ja) * | 2017-11-28 | 2019-04-03 | 東芝メモリ株式会社 | 半導体装置及びその製造方法 |
-
2022
- 2022-04-22 JP JP2024516044A patent/JP7827136B2/ja active Active
- 2022-04-22 WO PCT/JP2022/018580 patent/WO2023203764A1/ja not_active Ceased
- 2022-04-22 US US18/857,184 patent/US20250273610A1/en active Pending
- 2022-04-22 CN CN202280095053.9A patent/CN119096341A/zh active Pending
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