JPWO2023170751A5 - - Google Patents

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Publication number
JPWO2023170751A5
JPWO2023170751A5 JP2022550241A JP2022550241A JPWO2023170751A5 JP WO2023170751 A5 JPWO2023170751 A5 JP WO2023170751A5 JP 2022550241 A JP2022550241 A JP 2022550241A JP 2022550241 A JP2022550241 A JP 2022550241A JP WO2023170751 A5 JPWO2023170751 A5 JP WO2023170751A5
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JP
Japan
Prior art keywords
insulating film
forming
modified layer
substrate
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2022550241A
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English (en)
Japanese (ja)
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JPWO2023170751A1 (https=
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/JP2022/009757 external-priority patent/WO2023170751A1/ja
Publication of JPWO2023170751A1 publication Critical patent/JPWO2023170751A1/ja
Publication of JPWO2023170751A5 publication Critical patent/JPWO2023170751A5/ja
Pending legal-status Critical Current

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JP2022550241A 2022-03-07 2022-03-07 Pending JPWO2023170751A1 (https=)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/009757 WO2023170751A1 (ja) 2022-03-07 2022-03-07 半導体装置の製造方法および半導体装置

Publications (2)

Publication Number Publication Date
JPWO2023170751A1 JPWO2023170751A1 (https=) 2023-09-14
JPWO2023170751A5 true JPWO2023170751A5 (https=) 2024-02-14

Family

ID=87936363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022550241A Pending JPWO2023170751A1 (https=) 2022-03-07 2022-03-07

Country Status (2)

Country Link
JP (1) JPWO2023170751A1 (https=)
WO (1) WO2023170751A1 (https=)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6376351A (ja) * 1986-09-18 1988-04-06 Nec Corp 多層配線の形成方法
US6166439A (en) * 1997-12-30 2000-12-26 Advanced Micro Devices, Inc. Low dielectric constant material and method of application to isolate conductive lines
JP4016884B2 (ja) * 2003-05-27 2007-12-05 セイコーエプソン株式会社 電気光学パネルの製造方法、電気光学パネルの製造プログラム及び電気光学パネルの製造装置、並びに電子機器の製造方法
JP3974127B2 (ja) * 2003-09-12 2007-09-12 株式会社東芝 半導体装置の製造方法
JP2008300480A (ja) * 2007-05-30 2008-12-11 Konica Minolta Holdings Inc 有機薄膜トランジスタ、有機薄膜トランジスタシート及び有機薄膜トランジスタの製造方法
JPWO2009044659A1 (ja) * 2007-10-05 2011-02-03 コニカミノルタホールディングス株式会社 パターン形成方法

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