JPWO2021111604A1 - - Google Patents
Info
- Publication number
- JPWO2021111604A1 JPWO2021111604A1 JP2021562407A JP2021562407A JPWO2021111604A1 JP WO2021111604 A1 JPWO2021111604 A1 JP WO2021111604A1 JP 2021562407 A JP2021562407 A JP 2021562407A JP 2021562407 A JP2021562407 A JP 2021562407A JP WO2021111604 A1 JPWO2021111604 A1 JP WO2021111604A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/427—Power or ground buses
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/481—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes on the rear surfaces of the wafers or substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
- H10D84/968—Macro-architecture
- H10D84/974—Layout specifications, i.e. inner core regions
- H10D84/975—Wiring regions or routing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
- H10D84/968—Macro-architecture
- H10D84/974—Layout specifications, i.e. inner core regions
- H10D84/981—Power supply lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
- H10D84/992—Noise prevention, e.g. preventing crosstalk
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023171195A JP7639871B2 (ja) | 2019-12-05 | 2023-10-02 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2019/047688 WO2021111604A1 (ja) | 2019-12-05 | 2019-12-05 | 半導体装置 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023171195A Division JP7639871B2 (ja) | 2019-12-05 | 2023-10-02 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2021111604A1 true JPWO2021111604A1 (https=) | 2021-06-10 |
| JPWO2021111604A5 JPWO2021111604A5 (https=) | 2022-12-08 |
| JP7363921B2 JP7363921B2 (ja) | 2023-10-18 |
Family
ID=76221141
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021562407A Active JP7363921B2 (ja) | 2019-12-05 | 2019-12-05 | 半導体装置 |
| JP2023171195A Active JP7639871B2 (ja) | 2019-12-05 | 2023-10-02 | 半導体装置 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023171195A Active JP7639871B2 (ja) | 2019-12-05 | 2023-10-02 | 半導体装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US12284828B2 (https=) |
| JP (2) | JP7363921B2 (https=) |
| CN (1) | CN114762113B (https=) |
| WO (1) | WO2021111604A1 (https=) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2023053203A1 (https=) * | 2021-09-28 | 2023-04-06 | ||
| JPWO2023095616A1 (https=) * | 2021-11-29 | 2023-06-01 | ||
| US20230420369A1 (en) * | 2022-06-28 | 2023-12-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit device and manufacturing method |
| JPWO2024214205A1 (https=) * | 2023-04-12 | 2024-10-17 | ||
| CN120958979A (zh) * | 2023-04-12 | 2025-11-14 | 株式会社索思未来 | 半导体装置 |
| JPWO2024252660A1 (https=) * | 2023-06-09 | 2024-12-12 | ||
| WO2026074865A1 (ja) * | 2024-10-04 | 2026-04-09 | 株式会社ソシオネクスト | 半導体集積回路装置 |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5326689A (en) * | 1976-08-25 | 1978-03-11 | Hitachi Ltd | Semiconductor integrated circuit unit |
| JPH05206420A (ja) * | 1992-01-30 | 1993-08-13 | Nec Ic Microcomput Syst Ltd | 半導体集積回路 |
| JPH11102910A (ja) * | 1997-09-29 | 1999-04-13 | Hitachi Ltd | 半導体集積回路 |
| JP2000223575A (ja) * | 1999-01-28 | 2000-08-11 | Hitachi Ltd | 半導体装置の設計方法、半導体装置および半導体装置の製造方法 |
| JP2009302198A (ja) * | 2008-06-11 | 2009-12-24 | Elpida Memory Inc | 半導体チップ、半導体チップ群および半導体装置 |
| JP2011159810A (ja) * | 2010-02-01 | 2011-08-18 | Renesas Electronics Corp | 半導体集積回路及びその制御方法 |
| JP2012044042A (ja) * | 2010-08-20 | 2012-03-01 | Kawasaki Microelectronics Inc | 半導体集積回路および半導体集積回路装置 |
| JP2014165358A (ja) * | 2013-02-26 | 2014-09-08 | Panasonic Corp | 半導体装置及びその製造方法 |
| US20150187642A1 (en) * | 2013-12-30 | 2015-07-02 | International Business Machines Corporation | Double-sided segmented line architecture in 3d integration |
| JP2018190760A (ja) * | 2017-04-28 | 2018-11-29 | 株式会社ソシオネクスト | 半導体装置 |
| WO2019194007A1 (ja) * | 2018-04-05 | 2019-10-10 | 株式会社ソシオネクスト | 半導体集積回路装置 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009177200A (ja) * | 1998-05-01 | 2009-08-06 | Sony Corp | 半導体記憶装置 |
| JP2009124667A (ja) * | 2007-01-25 | 2009-06-04 | Panasonic Corp | 双方向スイッチ及びその駆動方法 |
| JP4962173B2 (ja) | 2007-07-02 | 2012-06-27 | ソニー株式会社 | 半導体集積回路 |
| US8530273B2 (en) | 2010-09-29 | 2013-09-10 | Guardian Industries Corp. | Method of making oxide thin film transistor array |
| DE102013207324A1 (de) | 2012-05-11 | 2013-11-14 | Semiconductor Energy Laboratory Co., Ltd. | Halbleitervorrichtung und elektronisches Gerät |
| EP2884542A3 (en) | 2013-12-10 | 2015-09-02 | IMEC vzw | Integrated circuit device with power gating switch in back end of line |
| US10325840B2 (en) | 2015-09-25 | 2019-06-18 | Intel Corporation | Metal on both sides with power distributed through the silicon |
| US9754923B1 (en) | 2016-05-09 | 2017-09-05 | Qualcomm Incorporated | Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs) |
| EP3324436B1 (en) | 2016-11-21 | 2020-08-05 | IMEC vzw | An integrated circuit chip with power delivery network on the backside of the chip |
| US10950546B1 (en) | 2019-09-17 | 2021-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including back side power supply circuit |
| US11004789B2 (en) | 2019-09-30 | 2021-05-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including back side power supply circuit |
-
2019
- 2019-12-05 CN CN201980102690.2A patent/CN114762113B/zh active Active
- 2019-12-05 JP JP2021562407A patent/JP7363921B2/ja active Active
- 2019-12-05 WO PCT/JP2019/047688 patent/WO2021111604A1/ja not_active Ceased
-
2022
- 2022-05-31 US US17/829,341 patent/US12284828B2/en active Active
-
2023
- 2023-10-02 JP JP2023171195A patent/JP7639871B2/ja active Active
-
2025
- 2025-03-25 US US19/089,996 patent/US20250227996A1/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5326689A (en) * | 1976-08-25 | 1978-03-11 | Hitachi Ltd | Semiconductor integrated circuit unit |
| JPH05206420A (ja) * | 1992-01-30 | 1993-08-13 | Nec Ic Microcomput Syst Ltd | 半導体集積回路 |
| JPH11102910A (ja) * | 1997-09-29 | 1999-04-13 | Hitachi Ltd | 半導体集積回路 |
| JP2000223575A (ja) * | 1999-01-28 | 2000-08-11 | Hitachi Ltd | 半導体装置の設計方法、半導体装置および半導体装置の製造方法 |
| JP2009302198A (ja) * | 2008-06-11 | 2009-12-24 | Elpida Memory Inc | 半導体チップ、半導体チップ群および半導体装置 |
| JP2011159810A (ja) * | 2010-02-01 | 2011-08-18 | Renesas Electronics Corp | 半導体集積回路及びその制御方法 |
| JP2012044042A (ja) * | 2010-08-20 | 2012-03-01 | Kawasaki Microelectronics Inc | 半導体集積回路および半導体集積回路装置 |
| JP2014165358A (ja) * | 2013-02-26 | 2014-09-08 | Panasonic Corp | 半導体装置及びその製造方法 |
| US20150187642A1 (en) * | 2013-12-30 | 2015-07-02 | International Business Machines Corporation | Double-sided segmented line architecture in 3d integration |
| JP2018190760A (ja) * | 2017-04-28 | 2018-11-29 | 株式会社ソシオネクスト | 半導体装置 |
| WO2019194007A1 (ja) * | 2018-04-05 | 2019-10-10 | 株式会社ソシオネクスト | 半導体集積回路装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114762113A (zh) | 2022-07-15 |
| JP7639871B2 (ja) | 2025-03-05 |
| CN114762113B (zh) | 2024-11-01 |
| US20220293634A1 (en) | 2022-09-15 |
| US12284828B2 (en) | 2025-04-22 |
| WO2021111604A1 (ja) | 2021-06-10 |
| JP2023171884A (ja) | 2023-12-05 |
| JP7363921B2 (ja) | 2023-10-18 |
| US20250227996A1 (en) | 2025-07-10 |
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