JPWO2023053203A1 - - Google Patents
Info
- Publication number
- JPWO2023053203A1 JPWO2023053203A1 JP2023550789A JP2023550789A JPWO2023053203A1 JP WO2023053203 A1 JPWO2023053203 A1 JP WO2023053203A1 JP 2023550789 A JP2023550789 A JP 2023550789A JP 2023550789 A JP2023550789 A JP 2023550789A JP WO2023053203 A1 JPWO2023053203 A1 JP WO2023053203A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/427—Power or ground buses
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2021/035637 WO2023053203A1 (ja) | 2021-09-28 | 2021-09-28 | 半導体集積回路装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPWO2023053203A1 true JPWO2023053203A1 (https=) | 2023-04-06 |
Family
ID=85781514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023550789A Pending JPWO2023053203A1 (https=) | 2021-09-28 | 2021-09-28 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20240234322A1 (https=) |
| JP (1) | JPWO2023053203A1 (https=) |
| WO (1) | WO2023053203A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021075540A1 (ja) * | 2019-10-18 | 2021-04-22 | 株式会社ソシオネクスト | 半導体集積回路装置 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009016683A (ja) * | 2007-07-06 | 2009-01-22 | Panasonic Corp | スタンダードセルを用いた半導体集積回路、及びスタンダードセルライブラリ |
| US20180151494A1 (en) * | 2016-11-28 | 2018-05-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having buried metal line and fabrication method of the same |
| WO2021075353A1 (ja) * | 2019-10-18 | 2021-04-22 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2021111604A1 (ja) * | 2019-12-05 | 2021-06-10 | 株式会社ソシオネクスト | 半導体装置 |
-
2021
- 2021-09-28 JP JP2023550789A patent/JPWO2023053203A1/ja active Pending
- 2021-09-28 WO PCT/JP2021/035637 patent/WO2023053203A1/ja not_active Ceased
-
2024
- 2024-03-19 US US18/609,760 patent/US20240234322A1/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009016683A (ja) * | 2007-07-06 | 2009-01-22 | Panasonic Corp | スタンダードセルを用いた半導体集積回路、及びスタンダードセルライブラリ |
| US20180151494A1 (en) * | 2016-11-28 | 2018-05-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having buried metal line and fabrication method of the same |
| WO2021075353A1 (ja) * | 2019-10-18 | 2021-04-22 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2021111604A1 (ja) * | 2019-12-05 | 2021-06-10 | 株式会社ソシオネクスト | 半導体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023053203A1 (ja) | 2023-04-06 |
| US20240234322A1 (en) | 2024-07-11 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20240815 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20250722 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20251216 |