JPWO2021105811A5 - - Google Patents

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Publication number
JPWO2021105811A5
JPWO2021105811A5 JP2021560756A JP2021560756A JPWO2021105811A5 JP WO2021105811 A5 JPWO2021105811 A5 JP WO2021105811A5 JP 2021560756 A JP2021560756 A JP 2021560756A JP 2021560756 A JP2021560756 A JP 2021560756A JP WO2021105811 A5 JPWO2021105811 A5 JP WO2021105811A5
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JP
Japan
Prior art keywords
layer
decoder
memory cell
cell section
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2021560756A
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English (en)
Japanese (ja)
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JPWO2021105811A1 (https=
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/IB2020/060677 external-priority patent/WO2021105811A1/ja
Publication of JPWO2021105811A1 publication Critical patent/JPWO2021105811A1/ja
Publication of JPWO2021105811A5 publication Critical patent/JPWO2021105811A5/ja
Priority to JP2025083305A priority Critical patent/JP2025118931A/ja
Withdrawn legal-status Critical Current

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JP2021560756A 2019-11-26 2020-11-13 Withdrawn JPWO2021105811A1 (https=)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025083305A JP2025118931A (ja) 2019-11-26 2025-05-19 記憶装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019213485 2019-11-26
PCT/IB2020/060677 WO2021105811A1 (ja) 2019-11-26 2020-11-13 記憶装置、および電子機器

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2025083305A Division JP2025118931A (ja) 2019-11-26 2025-05-19 記憶装置

Publications (2)

Publication Number Publication Date
JPWO2021105811A1 JPWO2021105811A1 (https=) 2021-06-03
JPWO2021105811A5 true JPWO2021105811A5 (https=) 2023-11-14

Family

ID=76130061

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2021560756A Withdrawn JPWO2021105811A1 (https=) 2019-11-26 2020-11-13
JP2025083305A Withdrawn JP2025118931A (ja) 2019-11-26 2025-05-19 記憶装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2025083305A Withdrawn JP2025118931A (ja) 2019-11-26 2025-05-19 記憶装置

Country Status (3)

Country Link
US (1) US12193236B2 (https=)
JP (2) JPWO2021105811A1 (https=)
WO (1) WO2021105811A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230074757A (ko) 2020-10-02 2023-05-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3999900B2 (ja) * 1998-09-10 2007-10-31 株式会社東芝 不揮発性半導体メモリ
JP2004334982A (ja) * 2003-05-08 2004-11-25 Nec Electronics Corp 行デコーダ、半導体回路装置
JP2010263211A (ja) * 2009-05-04 2010-11-18 Samsung Electronics Co Ltd 積層メモリ素子
JP2011044222A (ja) * 2009-07-22 2011-03-03 Toshiba Corp Ｎａｎｄ型フラッシュメモリ
JP2011187794A (ja) 2010-03-10 2011-09-22 Toshiba Corp 半導体記憶装置及びその製造方法
JP2012146861A (ja) 2011-01-13 2012-08-02 Toshiba Corp 半導体記憶装置
US9595533B2 (en) 2012-08-30 2017-03-14 Micron Technology, Inc. Memory array having connections going through control gates
JP2015056642A (ja) 2013-09-13 2015-03-23 株式会社東芝 半導体記憶装置
JP6430302B2 (ja) 2015-03-13 2018-11-28 東芝メモリ株式会社 不揮発性半導体記憶装置
JP6545587B2 (ja) * 2015-09-15 2019-07-17 東芝メモリ株式会社 半導体装置
US10593693B2 (en) * 2017-06-16 2020-03-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US10665580B1 (en) * 2019-01-08 2020-05-26 Sandisk Technologies Llc Bonded structure including a performance-optimized support chip and a stress-optimized three-dimensional memory chip and method for making the same

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