JPWO2021033075A1 - - Google Patents

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Publication number
JPWO2021033075A1
JPWO2021033075A1 JP2021541332A JP2021541332A JPWO2021033075A1 JP WO2021033075 A1 JPWO2021033075 A1 JP WO2021033075A1 JP 2021541332 A JP2021541332 A JP 2021541332A JP 2021541332 A JP2021541332 A JP 2021541332A JP WO2021033075 A1 JPWO2021033075 A1 JP WO2021033075A1
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2021541332A
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Japanese (ja)
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JP7720782B2 (ja
JPWO2021033075A5 (https=
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Publication of JPWO2021033075A1 publication Critical patent/JPWO2021033075A1/ja
Publication of JPWO2021033075A5 publication Critical patent/JPWO2021033075A5/ja
Priority to JP2025126415A priority Critical patent/JP2025146965A/ja
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/10—Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
JP2021541332A 2019-08-22 2020-08-11 メモリセルおよび記憶装置 Active JP7720782B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025126415A JP2025146965A (ja) 2019-08-22 2025-07-29 半導体装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019151814 2019-08-22
JP2019151814 2019-08-22
PCT/IB2020/057527 WO2021033075A1 (ja) 2019-08-22 2020-08-11 メモリセルおよび記憶装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2025126415A Division JP2025146965A (ja) 2019-08-22 2025-07-29 半導体装置

Publications (3)

Publication Number Publication Date
JPWO2021033075A1 true JPWO2021033075A1 (https=) 2021-02-25
JPWO2021033075A5 JPWO2021033075A5 (https=) 2023-08-08
JP7720782B2 JP7720782B2 (ja) 2025-08-08

Family

ID=74660681

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2021541332A Active JP7720782B2 (ja) 2019-08-22 2020-08-11 メモリセルおよび記憶装置
JP2025126415A Pending JP2025146965A (ja) 2019-08-22 2025-07-29 半導体装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2025126415A Pending JP2025146965A (ja) 2019-08-22 2025-07-29 半導体装置

Country Status (5)

Country Link
US (1) US12457732B2 (https=)
JP (2) JP7720782B2 (https=)
KR (1) KR20220050134A (https=)
CN (1) CN114258586A (https=)
WO (1) WO2021033075A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240165976A (ko) * 2022-03-31 2024-11-25 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 기억 장치, 및 전자 기기
JPWO2023223127A1 (https=) * 2022-05-16 2023-11-23
WO2025078928A1 (ja) * 2023-10-13 2025-04-17 株式会社半導体エネルギー研究所 半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015181159A (ja) * 2014-03-07 2015-10-15 株式会社半導体エネルギー研究所 半導体装置
JP2016127117A (ja) * 2014-12-26 2016-07-11 株式会社半導体エネルギー研究所 記憶装置及びその駆動方法
JP2016225617A (ja) * 2015-05-26 2016-12-28 株式会社半導体エネルギー研究所 記憶装置、又は該記憶装置を有する電子機器
JP2017168809A (ja) * 2015-10-22 2017-09-21 株式会社半導体エネルギー研究所 半導体装置、又は該半導体装置を有する記憶装置
JP2018037675A (ja) * 2017-10-30 2018-03-08 株式会社半導体エネルギー研究所 半導体装置

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US5646870A (en) * 1995-02-13 1997-07-08 Advanced Micro Devices, Inc. Method for setting and adjusting process parameters to maintain acceptable critical dimensions across each die of mass-produced semiconductor wafers
JP2001185700A (ja) 1999-12-27 2001-07-06 Mitsubishi Electric Corp 半導体記憶装置
EP1998373A3 (en) 2005-09-29 2012-10-31 Semiconductor Energy Laboratory Co, Ltd. Semiconductor device having oxide semiconductor layer and manufacturing method thereof
JP5064747B2 (ja) 2005-09-29 2012-10-31 株式会社半導体エネルギー研究所 半導体装置、電気泳動表示装置、表示モジュール、電子機器、及び半導体装置の作製方法
US7898893B2 (en) 2007-09-12 2011-03-01 Samsung Electronics Co., Ltd. Multi-layered memory devices
JP2010263211A (ja) 2009-05-04 2010-11-18 Samsung Electronics Co Ltd 積層メモリ素子
KR101698193B1 (ko) 2009-09-15 2017-01-19 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
KR101870119B1 (ko) 2009-12-25 2018-06-25 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP2012256821A (ja) 2010-09-13 2012-12-27 Semiconductor Energy Lab Co Ltd 記憶装置
JP2013236068A (ja) * 2012-04-12 2013-11-21 Semiconductor Energy Lab Co Ltd 半導体装置及び半導体装置の作製方法
JP2014135398A (ja) * 2013-01-10 2014-07-24 Fujitsu Semiconductor Ltd 半導体記憶装置
KR102367921B1 (ko) * 2014-03-14 2022-02-25 가부시키가이샤 한도오따이 에네루기 켄큐쇼 회로 시스템
JP6635670B2 (ja) 2014-04-11 2020-01-29 株式会社半導体エネルギー研究所 半導体装置
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TW202537448A (zh) 2019-01-25 2025-09-16 日商半導體能源研究所股份有限公司 半導體裝置及包括該半導體裝置的電子裝置
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KR102943470B1 (ko) 2019-02-22 2026-03-25 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 상기 반도체 장치를 가지는 전기 기기
KR20250125448A (ko) 2019-02-22 2025-08-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 오류 검출 기능을 가지는 기억 장치, 반도체 장치, 및 전자 기기

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Publication number Priority date Publication date Assignee Title
JP2015181159A (ja) * 2014-03-07 2015-10-15 株式会社半導体エネルギー研究所 半導体装置
JP2016127117A (ja) * 2014-12-26 2016-07-11 株式会社半導体エネルギー研究所 記憶装置及びその駆動方法
JP2016225617A (ja) * 2015-05-26 2016-12-28 株式会社半導体エネルギー研究所 記憶装置、又は該記憶装置を有する電子機器
JP2017168809A (ja) * 2015-10-22 2017-09-21 株式会社半導体エネルギー研究所 半導体装置、又は該半導体装置を有する記憶装置
JP2018037675A (ja) * 2017-10-30 2018-03-08 株式会社半導体エネルギー研究所 半導体装置

Also Published As

Publication number Publication date
WO2021033075A1 (ja) 2021-02-25
JP7720782B2 (ja) 2025-08-08
US20220310616A1 (en) 2022-09-29
US12457732B2 (en) 2025-10-28
CN114258586A (zh) 2022-03-29
JP2025146965A (ja) 2025-10-03
KR20220050134A (ko) 2022-04-22

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