JPWO2019226229A5 - - Google Patents
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- Publication number
- JPWO2019226229A5 JPWO2019226229A5 JP2021516521A JP2021516521A JPWO2019226229A5 JP WO2019226229 A5 JPWO2019226229 A5 JP WO2019226229A5 JP 2021516521 A JP2021516521 A JP 2021516521A JP 2021516521 A JP2021516521 A JP 2021516521A JP WO2019226229 A5 JPWO2019226229 A5 JP WO2019226229A5
- Authority
- JP
- Japan
- Prior art keywords
- gate
- gem
- metal
- source
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 26
- 239000002184 metal Substances 0.000 claims 24
- 238000004519 manufacturing process Methods 0.000 claims 11
- 125000006850 spacer group Chemical group 0.000 claims 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 4
- 238000002955 isolation Methods 0.000 claims 4
- 229910052710 silicon Inorganic materials 0.000 claims 4
- 239000010703 silicon Substances 0.000 claims 4
- 239000000758 substrate Substances 0.000 claims 4
- 239000002070 nanowire Substances 0.000 claims 2
- 238000000034 method Methods 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/989,604 | 2018-05-25 | ||
| US15/989,604 US10818762B2 (en) | 2018-05-25 | 2018-05-25 | Gate contact over active region in cell |
| PCT/US2019/024364 WO2019226229A1 (en) | 2018-05-25 | 2019-03-27 | Gate contact over active region in cell |
Publications (4)
| Publication Number | Publication Date |
|---|---|
| JP2021525974A JP2021525974A (ja) | 2021-09-27 |
| JPWO2019226229A5 true JPWO2019226229A5 (https=) | 2022-04-21 |
| JP2021525974A5 JP2021525974A5 (https=) | 2022-04-21 |
| JP7572948B2 JP7572948B2 (ja) | 2024-10-24 |
Family
ID=66102798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021516521A Active JP7572948B2 (ja) | 2018-05-25 | 2019-03-27 | セル内のアクティブ領域でのゲート接点 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US10818762B2 (https=) |
| EP (1) | EP3803962A1 (https=) |
| JP (1) | JP7572948B2 (https=) |
| KR (2) | KR20210002649A (https=) |
| CN (1) | CN112166498B (https=) |
| WO (1) | WO2019226229A1 (https=) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11152347B2 (en) * | 2018-04-13 | 2021-10-19 | Qualcomm Incorporated | Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections |
| US10818762B2 (en) * | 2018-05-25 | 2020-10-27 | Advanced Micro Devices, Inc. | Gate contact over active region in cell |
| US10846327B2 (en) * | 2018-11-02 | 2020-11-24 | A9.Com, Inc. | Visual attribute determination for content selection |
| EP3723127A1 (en) * | 2019-04-10 | 2020-10-14 | IMEC vzw | A standard cell device and a method for forming an interconnect structure for a standard cell device |
| US10796061B1 (en) * | 2019-08-29 | 2020-10-06 | Advanced Micro Devices, Inc. | Standard cell and power grid architectures with EUV lithography |
| US11362090B2 (en) | 2020-01-31 | 2022-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having buried logic conductor type of complementary field effect transistor, method of generating layout diagram and system for same |
| DE102020125647A1 (de) * | 2020-01-31 | 2021-08-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleitervorrichtung mit Komplementärfeldeffekttransistor des Typs mit vergrabenenen Logikleitern, Layout-Diagramm-Herstellungsverfahren und System dafür |
| US12205897B2 (en) | 2021-09-23 | 2025-01-21 | Advanced Micro Devices, Inc. | Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells |
Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5889329A (en) | 1994-11-02 | 1999-03-30 | Lsi Logic Corporation | Tri-directional interconnect architecture for SRAM |
| DE102004063926B4 (de) | 2004-03-24 | 2017-10-19 | Infineon Technologies Ag | Konfigurierbare Treiberzelle eines logischen Zellenfeldes |
| US7761831B2 (en) | 2005-12-29 | 2010-07-20 | Mosaid Technologies Incorporated | ASIC design using clock and power grid standard cell |
| JP4322888B2 (ja) | 2006-06-01 | 2009-09-02 | エルピーダメモリ株式会社 | 半導体装置 |
| US7984395B2 (en) | 2008-01-17 | 2011-07-19 | Synopsys, Inc. | Hierarchical compression for metal one logic layer |
| JP5410082B2 (ja) | 2008-12-12 | 2014-02-05 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
| US8533641B2 (en) | 2011-10-07 | 2013-09-10 | Baysand Inc. | Gate array architecture with multiple programmable regions |
| US8716124B2 (en) * | 2011-11-14 | 2014-05-06 | Advanced Micro Devices | Trench silicide and gate open with local interconnect with replacement gate process |
| KR20130070252A (ko) | 2011-12-19 | 2013-06-27 | 에스케이하이닉스 주식회사 | 반도체 메모리 소자의 스페어 로직 구현방법 및 그 구조 |
| EP2803077A4 (en) * | 2012-01-13 | 2015-11-04 | Tela Innovations Inc | CIRCUITS WITH LINEAR FINFET STRUCTURES |
| US8743580B2 (en) * | 2012-03-30 | 2014-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus for high speed ROM cells |
| US9461143B2 (en) * | 2012-09-19 | 2016-10-04 | Intel Corporation | Gate contact structure over active gate and method to fabricate same |
| US10283437B2 (en) | 2012-11-27 | 2019-05-07 | Advanced Micro Devices, Inc. | Metal density distribution for double pattern lithography |
| US9331013B2 (en) | 2013-03-14 | 2016-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated capacitor |
| US20160276287A1 (en) | 2013-12-06 | 2016-09-22 | Renesas Electronics Corporation | Semiconductor device |
| US9653346B2 (en) * | 2015-05-07 | 2017-05-16 | United Microelectronics Corp. | Integrated FinFET structure having a contact plug pitch larger than fin and first metal pitch |
| KR102369511B1 (ko) | 2015-07-08 | 2022-03-03 | 삼성전자주식회사 | 반도체 집적 회로 및 이를 포함하는 전자 시스템 |
| US10672708B2 (en) | 2015-11-30 | 2020-06-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Standard-cell layout structure with horn power and smart metal cut |
| US9881872B2 (en) | 2016-01-15 | 2018-01-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating a local interconnect in a semiconductor device |
| WO2018042986A1 (ja) | 2016-08-29 | 2018-03-08 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| US11189569B2 (en) | 2016-09-23 | 2021-11-30 | Advanced Micro Devices, Inc. | Power grid layout designs for integrated circuits |
| US9837398B1 (en) | 2016-11-23 | 2017-12-05 | Advanced Micro Devices, Inc. | Metal track cutting in standard cell layouts |
| US10270430B2 (en) | 2016-12-28 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same |
| US10503859B2 (en) | 2017-08-30 | 2019-12-10 | Arm Limited | Integrated circuit design and/or fabrication |
| US11120190B2 (en) | 2017-11-21 | 2021-09-14 | Advanced Micro Devices, Inc. | Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level |
| US10818762B2 (en) * | 2018-05-25 | 2020-10-27 | Advanced Micro Devices, Inc. | Gate contact over active region in cell |
-
2018
- 2018-05-25 US US15/989,604 patent/US10818762B2/en active Active
-
2019
- 2019-03-27 CN CN201980035109.XA patent/CN112166498B/zh active Active
- 2019-03-27 EP EP19717063.2A patent/EP3803962A1/en active Pending
- 2019-03-27 KR KR1020207033968A patent/KR20210002649A/ko not_active Ceased
- 2019-03-27 JP JP2021516521A patent/JP7572948B2/ja active Active
- 2019-03-27 KR KR1020247006821A patent/KR102876341B1/ko active Active
- 2019-03-27 WO PCT/US2019/024364 patent/WO2019226229A1/en not_active Ceased
-
2020
- 2020-10-14 US US17/070,335 patent/US11424336B2/en active Active
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