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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
  • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
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  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
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  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6728—Vertical TFTs
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  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
  • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
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  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
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  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
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  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
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  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/10—Integrated device layouts
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/0698—Local interconnections
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Definitions

• Non-planar transistors are a recent development in semiconductor processing for reducing short channel effects.
• Tri-gate transistors, Fin field effect transistors (FETs) and gate all around (GAA) transistors are examples of non-planar transistors.
• the processing steps for non-planar devices (transistors) are more complex than the processing steps for planar devices (transistors).
• changes to the processing steps are made when these changes provide sufficient yield and do not increase the manufacturing costs above a limit.
• PNR place-and-route
• FIG. l is a generalized diagram of top and cross-sectional views of a cell layout with non- planar devices.
• FIG. 2 is a generalized diagram of top and cross-sectional views of a cell layout.
• FIG. 3 is a generalized diagram of a method for creating cell layout with contacts over gates in an active region of a non-planar device.
• FIG. 4 is a generalized diagram of a method for creating cell layout with contacts over gates in an active region of a non-planar device.
• FIG. 5 is a generalized diagram of top and cross-sectional views of a cell layout with non-planar devices.
• FIG. 6 is a generalized diagram of top and cross-sectional views of a cell layout with non-planar devices.
• FIG. 7 is a generalized diagram of a method for creating cell layout with contacts over gates in an active region of a non-planar device.
• the cell layout is a standard cell in a cell layout library. In other implementations, the cell layout is a custom designed cell, which is separate from the standard cell layout library.
• gate metal is placed over non-planar vertical conducting structures.
• the non-planar vertical conducting structures are used to form non-planar devices (transistors). Examples of non-planar devices are tri-gate transistors, fin field effect transistors (FETs) and gate all around (GAA) transistors.
• gate contacts connect gate metal to gate extension metal (GEM) above the gate metal. In an implementation, GEM is only used above the gate metal.
• a single gate contact per column of gate metal is included in cell layout to connect gate metal to GEM.
• two or more gate contacts are used to connect gate metal to GEM, which increases yield.
• the separate two or more gate contacts are placed at the top and bottom of cell layout for several columns.
• a gate contact or gate via is not located directly over the active region such as over one of the non-planar vertical conducting structures.
• To do so typically includes a complex semiconductor fabrication process, which includes using a self-aligned contacts process for the diffusion contact and gate contact.
• a complex semiconductor fabrication process which includes using a self-aligned contacts process for gate contacts, is not used. Rather, a less complex fabrication process is used instead to place gate contacts.
• GEM is placed above the gate metal and makes a connection with gate metal through the one or more gate contacts.
• gate extension contacts are formed above the active regions on the GEM. Similar to gate contacts between the gate metal and the GEM, in various implementations, gate extension contacts are formed with a less complex fabrication process than using a self-aligned contacts process. Gate extension contacts connect GEM to an interconnect layer such as a metal zero layer. Gate extension contacts do not connect to the gate contacts or the gate metal. In some implementations, gate extension contacts are aligned vertically with one of the non-planar vertical conducting structures. Therefore, in an implementation, one or more gate extension contacts are located above the active region. Accordingly, in an implementation, the height of cell layout is reduced, which improves scalability and metal track routing. [0019] Referring to FIG.
• a generalized block diagram of non-planar cell layout 100 which is a top view of cell layout, is shown. Additionally, a generalized block diagram of a cross-section view of the same cell layout from Side A, is shown. As shown, Side A is to the left of non- planar cell layout 100.
• the p-type metal oxide semiconductor (pmos) field effect transistors (fets) are at the top of cell layout 100.
• the n-type metal oxide semiconductor (nmos) field effect transistors (fets) are at the bottom of cell layout 100.
• the active regions are not shown in the cell layout 100 for ease of illustration.
• cell layout 100 is part of a standard cell layout library. In other implementations, cell layout 100 is custom layout cells for particular areas of a chip design.
• the layout techniques shown in figures 1-2 and 5-7 are used for a variety of other standard cells and custom cells used for a variety of complex gates and functional units.
• the devices (transistors) in the cell layout 100 are non-planar devices (transistors). Non-planar devices are a recent development in semiconductor processing for reducing short channel effects. Tri-gate transistors, Fin field effect transistors (FETs) and gate all around (GAA) transistors are examples of non-planar devices.
• the non-planar vertical conducting structures 110 come up out of the page in a three- dimensional manner.
• the non-planar vertical conducting structures 110 are also referred to as“vertical structures 110.” It is noted that the vertical structures 110 are considered vertical due to coming out of the page in a three-dimensional manner although the vertical structures 110 are routed in a horizontal direction.
• the vertical structures 110 are included in one of the above types of non-planar devices such as tri-gate transistors, fin field effect transistors (FETs) and gate all around (GAA) transistors.
• the non-planar devices in cell layout 100 are fabricated by one of the immersion lithography techniques, the double patterning technique, the extreme ultraviolet lithography (EETV) technique, and the directed self-assembly (DSA) lithography technique.
• the EETV technique provides more flexibility relative to via and contact modules relative to other techniques.
• cell layout 100 uses gate metal 112 in a vertical direction.
• titanium nitride (TiN) is used for the gate metal 112.
• the boundaries of the active regions are not shown for ease of illustration, but the rectangular boundaries of active regions are within a relatively close proximity of the vertical structures 110 and gate metal 112.
• the layer 140 is used to cut the gate layer and shows where the gate metal
• the local interconnect 130 is routed in a vertical direction similar to the gate metal 112.
• local interconnect 130 is copper, tungsten or cobalt and the material used is based on the design tradeoff between resistance and process dependability.
• copper, tungsten or cobalt contacts 132 are used for the source and drain regions.
• Metal 0 (M0 or MetalO) 120 is used for local interconnections in the horizontal direction. For ease of illustration, MetalO 120 is not shown in cell layout 100, but rather only in the cross-section view.
• the gate contact 114 connects gate metal 112 to gate extension metal (GEM) 116.
• GEM gate extension metal
• GEM 116 is only used above the gate metal 112.
• the separate gate contacts 114 are seen at the top of cell layout 100 and the bottom of cell layout 100 for several columns.
• a single gate contact 114 per column is included in cell layout 100 to connect gate metal 112 to GEM 116.
• two or more gate contacts 114 are used to connect gate metal 112 to GEM 116, which increases yield.
• a gate contact or gate via is not located directly over the active region such as over one of the vertical structures 110.
• a complex semiconductor fabrication process which includes using a self-aligned contacts process for the diffusion contact and gate contact.
• gate contacts 114 are placed outside the active regions, and thus, placed separate from the vertical structures 110. Therefore, a complex semiconductor fabrication process, which includes using a self-aligned contacts process for gate contacts 114, is not used. Rather, a less complex fabrication process is used instead to place gate contacts 114 outside the active regions.
• GEM 116 is placed above the gate metal 112 and makes a connection with gate metal 112 through the gate contacts 114.
• gate contacts 118 are formed above the active regions. Similar to gate contacts 114, in various implementations, gate extension contacts 118 are formed with a less complex fabrication process than using a self- aligned contacts process.
• Gate extension contacts 118 connect GEM 116 to the horizontal MetalO 120. Gate extension contacts 118 do not connect to the gate contacts 114 or the gate metal 112. It is noted that one or more of the gate extension contacts 118 are aligned vertically with one of the vertical structures 110. Therefore, in an implementation, one or more gate extension contacts 118 are located above the active region. Accordingly, in an implementation, the height of cell layout 100 is reduced, which improves scalability and metal track routing.
• FIG. 2 a generalized block diagram of non-planar cell layout 100, which is a top view of cell layout, is shown. Additionally, a generalized block diagram of a cross- section view of the same cell layout from Side B, is shown. As shown, Side B is at the bottom of non-planar cell layout 100. Layout elements described earlier are numbered identically.
• each of cell layout 100 is shown as a two-dimensional diagram, there are three- dimensional elements depicted in the diagrams. As described earlier, each of the vertical structures 110 is considered vertical due to coming out of the page in a three-dimensional manner although the vertical structures 110 are routed in a horizontal direction.
• source/drain contact 132 is further out of the page in a three-dimensional manner than gate extension contact 118.
• gate extension contact 118 is further out of the page than each of gate contacts 114.
• MetalO 120 making contact with source/drain contact 132 is further out of the page than metalO 120 making contact with gate extension contact 118. Therefore, a dashed line in the cross-section view is used to separate the two separate horizontal routes of metalO 120.
• the metalO 120 on the right of the dashed line is further out of the page than the metalO 120 on the left of the dashed line.
• each of gate extension contact 118 and vertical structure 110 is no further out of the page than the other. Accordingly, gate extension contact 118 is aligned vertically with vertical structures 110 in the cross-section view, and gate extension contact 118 is located above the active region.
• FIG. 3 a generalized block diagram of a method 300 for creating cell layout with contacts over gates in an active region of a non-planar device is shown.
• the steps in this implementation are shown in sequential order. However, in other implementations some steps occur in a different order than shown, some steps are performed concurrently, some steps are combined with other steps, and some steps are absent.
• One or more non-planar vertical conducting structures are formed on a silicon substrate (block 302).
• the non-planar vertical conducting structures are used to fabricate one of a variety of non-planar devices such as tri-gate transistors, fin field effect transistors (FETs) and gate all around (GAA) transistors.
• Gate metal is placed on a portion of the one or more non-planar vertical conducting structures (block 304).
• a gate contact is formed on one or more of the ends the metal gate (block 306). In various implementations, the gate contacts are not formed over one of the non-planar vertical conducting structures.
• Gate extension metal is placed above the metal gate on the one or more gate contacts (block 308).
• the length of the GEM is the same or greater than the length of the gate metal. In another implementation, the length of the GEM is less than the length of the gate metal.
• a gate extension contact is formed at a location on the GEM both above and aligned with one of the non-planar vertical conducting structures (block 310).
• the gate extension contact is formed above the active region.
• Local metal layers are placed for connecting local routes and power connections (block
• the cell layout is a standard cell in a cell layout library.
• the cell layout is a custom designed cell, which is separate from the standard cell layout library.
• FIG. 4 a generalized block diagram of a method 400 for creating cell layout with contacts over gates in an active region of a non-planar device is shown.
• a region is selected with an existing gate extension contact on gate extension metal (GEM) over a non- planar vertical conducting structure formed on a silicon substrate (block 402).
• GEM gate extension metal
• the region including the gate extension contact 118 at the top of the sixth column from the left is selected.
• a local interconnect layer is placed running parallel with a portion of a metal gate below the GEM between the selected region and a source/drain region that does not include a gate extension contact (block 404).
• a source/drain contact is formed at a location on the local interconnect layer in the source/drain region (block 406).
• source/drain contact 132 is placed to the right and below gate extension contact 118 at the top of the sixth column from the left.
• each of the local interconnect layer 130 and the source/drain contact 132 are placed between each of two gate metals and two gate extension metals (GEMs).
• GEMs gate extension metals
• Local metal layers for connecting local routes and power connections are placed (block 408).
• the cell layout is a standard cell in a cell layout library. In other implementations, the cell layout is a custom designed cell, which is separate from the standard cell layout library.
• FIG. 5 a generalized block diagram of non-planar cell layout 100, which is a top view of cell layout, is shown. Additionally, a generalized block diagram of a cross- section view of the same cell layout from Side B, is shown. As shown, Side B is at the bottom of non-planar cell layout 100. Layout elements described earlier are numbered identically. Although each of cell layouts 100 and 500 is shown as a two-dimensional diagram, there are three-dimensional elements depicted in the diagrams. As described earlier, each of the vertical structures 110 is considered vertical due to coming out of the page in a three-dimensional manner although the vertical structures 110 are routed in a horizontal direction. Additionally, in an implementation, in the cross-section view, source/drain contact 132 is further out of the page in a three-dimensional manner than gate extension contact 118. Next, gate extension contact 118 is further out of the page than each of gate contacts 114.
• each of gate extension contact 118 and vertical structure 110 is no further out of the page than the other. Accordingly, gate extension contact 118 is aligned vertically with vertical structures 110 in the cross-section view, and gate extension contact 118 is located above the active region.
• local interconnect layer 130 is formed over source/drain region (area) 142.
• source/drain area 142 is formed by an implantation process.
• each of the gate metals 112 in the cross-section view is surrounded by isolated spacers 150.
• each of the GEMs 116 is surrounded by isolated spacers 152.
• each of the isolated spacers 150 and 152 includes a same material.
• each of the isolated spacers 150 and 152 includes a different material.
• the material used for one or more of isolated spacers 150 and 152 is silicon nitride.
• the gate metal 112 is placed with a height reaching the top of the isolated spacers 150.
• the isolated spacers are formed over the gate metal 112 and the two materials are etched to near the final height of the gate metal 112. More isolated spacer 150 is placed on top of the gate metal 112 followed by etching and polishing. For example, SiN deposition and chemical mechanical planarization (CMP) steps are used. An area is etched into the isolated spacer 150 for the gate contact 114, so that the gate contact 114 makes a physical connection with GEM 116 and gate 112. Next, tetraethyl orthosilicate (TEOS) or other oxide deposition occurs followed by a trench is formed for GEM 116.
• TEOS tetraethyl orthosilicate
• the isolated spacer 150 is patterned and etched after it is deposited on the gate metal 112 followed by an oxide deposition, such as a TEOS deposition. Afterward, the trench for the GEM 116 is formed and then the final via etch.
• oxide deposition such as a TEOS deposition
• Cell layout 500 shows the source/drain contact 132 is dual self-aligned by the GEM 116 and MetalO layer 120.
• the MetalO layer 120 self-aligns the source/drain contact 132 into and out of the page.
• the isolated spacer 152 on the GEM 116 self-aligns the source/drain contact 132. If the GEM 116 is misaligned, then the isolated spacer 150 on the gate meal 112 self-aligns the source/drain contact 132 to the local interconnect layer 130.
• FIG. 6 a generalized block diagram of non-planar cell layout 100, which is a top view of cell layout, is shown.
• FIG. 1 a generalized block diagram of a cross- section view of the same cell layout from Side B, is shown. As shown, Side B is at the bottom of non-planar cell layout 100. Layout elements described earlier are numbered identically.
• the isolated spacer 154 reaches down to the gate metal 112 as shown in the cross-section view. Isolated spacer 154 provides further alignment and further isolation.
• each of the isolated spacers 150 and 154 includes a same material. In other implementations, each of the isolated spacers 150 and 154 includes a different material.
• FIG. 7 a generalized block diagram of a method 700 for creating cell layout with contacts over gates in an active region of a non-planar device is shown. Gate metal is placed on a portion of one or more non-planar vertical conducting structures (block 702).
• Isolating spacers are placed on either side of the gate metal (block 704). Isolating spacers are placed on top of the gate metal (block 706). A local interconnect layer is placed running parallel with a portion of a metal gate between the side spacers of the gate metals (block 708).
• Gate extension metal is placed above the metal gate on the one or more gate contacts (block 710). Isolating spacers are placed on either side of the GEM (block 712).
• Isolating spacer is placed on top of the GEM (block 714).
• a source/drain contact is formed at a location on the local interconnect layer in the source/drain region (block 716).
• Local metal layers are placed for connecting local routes and power connections (block 718).
• the cell layout is a standard cell in a cell layout library. In other implementations, the cell layout is a custom designed cell, which is separate from the standard cell layout library.
• a computer accessible storage medium includes any storage media accessible by a computer during use to provide instructions and/or data to the computer.
• a computer accessible storage medium includes storage media such as magnetic or optical media, e.g., disk (fixed or removable), tape, CD-ROM, or DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, or Blu-Ray.
• Storage media further includes volatile or non-volatile memory media such as RAM (e.g. synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low-power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), static RAM (SRAM), etc ), ROM, Flash memory, non-volatile memory (e.g. Flash memory) accessible via a peripheral interface such as the Universal Serial Bus (USB) interface, etc.
• SDRAM synchronous dynamic RAM
• DDR double data rate SDRAM
• LPDDR2, etc. low-power DDR
• RDRAM Rambus DRAM
• SRAM static RAM
• ROM Flash memory
• non-volatile memory e.g. Flash memory
• USB
• program instructions include behavioral -level descriptions or register-transfer level (RTL) descriptions of the hardware functionality in a high level programming language such as C, or a design language (HDL) such as Verilog, VHDL, or database format such as GDS II stream format (GDSII).
• RTL register-transfer level
• HDL design language
• GDSII database format
• the description is read by a synthesis tool, which synthesizes the description to produce a netlist including a list of gates from a synthesis library.
• the netlist includes a set of gates, which also represent the functionality of the hardware including the system.
• the netlist is then placed and routed to produce a data set describing geometric shapes to be applied to masks.
• the masks are then used in various semiconductor fabrication steps to produce a semiconductor circuit or circuits corresponding to the system.
• the instructions on the computer accessible storage medium are the netlist (with or without the synthesis library) or the data set, as desired. Additionally, the instructions are utilized for purposes of emulation by a hardware based type emulator from such vendors as Cadence®, EVE®, and Mentor Graphics®.

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