CN112166498B - 单元中的有源区上方的栅极触点 - Google Patents

单元中的有源区上方的栅极触点

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Publication number
CN112166498B
CN112166498B CN201980035109.XA CN201980035109A CN112166498B CN 112166498 B CN112166498 B CN 112166498B CN 201980035109 A CN201980035109 A CN 201980035109A CN 112166498 B CN112166498 B CN 112166498B
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CN
China
Prior art keywords
gate
metal
contacts
source
gate extension
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Application number
CN201980035109.XA
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English (en)
Chinese (zh)
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CN112166498A (zh
Inventor
理查德·T·舒尔茨
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of CN112166498A publication Critical patent/CN112166498A/zh
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Publication of CN112166498B publication Critical patent/CN112166498B/zh
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CN201980035109.XA 2018-05-25 2019-03-27 单元中的有源区上方的栅极触点 Active CN112166498B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/989,604 2018-05-25
US15/989,604 US10818762B2 (en) 2018-05-25 2018-05-25 Gate contact over active region in cell
PCT/US2019/024364 WO2019226229A1 (en) 2018-05-25 2019-03-27 Gate contact over active region in cell

Publications (2)

Publication Number Publication Date
CN112166498A CN112166498A (zh) 2021-01-01
CN112166498B true CN112166498B (zh) 2025-08-08

Family

ID=66102798

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980035109.XA Active CN112166498B (zh) 2018-05-25 2019-03-27 单元中的有源区上方的栅极触点

Country Status (6)

Country Link
US (2) US10818762B2 (https=)
EP (1) EP3803962A1 (https=)
JP (1) JP7572948B2 (https=)
KR (2) KR20210002649A (https=)
CN (1) CN112166498B (https=)
WO (1) WO2019226229A1 (https=)

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US11152347B2 (en) * 2018-04-13 2021-10-19 Qualcomm Incorporated Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections
US10818762B2 (en) * 2018-05-25 2020-10-27 Advanced Micro Devices, Inc. Gate contact over active region in cell
US10846327B2 (en) * 2018-11-02 2020-11-24 A9.Com, Inc. Visual attribute determination for content selection
EP3723127A1 (en) * 2019-04-10 2020-10-14 IMEC vzw A standard cell device and a method for forming an interconnect structure for a standard cell device
US10796061B1 (en) * 2019-08-29 2020-10-06 Advanced Micro Devices, Inc. Standard cell and power grid architectures with EUV lithography
US11362090B2 (en) 2020-01-31 2022-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having buried logic conductor type of complementary field effect transistor, method of generating layout diagram and system for same
DE102020125647A1 (de) * 2020-01-31 2021-08-05 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung mit Komplementärfeldeffekttransistor des Typs mit vergrabenenen Logikleitern, Layout-Diagramm-Herstellungsverfahren und System dafür
US12205897B2 (en) 2021-09-23 2025-01-21 Advanced Micro Devices, Inc. Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells

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DE102004063926B4 (de) 2004-03-24 2017-10-19 Infineon Technologies Ag Konfigurierbare Treiberzelle eines logischen Zellenfeldes
US7761831B2 (en) 2005-12-29 2010-07-20 Mosaid Technologies Incorporated ASIC design using clock and power grid standard cell
JP4322888B2 (ja) 2006-06-01 2009-09-02 エルピーダメモリ株式会社 半導体装置
US7984395B2 (en) 2008-01-17 2011-07-19 Synopsys, Inc. Hierarchical compression for metal one logic layer
JP5410082B2 (ja) 2008-12-12 2014-02-05 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US8533641B2 (en) 2011-10-07 2013-09-10 Baysand Inc. Gate array architecture with multiple programmable regions
US8716124B2 (en) * 2011-11-14 2014-05-06 Advanced Micro Devices Trench silicide and gate open with local interconnect with replacement gate process
KR20130070252A (ko) 2011-12-19 2013-06-27 에스케이하이닉스 주식회사 반도체 메모리 소자의 스페어 로직 구현방법 및 그 구조
EP2803077A4 (en) * 2012-01-13 2015-11-04 Tela Innovations Inc CIRCUITS WITH LINEAR FINFET STRUCTURES
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Also Published As

Publication number Publication date
JP2021525974A (ja) 2021-09-27
US10818762B2 (en) 2020-10-27
KR20240033144A (ko) 2024-03-12
US20210028288A1 (en) 2021-01-28
WO2019226229A1 (en) 2019-11-28
US11424336B2 (en) 2022-08-23
JP7572948B2 (ja) 2024-10-24
US20190363167A1 (en) 2019-11-28
CN112166498A (zh) 2021-01-01
EP3803962A1 (en) 2021-04-14
KR20210002649A (ko) 2021-01-08
KR102876341B1 (ko) 2025-10-27

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