JPWO2018181417A1 - パワーモジュールおよびその製造方法 - Google Patents
パワーモジュールおよびその製造方法 Download PDFInfo
- Publication number
- JPWO2018181417A1 JPWO2018181417A1 JP2019509940A JP2019509940A JPWO2018181417A1 JP WO2018181417 A1 JPWO2018181417 A1 JP WO2018181417A1 JP 2019509940 A JP2019509940 A JP 2019509940A JP 2019509940 A JP2019509940 A JP 2019509940A JP WO2018181417 A1 JPWO2018181417 A1 JP WO2018181417A1
- Authority
- JP
- Japan
- Prior art keywords
- layer
- power module
- semiconductor device
- thick copper
- aluminum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 246
- 239000010949 copper Substances 0.000 claims abstract description 226
- 229910052802 copper Inorganic materials 0.000 claims abstract description 200
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 199
- 239000000758 substrate Substances 0.000 claims abstract description 135
- 229910052751 metal Inorganic materials 0.000 claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 63
- 238000009792 diffusion process Methods 0.000 claims abstract description 59
- 238000007747 plating Methods 0.000 claims abstract description 35
- 229910052782 aluminium Inorganic materials 0.000 claims description 160
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 160
- 238000000034 method Methods 0.000 claims description 89
- 238000003825 pressing Methods 0.000 claims description 43
- 238000010438 heat treatment Methods 0.000 claims description 40
- 239000000919 ceramic Substances 0.000 claims description 38
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 29
- 229910052709 silver Inorganic materials 0.000 claims description 29
- 239000004332 silver Substances 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 19
- 150000001875 compounds Chemical class 0.000 claims description 17
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 239000007921 spray Substances 0.000 claims description 10
- 238000004544 sputter deposition Methods 0.000 claims description 8
- 238000007751 thermal spraying Methods 0.000 claims description 5
- 238000010304 firing Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000007790 solid phase Substances 0.000 abstract description 14
- 239000010410 layer Substances 0.000 description 500
- 238000010586 diagram Methods 0.000 description 76
- 230000000052 comparative effect Effects 0.000 description 33
- 239000012071 phase Substances 0.000 description 28
- 230000035882 stress Effects 0.000 description 28
- 210000000746 body region Anatomy 0.000 description 26
- 239000000523 sample Substances 0.000 description 21
- 238000012986 modification Methods 0.000 description 19
- 230000004048 modification Effects 0.000 description 19
- 238000012360 testing method Methods 0.000 description 19
- 230000006866 deterioration Effects 0.000 description 18
- 229920005989 resin Polymers 0.000 description 15
- 239000011347 resin Substances 0.000 description 15
- 238000004088 simulation Methods 0.000 description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 12
- 238000005096 rolling process Methods 0.000 description 11
- 238000001816 cooling Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 8
- 238000005476 soldering Methods 0.000 description 8
- 238000005304 joining Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 238000001000 micrograph Methods 0.000 description 5
- 230000002040 relaxant effect Effects 0.000 description 5
- 230000008646 thermal stress Effects 0.000 description 5
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 description 4
- 102100029563 Somatostatin Human genes 0.000 description 4
- 239000000498 cooling water Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 240000004050 Pentaglottis sempervirens Species 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000006664 bond formation reaction Methods 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- 230000020169 heat generation Effects 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000003325 tomography Methods 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052770 Uranium Inorganic materials 0.000 description 1
- 241000905137 Veronica schmidtiana Species 0.000 description 1
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/08245—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/275—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
- H01L2224/27505—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29005—Structure
- H01L2224/29006—Layer connector larger than the underlying bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/802—Applying energy for connecting
- H01L2224/80201—Compression bonding
- H01L2224/80203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/80399—Material
- H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/80417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/80424—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/80399—Material
- H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/80438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/80439—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/80399—Material
- H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/80438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/80444—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/80399—Material
- H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/80463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/80464—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80801—Soldering or alloying
- H01L2224/8082—Diffusion bonding
- H01L2224/8083—Solid-solid interdiffusion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83439—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83444—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/83464—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/8382—Diffusion bonding
- H01L2224/8383—Solid-solid interdiffusion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
(厚銅基板例)
実施の形態に係るパワーモジュール1に適用可能な厚銅基板2の模式的断面構造は、図1(a)に示すように表され、実施の形態に係るパワーモジュール1に適用可能な別の厚銅基板2の模式的断面構造は、図1(b)に示すように表される。
第1の実施の形態に係るパワーモジュール1の模式的断面構造は、図2(a)に示すように表され、第1の実施の形態の変形例に係るパワーモジュール1の模式的断面構造は、図2(b)に示すように表される。
第1の実施の形態の変形例に係るパワーモジュール1は、図2(b)に示すように、絶縁シート層16上に配置された第2アルミニウム緩和層24Dを備える。第2厚銅層18は、第2アルミニウム緩和層24D上に圧延接着などにより接合可能である。その他の構成は、第1の実施の形態に係るパワーモジュール1と同様である。
第2の実施の形態に係るパワーモジュール1の模式的断面構造は、図3(a)に示すように表され、第2の実施の形態の変形例に係るパワーモジュール1の模式的断面構造は、図3(b)に示すように表される。
第2の実施の形態の変形例に係るパワーモジュール1は、図3(b)に示すように、絶縁シート層16上に配置された第2アルミニウム緩和層24Dを備える。第2厚銅層18は、第2アルミニウム緩和層24D上に圧延接着などにより接合可能である。その他の構成は、第2の実施の形態に係るパワーモジュール1と同様である。
第3の実施の形態に係るパワーモジュール1の模式的断面構造は、図4(a)に示すように表され、第3の実施の形態の変形例に係るパワーモジュール1の模式的断面構造は、図4(b)に示すように表される。
第3の実施の形態の変形例に係るパワーモジュール1は、図4(b)に示すように、絶縁シート層16上に配置された第2アルミニウム緩和層24Dを備える。第2厚銅層18は、第2アルミニウム緩和層24D上に圧延接着などにより接合可能である。その他の構成は、第3の実施の形態に係るパワーモジュール1と同様である。
比較例1に係るパワーモジュール1Aの模式的断面構造(厚銅+絶縁層構造例)は、図5(a)に示すように表される。
実施の形態に係るパワーモジュールのプレス加工工程の説明図であって、半導体デバイス22をアルミニウム緩和層24U上に搭載する工程は図6(a)に示すように表され、加熱・加圧工程は図6(b)に示すように表される。また、加熱・加圧工程後の形状であって、半導体デバイス22がアルミニウム緩和層24Uに一部埋め込まれた形状の説明図は、図6(c)に示すように表される。図6においては、第1の実施の形態や第3の実施の形態における加熱・加圧工程により、半導体デバイス22がアルミニウム緩和層24Uに一部埋め込まれる構造を説明しており、メッキ層30やAg焼成層20は、図示を省略している。
第1〜第3の実施の形態に係るパワーモジュールにおいて、熱サイクルテストにおける温度プロファイル例は、図8に示すように表される。すなわち、図8に示すように、−50℃〜200℃の範囲で熱サイクルテストを行った。熱サイクルの1サイクルの周期は80分であり、その内訳は、マイナス50℃で30分、マイナス50℃からプラス200℃までの昇温時間10分、プラス200℃で30分、プラス200℃からマイナス50℃までの冷却時間10分である(図8参照)。
超音波探傷装置(SAT:Scanning Acoustic Tomography)による内部観察のための実験系の模式的説明図は、図9(a)に示すように表され、内部観察された画像の模式図は、図9(b)に示すように表され、サンプルの模式的断面構造は、図9(c)に示すように表される。図9(a)においては、厚銅層18Aと、厚銅層18A上にAg焼成層20を接合層として形成された半導体デバイス22とを備える比較例に係るパワーモジュールに対して、超音波プローブ29を走査して内部観察するためのSAT実験系の模式的構造が示されている。
厚銅層18A上にAg焼成層20を接合層として半導体デバイス22を搭載した比較例1に係るパワーモジュールの初期状態のSAT画像例は、図10(a)に示すように表され、図10(a)を説明するための線図は、図10(b)に示すように表される。また、サンプルの模式的断面構造は、図10(c)に示すように表される。
図11(a)および図11(b)に示すように、200サイクル後(−50℃〜+300℃、30分)の結果より、厚銅基板では、接合層の劣化が顕著である。
セラミックス基板17と、セラミックス基板17の上下にアルミニウム層24A・24Bを形成したDBA(Direct Bonded Aluminum)基板を用い、DBA基板上に半導体デバイス22を搭載したパワーモジュールの初期状態のSAT画像例は、図12(a)に示すように表され、図12(a)を説明するための線図は、図12(b)に示すように表される。また、サンプルの模式的断面構造は、図12(c)に示すように表される。DBA基板上に半導体デバイス22を搭載したパワーモジュール構造は、アルミニウム層24A・24Bを備えるセラミックス基板17を用いており、実施の形態に係るパワーモジュールと同様の緩和効果が見られる。
セラミックス基板17と、セラミックス基板17の上下に厚銅層14B・18Bを形成した厚銅化セラミックス基板を用い、厚銅層18B上にAg焼成層20を介して半導体デバイス22を搭載した比較例2に係るパワーモジュールにおいて、50サイクル(−50℃〜+200℃)後のCu/SiNセラミックス間の劣化を示すSAT画像例は、図14(a)に示すように表され、図14(a)を説明するための線図は、図14(b)に示すように表される。また、サンプルの模式的断面構造は、図14(c)に示すように表される。
第1の実施の形態に係るパワーモジュールにおいて、アルミニウム緩和層24Uの厚さtAをパラメータとした熱抵抗RTj-wと第2厚銅層18の厚さt1の関係のシミュレーション結果は、図18に示すように表される。また、第1の実施の形態に係るパワーモジュールにおいて、アルミニウム緩和層24Uの厚さtAおよび第2厚銅層18の厚さt1のシミュレーション条件を説明するための図は、図19に示すように表され、熱抵抗RTj-wのシミュレーション条件を説明するための図は、図20に示すように表される。尚、図19においては、メッキ層30は図示を省略している。また、図20においては、第3の実施の形態に係るパワーモジュール1を水冷式の冷却器10に搭載する例を図示しているが、第1〜第2の実施の形態に係るパワーモジュール1も図20と同様に、水冷式の冷却器10に搭載可能である。
固相拡散接合を形成後の半導体デバイス22のアルミニウム緩和層24への食い込みに関して、プロセス時の加圧力を変更してDBA基板上に接合したサンプルを例として説明する。
(構成例1)
冷却器10に搭載可能な第3の実施の形態に係るパワーモジュール(構成例1)は、図20に示すように、冷却器10と、冷却器10上に配置された第1サーマルコンパウンド層12THとを備える。ここで、厚銅基板2は、冷却器10上に第1サーマルコンパウンド層12THを介して配置される。その他の構成は、図4(a)に示す第3の実施の形態に係るパワーモジュールと同様である。また、第1サーマルコンパウンド層12THの代わりに、半田層、銀焼成層若しくは拡散接合層を備え、厚銅基板2は、冷却器10上に半田層、銀焼成層若しくは拡散接合層のいずれかを介して配置されていても良い。
冷却器10に搭載可能な第3の実施の形態に係るパワーモジュール(構成例2)は、図25に示すように、冷却器10と、冷却器10上に配置された第1サーマルコンパウンド層12THとを備える。ここで、厚銅基板2は、冷却器10上に第1サーマルコンパウンド層12THを介して配置される。その他の構成は、図4(a)に示す第3の実施の形態に係るパワーモジュールと同様である。
冷却器10に搭載可能な実施の形態に係るパワーモジュール(構成例3)は、図26に示すように、冷却器10と、冷却器10上に配置された絶縁シート16とを備える。ここで、第2厚銅層18は、冷却器10上に絶縁シート16を介して配置される。ここで、構成例3は、図26に示すように、厚銅基板2として、第2厚銅層18を用いる例に対応している。その他の構成は、図4(a)に示す第3の実施の形態に係るパワーモジュールと同様である。
冷却器10に搭載可能な実施の形態に係るパワーモジュール(構成例4)は、図27に示すように、冷却器10と、冷却器10上に配置された絶縁基板2Bとを備える。ここで、絶縁基板2Bは、冷却器10上に第1サーマルコンパウンド層12THを介して配置される。
実施の形態に係るパワーモジュールの製造方法であって、Al/Cu材の製造工程は図28(a)に示すように表され、絶縁シート貼付け工程は図28(b)に示すように表され、半導体デバイス接合形成工程は図28(c)に示すように表され、樹脂モールド形成工程は図28(d)に示すように表される。図28においては、第1の実施の形態や第3の実施の形態における加熱・加圧工程により、半導体デバイス22がアルミニウム緩和層24Uに一部埋め込まれる構造を説明しており、メッキ層30やAg焼成層20は、図示を省略している。
(ワンインワン構成)
実施の形態に係るパワーモジュール1であって、1 in 1モジュールの模式的平面パターン構成は図30(a)に示すように表され、図30(a)のI−I線に沿う模式的断面構造は図30(b)に示すように表される。更に、実施の形態に係るパワーモジュールであって、図30(a)および図30(b)に対応する1 in 1モジュールの模式的鳥瞰構成は、図31に示すように表される。
実施の形態に係るパワーモジュールであって、2 in 1モジュールの模式的平面パターン構成は図34に示すように表され、模式的鳥瞰構成は図35に示すように表される。
実施の形態に係るパワーモジュールであって、2 in 1モジュール100のSiC MOSFETの模式的回路表現は、図36(a)に示すように表され、2 in 1モジュール100のIGBTの模式的回路表現は、図36(b)に示すように表される。
実施の形態に係るパワーモジュールに適用可能な半導体デバイスQ1・Q4の例であって、ソースパッド電極SPD、ゲートパッド電極GPDを含むSiC MOSFET130Aの模式的断面構造は、図37に示すように表される。
実施の形態に係るパワーモジュールに適用可能な半導体デバイスの例であって、SiC DIMOSFET130Cの模式的断面構造は、図39に示すように表される。
実施の形態に係るパワーモジュールに適用可能な半導体デバイスの例であって、SiC TMOSFET130Dの模式的断面構造は、図40に示すように表される。
実施の形態に係るパワーモジュールを用いて構成した3相交流インバータ40Aの回路構成において、半導体デバイスとしてSiC MOSFETを適用し、電源端子PL・接地端子NL間にスナバコンデンサCを接続した回路構成例は、図41(a)に示すように表される。同様に、半導体デバイスとしてIGBTを適用し、電源端子PL・接地端子NL間にスナバコンデンサCを接続した3相交流インバータ40Bの回路構成例は、図41(b)に示すように表される。
次に、図42を参照して、半導体デバイスとしてSiC MOSFETを適用した3相交流インバータ42Bについて説明する。
<インサート金属を入れない例>
拡散接合技術を適用する一実施の形態に係るパワーモジュールの製造方法の説明図であって、拡散接合形成前のSiC半導体デバイス22の裏面近傍の模式的断面構造は、図44(a)に示すように表され、拡散接合形成前の厚銅基板2の表面近傍の模式的断面構造は、図44(b)に示すように表される。
拡散接合技術を適用する一実施の形態に係るパワーモジュールの拡散接合近傍の断面構造のSEM写真例は、図46(a)に示すように表され、図46(a)を説明するための線図は、図46(b)に示すように表される。
上述のインサート金属をいれない例において、SiC半導体デバイス22の裏面電極134の最下面が銀層124で、厚銅基板2の表面電極132の最上面も銀層122の場合、銀層124と銀層122間に銀層からなるインサート金属を更に配置して、加熱・加圧プロセスを実施しても良い。SiC半導体デバイス22の裏面電極134の最下面と、厚銅基板2の表面電極132の最上面を同じ金属にして、インサート金属も同じものにすることで、良好な拡散接合を形成可能である。インサート金属として銀層を適用した場合も図46(a)および図46(b)と同様の銀層124−インサート金属(銀層)−銀層122が一体化された拡散接合が形成可能である。
本技術を適用する一実施の形態に係るパワーモジュールの厚銅基板の表面近傍の模式的断面図(その1)は図48(a)に示すように表され、厚銅基板の表面近傍の模式的断面図(その2)は図48(b)に示すように表される。
拡散接合技術を適用する一実施の形態に係るパワーモジュールの熱サイクルテストに用いた基板構造の模式的断面構造は、図49に示すように表される。
上記のように、いくつかの実施の形態について記載したが、開示の一部をなす論述および図面は例示的なものであり、限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例および運用技術が明らかとなろう。
2,2A…厚銅基板
2B…絶縁基板
10…冷却器
10W…冷却水
12…半田層
12TH…第1サーマルコンパウンド層
14、14B…第1厚銅層(Cu層)
16…絶縁シート層
16TH……第2サーマルコンパウンド層
17…セラミックス基板
18、18B…第2厚銅層(Cu層)
20…Ag焼成層
22、QA、QB、Q、Q1〜Q6…半導体デバイス(SiC MOSFET)
24A、24B…アルミニウム(Al)層
24U…応力緩和金属層(第1アルミニウム緩和層)
24D…応力緩和金属層(第2アルミニウム緩和層)
26…プレス板
29…超音波プローブ
30、30U、30D…メッキ層
40A、40B、42A、42B…3相交流インバータ
50…1 in 1モジュール
100…2 in 1モジュール
122、123、124…銀層
120、128…ニッケル層
126…金層
130…チタン層
132…表面電極
134…裏面電極
200…パワーモジュール部
300…樹脂層
t1…第2厚銅層の厚さ
tA…応力緩和金属層(第1アルミニウム緩和層)の厚さ
tD…半導体デバイスの厚さ
tB…第1アルミニウム緩和層の加圧厚さ
SD…半導体デバイスの側壁部と台形形状のアルミニウム緩和層表面との距離
PA…加圧圧力
RTj-w…熱抵抗
P…正側電力端子
N…負側電力端子
O、U、V、W…出力端子
GT1、GT4…ゲート端子
ST…ソース端子
DT…ドレイン端子
GWA、GWB、GW1、GW4…ゲートボンディングワイヤ
SWA、SWB、SW1、SW4、SWO、SWN…ソースボンディングワイヤ
GP、GP1、GP4…ゲート信号用配線パターン
SP、SP1、SP4…ソース信号用配線パターン
BR1、BR2…埋め込み部
Claims (39)
- 平板状の厚銅基板と、
前記厚銅基板上に配置された導電性の応力緩和金属層と、
前記応力緩和金属層上に配置された半導体デバイスと
を備え、前記半導体デバイスは、前記応力緩和金属層と接合していることを特徴とするパワーモジュール。 - 前記応力緩和金属層上に配置されたメッキ層を備え、
前記半導体デバイスは、前記応力緩和金属層と前記メッキ層を介して接合していることを特徴とする請求項1に記載のパワーモジュール。 - 前記応力緩和金属層上に配置されたAg焼成層を備え、
前記半導体デバイスは、前記Ag焼成層を介して、前記応力緩和金属層と接合していることを特徴とする請求項1に記載のパワーモジュール。 - 前記メッキ層上に配置されたAg焼成層を備え、
前記半導体デバイスは、前記Ag焼成層および前記メッキ層を介して、前記応力緩和金属層と接合していることを特徴とする請求項2に記載のパワーモジュール。 - 前記半導体デバイスの一部は、前記応力緩和金属層または前記メッキ層に食い込んで固着していることを特徴とする請求項2または4に記載のパワーモジュール。
- 前記半導体デバイスと前記応力緩和金属層または前記メッキ層との接合面は、一体化していることを特徴とする請求項5に記載のパワーモジュール。
- 前記半導体デバイスは、前記応力緩和金属層または前記メッキ層に前記半導体デバイスの厚さの1/3〜1/2食い込んで接合していることを特徴とする請求項6に記載のパワーモジュール。
- 前記応力緩和金属層は、第1アルミニウム緩和層を備えることを特徴とする請求項1〜7のいずれか1項に記載のパワーモジュール。
- 前記厚銅基板は、
第1厚銅層と、
前記第1厚銅層上に配置された第2厚銅層と
を備え、前記応力緩和金属層は、前記第2厚銅層上に配置されることを特徴とする請求項1〜8のいずれか1項に記載のパワーモジュール。 - 前記第1厚銅層上に配置された絶縁シート層を備え、
前記第2厚銅層は、前記絶縁シート層上に配置されることを特徴とする請求項9に記載のパワーモジュール。 - 前記絶縁シート層上に配置された第2アルミニウム緩和層を備え、
前記第2厚銅層は、前記第2アルミニウム緩和層上に圧延接着されていることを特徴とする請求項9または10に記載のパワーモジュール。 - 前記絶縁シート層上に配置された第2アルミニウム緩和層を備え、
前記第2厚銅層は、前記第2アルミニウム緩和層上にスパッタリング技術、コールドスプレー技術若しくは溶射技術を用いて接着されていることを特徴とする請求項9または10に記載のパワーモジュール。 - 冷却器と、
前記冷却器上に配置された第1サーマルコンパウンド層と
を備え、前記厚銅基板は、前記冷却器上に前記第1サーマルコンパウンド層を介して配置されることを特徴とする請求項9〜11のいずれか1項に記載のパワーモジュール。 - 冷却器と、前記冷却器上に配置された半田層、銀焼成層若しくは拡散接合層とを備え、前記厚銅基板は、前記冷却器上に前記半田層、前記銀焼成層若しくは前記拡散接合層のいずれかを介して配置されることを特徴とする請求項9〜11のいずれか1項に記載のパワーモジュール。
- 前記厚銅基板を挟んで、前記第1アルミニウム緩和層に対向して配置される第2アルミニウム緩和層を備えることを特徴とする請求項8に記載のパワーモジュール。
- 冷却器と、
前記冷却器上に配置された絶縁シートと
を備え、前記厚銅基板は、前記絶縁シート上に配置されることを特徴とする請求項15に記載のパワーモジュール。 - 絶縁基板と、
前記絶縁基板上に配置された第2サーマルコンパウンド層と
を備え、前記厚銅基板は、前記第2サーマルコンパウンド層上に配置されることを特徴とする請求項15に記載のパワーモジュール。 - 冷却器と、
前記冷却器上に配置された第2サーマルコンパウンド層と
を備え、前記厚銅基板は、前記冷却器上に前記第2サーマルコンパウンド層を介して配置されることを特徴とする請求項17に記載のパワーモジュール。 - 前記絶縁基板は、DBC基板、DBA基板、AMB基板、若しくはセラミックス基板のいずれかを備えることを特徴とする請求項17または18に記載のパワーモジュール。
- 前記冷却器は、水冷式若しくは空冷式であり、車載機器に用いられることを特徴とする請求項13、14、16、若しくは18のいずれか1項に記載のパワーモジュール。
- 前記第1アルミニウム緩和層の厚さは、0.01mm〜0.5mmの範囲を備えることを特徴とする請求項8に記載のパワーモジュール。
- 前記第2厚銅層の厚さは、1mm〜3mmの範囲を備えることを特徴とする請求項9〜13のいずれか1項に記載のパワーモジュール。
- 平板状の第1厚銅層と、
前記第1厚銅層上に配置された絶縁シート層と、
前記絶縁シート層上に配置され、パターン形成された第2厚銅層と、
前記第2厚銅層上に配置された第1アルミニウム緩和層と、
前記第1アルミニウム緩和層上に配置された半導体デバイスと
を備え、前記半導体デバイスは、前記第1アルミニウム緩和層と接合していることを特徴とするパワーモジュール。 - 前記第1アルミニウム緩和層上に配置されたメッキ層を備え、
前記半導体デバイスは、前記メッキ層を介して、前記第1アルミニウム緩和層と接合していることを特徴とする請求項23に記載のパワーモジュール。 - 前記第1アルミニウム緩和層上に配置されたAg焼成層を備え、
前記半導体デバイスは、前記Ag焼成層を介して、前記第1アルミニウム緩和層と接合していることを特徴とする請求項23に記載のパワーモジュール。 - 前記メッキ層上に配置されたAg焼成層を備え、
前記半導体デバイスは、前記Ag焼成層および前記メッキ層を介して、前記第1アルミニウム緩和層と接合していることを特徴とする請求項24に記載のパワーモジュール。 - 前記半導体デバイスの一部は、前記メッキ層または前記第1アルミニウム緩和層に食い込んで固着していることを特徴とする請求項24または26に記載のパワーモジュール。
- 前記半導体デバイスと前記メッキ層または前記第1アルミニウム緩和層との接合面は、一体化していることを特徴とする請求項27に記載のパワーモジュール。
- 前記半導体デバイスは、前記メッキ層または前記第1アルミニウム緩和層に前記半導体デバイスの厚さの1/3〜1/2食い込んで接合していることを特徴とする請求項28に記載のパワーモジュール。
- 前記絶縁シート層上に配置された第2アルミニウム緩和層を備え、
前記第2厚銅層は、前記第2アルミニウム緩和層上に圧延接着されていることを特徴とする請求項23〜29のいずれか1項に記載のパワーモジュール。 - 前記絶縁シート層上に配置された第2アルミニウム緩和層を備え、
前記第2厚銅層は、前記第2アルミニウム緩和層上にスパッタリング技術、コールドスプレー技術若しくは溶射技術を用いて接着されていることを特徴とする請求項23〜29のいずれか1項に記載のパワーモジュール。 - 前記半導体デバイスは、その上面にソース電極またはエミッタ電極とゲート電極が形成され、その下面にドレイン電極またはコレクタ電極が形成されたFETまたはIGBTであり、
前記絶縁シート層上に配置され、前記第2厚銅層と同一材料によりパターン形成され、前記ゲート電極に電気的に接続されるゲート信号用配線パターンおよび前記ソース電極または前記エミッタ電極に電気的に接続されるソースまたはエミッタ信号用配線パターンとを備えることを特徴とする請求項23〜31のいずれか1項に記載のパワーモジュール。 - 前記半導体デバイスは複数のチップを並列接続した構成を備えることを特徴とする請求項32に記載のパワーモジュール。
- 前記半導体デバイスは、Si系IGBT、Si系MOSFET、SiC系MOSFET、SiC系IGBT、GaN系FETのいずれか、またはこれらのうちの異なる複数を備えることを特徴とする請求項1〜33のいずれか1項に記載のパワーモジュール。
- 前記半導体デバイスを用いて、ワンインワンモジュール、ツーインワンモジュール、フォーインワンモジュール、シックスインワンモジュール、セブンインワンモジュール、エイトインワンモジュール、トゥエルブインワンモジュール、またはフォーティーンインワンモジュールのいずれかを構成する請求項1〜34のいずれか1項に記載のパワーモジュール。
- 前記半導体デバイスを第1電源と第2電源との間に直列に接続し、直列接続された前記半導体デバイスの接続点を出力とするスイッチング回路を複数用いると共に、前記半導体デバイスの各ゲートを個別に制御してインバータ回路装置またはコンバータ回路を構成することを特徴とする請求項35に記載のパワーモジュール。
- 第2厚銅層上に第1アルミニウム緩和層を形成する工程と、
第1厚銅層上に絶縁シート層を介して前記第2厚銅層を配置する工程と、
前記第1アルミニウム緩和層上に半導体デバイスを配置し、加熱しながら加圧する加熱・加圧プロセスにより前記半導体デバイスを前記第1アルミニウム緩和層と接合する工程と、
前記半導体デバイスの電極と外部端子とを接続する工程と
を有することを特徴とするパワーモジュールの製造方法。 - 第2厚銅層上に第1アルミニウム緩和層を形成する工程と、
前記第1アルミニウム緩和層上に半導体デバイスを配置し、加熱しながら加圧する加熱・加圧プロセスにより前記半導体デバイスを前記第1アルミニウム緩和層と接合する工程と、
第1厚銅層上に絶縁シート層を介して前記第2厚銅層を配置する工程と、
前記半導体デバイスの電極と外部端子とを接続する工程と
を有することを特徴とするパワーモジュールの製造方法。 - 前記加熱・加圧プロセスの加熱温度は、300℃〜350℃を備え、加圧圧力は、10MPa〜80MPaを備えることを特徴とする請求項37または38に記載のパワーモジュールの製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017071880 | 2017-03-31 | ||
JP2017071880 | 2017-03-31 | ||
PCT/JP2018/012634 WO2018181417A1 (ja) | 2017-03-31 | 2018-03-28 | パワーモジュールおよびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2018181417A1 true JPWO2018181417A1 (ja) | 2020-02-06 |
JP7125931B2 JP7125931B2 (ja) | 2022-08-25 |
Family
ID=63677727
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019509940A Active JP7125931B2 (ja) | 2017-03-31 | 2018-03-28 | パワーモジュールおよびその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US11171071B2 (ja) |
JP (1) | JP7125931B2 (ja) |
CN (1) | CN110476244B (ja) |
DE (1) | DE112018001769B4 (ja) |
WO (1) | WO2018181417A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7147502B2 (ja) | 2018-11-19 | 2022-10-05 | 三菱電機株式会社 | 半導体装置、電力変換装置および半導体装置の製造方法 |
JP7342371B2 (ja) * | 2019-02-14 | 2023-09-12 | 三菱マテリアル株式会社 | 絶縁回路基板、及び、絶縁回路基板の製造方法 |
JP7319808B2 (ja) | 2019-03-29 | 2023-08-02 | ローム株式会社 | 半導体装置および半導体パッケージ |
WO2024024371A1 (ja) * | 2022-07-27 | 2024-02-01 | ローム株式会社 | 半導体装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013191640A (ja) * | 2012-03-12 | 2013-09-26 | Mitsubishi Materials Corp | パワーモジュール用基板及びその製造方法 |
JP2015070063A (ja) * | 2013-09-27 | 2015-04-13 | 三菱マテリアル株式会社 | パワーモジュール用基板の製造方法 |
JP2015211125A (ja) * | 2014-04-25 | 2015-11-24 | 三菱マテリアル株式会社 | パワーモジュール用基板及びヒートシンク付パワーモジュール用基板並びにヒートシンク付パワーモジュール |
JP2016103526A (ja) * | 2014-11-27 | 2016-06-02 | トヨタ自動車株式会社 | 半導体装置 |
WO2017130512A1 (ja) * | 2016-01-28 | 2017-08-03 | 三菱電機株式会社 | パワーモジュール |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4993148A (en) * | 1987-05-19 | 1991-02-19 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a circuit board |
DE4315272A1 (de) | 1993-05-07 | 1994-11-10 | Siemens Ag | Leistungshalbleiterbauelement mit Pufferschicht |
JP4595665B2 (ja) | 2005-05-13 | 2010-12-08 | 富士電機システムズ株式会社 | 配線基板の製造方法 |
DE102009033029A1 (de) | 2009-07-02 | 2011-01-05 | Electrovac Ag | Elektronische Vorrichtung |
DE102009045181B4 (de) | 2009-09-30 | 2020-07-09 | Infineon Technologies Ag | Leistungshalbleitermodul |
JP2014072314A (ja) | 2012-09-28 | 2014-04-21 | Toyota Industries Corp | 半導体装置、及び半導体装置の製造方法 |
JP6621076B2 (ja) * | 2013-03-29 | 2019-12-18 | 三菱マテリアル株式会社 | パワーモジュール用基板、ヒートシンク付パワーモジュール用基板及びパワーモジュール |
JP6262968B2 (ja) | 2013-09-09 | 2018-01-17 | Dowaメタルテック株式会社 | 電子部品搭載基板およびその製造方法 |
KR20170073618A (ko) * | 2014-10-16 | 2017-06-28 | 미쓰비시 마테리알 가부시키가이샤 | 냉각기가 장착된 파워 모듈용 기판 및 그 제조 방법 |
CN107112299B (zh) * | 2015-01-29 | 2019-10-01 | 京瓷株式会社 | 电路基板以及电子装置 |
JP2015195415A (ja) | 2015-08-10 | 2015-11-05 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
WO2017206045A1 (en) * | 2016-05-31 | 2017-12-07 | Thomson Licensing | Method and device for providing a backup link |
-
2018
- 2018-03-28 JP JP2019509940A patent/JP7125931B2/ja active Active
- 2018-03-28 WO PCT/JP2018/012634 patent/WO2018181417A1/ja active Application Filing
- 2018-03-28 CN CN201880022963.8A patent/CN110476244B/zh active Active
- 2018-03-28 DE DE112018001769.9T patent/DE112018001769B4/de active Active
-
2019
- 2019-08-15 US US16/541,750 patent/US11171071B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013191640A (ja) * | 2012-03-12 | 2013-09-26 | Mitsubishi Materials Corp | パワーモジュール用基板及びその製造方法 |
JP2015070063A (ja) * | 2013-09-27 | 2015-04-13 | 三菱マテリアル株式会社 | パワーモジュール用基板の製造方法 |
JP2015211125A (ja) * | 2014-04-25 | 2015-11-24 | 三菱マテリアル株式会社 | パワーモジュール用基板及びヒートシンク付パワーモジュール用基板並びにヒートシンク付パワーモジュール |
JP2016103526A (ja) * | 2014-11-27 | 2016-06-02 | トヨタ自動車株式会社 | 半導体装置 |
WO2017130512A1 (ja) * | 2016-01-28 | 2017-08-03 | 三菱電機株式会社 | パワーモジュール |
Also Published As
Publication number | Publication date |
---|---|
JP7125931B2 (ja) | 2022-08-25 |
US20190371695A1 (en) | 2019-12-05 |
WO2018181417A1 (ja) | 2018-10-04 |
CN110476244B (zh) | 2023-11-03 |
CN110476244A (zh) | 2019-11-19 |
DE112018001769T5 (de) | 2019-12-19 |
DE112018001769B4 (de) | 2022-05-05 |
US11171071B2 (en) | 2021-11-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10483216B2 (en) | Power module and fabrication method for the same | |
CN110622301B (zh) | 功率半导体装置及其制造方法 | |
KR102585450B1 (ko) | 브레이징된 전기 전도성 층을 포함하는 칩 캐리어를 구비한 몰딩된 패키지 | |
US9041183B2 (en) | Power module packaging with double sided planar interconnection and heat exchangers | |
JP4635564B2 (ja) | 半導体装置 | |
EP3026701B1 (en) | Power module and manufacturing method thereof | |
JP7125931B2 (ja) | パワーモジュールおよびその製造方法 | |
JP6077773B2 (ja) | パワーモジュール半導体装置 | |
CN108735692B (zh) | 半导体装置 | |
JP6097013B2 (ja) | パワーモジュール半導体装置 | |
WO2015053219A1 (ja) | パワーモジュールおよびその製造方法 | |
EP3026700B1 (en) | Power module and manufacturing method thereof | |
JP2021185615A (ja) | 半導体装置及びパワーモジュール | |
JP2017017283A (ja) | パワーモジュールおよびインバータ装置 | |
JP2014120639A (ja) | パワーモジュール半導体装置 | |
US20180040562A1 (en) | Elektronisches modul und verfahren zu seiner herstellung | |
JP2014120638A (ja) | パワーモジュール半導体装置およびその製造方法 | |
JP2014053403A (ja) | パワーモジュール半導体装置 | |
WO2018047485A1 (ja) | パワーモジュールおよびインバータ装置 | |
JP2004221381A (ja) | 半導体装置 | |
WO2017112863A1 (en) | Metal slugs for double-sided cooling of power module | |
JP2018107481A (ja) | パワーモジュール半導体装置 | |
US11996344B2 (en) | Semiconductor device | |
JP2000228490A (ja) | パワー半導体モジュール | |
US20210407881A1 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20210204 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20220222 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220418 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20220802 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20220815 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7125931 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |