JPWO2018074172A1 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
- Publication number
- JPWO2018074172A1 JPWO2018074172A1 JP2018546216A JP2018546216A JPWO2018074172A1 JP WO2018074172 A1 JPWO2018074172 A1 JP WO2018074172A1 JP 2018546216 A JP2018546216 A JP 2018546216A JP 2018546216 A JP2018546216 A JP 2018546216A JP WO2018074172 A1 JPWO2018074172 A1 JP WO2018074172A1
- Authority
- JP
- Japan
- Prior art keywords
- height
- integrated circuit
- circuit device
- semiconductor integrated
- supply path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 239000002184 metal Substances 0.000 claims abstract description 144
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 10
- 230000000295 complement effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 20
- 230000006641 stabilisation Effects 0.000 description 8
- 238000011105 stabilization Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 2
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11868—Macro-architecture
- H01L2027/11874—Layout specification, i.e. inner core region
- H01L2027/11875—Wiring region, routing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11868—Macro-architecture
- H01L2027/11874—Layout specification, i.e. inner core region
- H01L2027/11879—Data lines (buses)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11868—Macro-architecture
- H01L2027/11874—Layout specification, i.e. inner core region
- H01L2027/11881—Power supply lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
図1は第1実施形態に係る半導体集積回路装置が備えたスタンダードセル1のレイアウト構成例を示す平面図である。図1では、図面横方向をX方向(第1方向に相当)とし、図面縦方向をY方向(第2方向に相当)としている。以降のレイアウト平面図についても同様である。また、図2は図1のスタンダードセル1の回路図である。
図7は第2実施形態に係る半導体集積回路装置が備えたスタンダードセル2の回路図である。図7に示すように、スタンダードセル2は8ビットFF(フリップフロップ)であり、8個のフリップフロップFF0〜FF7を部分回路として備えている。各フリップフロップFF*(*は0〜7の整数)は、入力D*と出力Q*とを備えており、クロック信号CKおよび反転クロック信号NCKを共通信号として受けて動作する。クロック信号CKおよび、クロック信号CKと相補関係にある反転クロック信号NCKは、インバータ52a,52bを備えた共通信号生成回路52によって、スタンダードセル2の外部から供給される原クロック信号CLKを基にして生成される。クロック信号CKおよび反転クロック信号NCKは、それぞれの供給経路を経て、各フリップフロップFF0〜FF7に供給される。
上述した実施形態では、スタンダードセルを構成する部分回路として、セレクタやフリップフロップを例にとって説明を行ったが、本開示において、スタンダードセルを構成する部分回路はこれらに限られるものではない。例えば、ラッチであってもよい。
11,13,15 第1電源配線
12,14 第2電源配線
21,22,31,32 メタル配線
41 ゲート配線
51,52 共通信号生成回路
61,62,71,72 メタル配線
AR1〜AR4 ハイト領域
FF0〜FF7 フリップフロップ(部分回路)
SL0〜SL7 セレクタ(部分回路)
S セレクト信号(共通信号)
NS 反転セレクト信号(共通信号)
CK クロック信号(共通信号)
NCK 反転クロック信号(共通信号)
図1は第1実施形態に係る半導体集積回路装置が備えたスタンダードセル1のレイアウト構成例を示す平面図である。図1では、図面横方向をX方向(第1方向に相当)とし、図面縦方向をY方向(第2方向に相当)としている。以降のレイアウト平面図についても同様である。また、図2は図1のスタンダードセル1の回路図である。
図7は第2実施形態に係る半導体集積回路装置が備えたスタンダードセル2の回路図である。図7に示すように、スタンダードセル2は8ビットFF(フリップフロップ)であり、8個のフリップフロップFF0〜FF7を部分回路として備えている。各フリップフロップFF*(*は0〜7の整数)は、入力D*と出力Q*とを備えており、クロック信号CKおよび反転クロック信号NCKを共通信号として受けて動作する。クロック信号CKおよび、クロック信号CKと相補関係にある反転クロック信号NCKは、インバータ52a,52bを備えた共通信号生成回路52によって、スタンダードセル2の外部から供給される原クロック信号CLKを基にして生成される。クロック信号CKおよび反転クロック信号NCKは、それぞれの供給経路を経て、各フリップフロップFF0〜FF7に供給される。
上述した実施形態では、スタンダードセルを構成する部分回路として、セレクタやフリップフロップを例にとって説明を行ったが、本開示において、スタンダードセルを構成する部分回路はこれらに限られるものではない。例えば、ラッチであってもよい。
11,13,15 第1電源配線
12,14 第2電源配線
21,22,31,32 メタル配線
41 ゲート配線
51,52 共通信号生成回路
61,62,71,72 メタル配線
AR1〜AR4 ハイト領域
FF0〜FF7 フリップフロップ(部分回路)
SL0〜SL7 セレクタ(部分回路)
S セレクト信号(共通信号)
NS 反転セレクト信号(共通信号)
CK クロック信号(共通信号)
NCK 反転クロック信号(共通信号)
Claims (19)
- 所定の回路機能を実現するスタンダードセルを備え、
前記スタンダードセルは、
第1方向にそれぞれ延びており、前記第1方向と垂直をなす第2方向において、第1電源電位を供給する第1電源配線と第2電源電位を供給する第2電源配線とが交互に配置された、N(Nは3以上の整数)本の電源配線と、
1つまたは複数種類の共通信号を受けてそれぞれ動作する、複数のフリップフロップ回路とを備え、
前記複数のフリップフロップ回路は、それぞれ、前記第1電源配線と前記第2電源配線とに挟まれた領域であるM(M=N−1)個のハイト領域のいずれかに、配置されており、
前記M個のハイト領域のうち少なくとも2つである第1ハイト領域は、それぞれ、前記フリップフロップ回路が複数個、配置されており、かつ、前記共通信号のうちの1つである第1共通信号の供給経路を構成するメタル配線が、少なくとも2個の前記フリップフロップ回路に接続されるように配置されている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記スタンダードセルは、前記第1共通信号を生成する共通信号生成回路を備えている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第1共通信号の供給経路は、前記M個のハイト領域のうちの隣り合う2個以上のハイト領域にわたって、前記第2方向に延びるように形成されたゲート配線を含む
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記M個のハイト領域は、前記第1共通信号の供給経路を構成するメタル配線が設けられていないハイト領域を含む
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第1ハイト領域に配置されており、前記第1共通信号の供給経路を構成するメタル配線は、前記第1方向に延びるように形成されている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第1共通信号は、クロック信号である
ことを特徴とする半導体集積回路装置。 - 請求項6記載の半導体集積回路装置において、
前記共通信号は、前記クロック信号の反転信号である反転クロック信号を含み、
前記M個のハイト領域のうち少なくとも1つである第2ハイト領域は、前記フリップフロップ回路が複数個、配置されており、かつ、前記反転クロック信号の供給経路を構成する第2メタル配線が、少なくとも2個の前記フリップフロップ回路に接続されるように配置されている
ことを特徴とする半導体集積回路装置。 - 請求項7記載の半導体集積回路装置において、
前記第2ハイト領域は、前記第1ハイト領域と異なるハイト領域である
ことを特徴とする半導体集積回路装置。 - 請求項8記載の半導体集積回路装置において、
前記M個のハイト領域は、前記第1ハイト領域と前記第2ハイト領域とが、前記第2方向において交互に配置されている
ことを特徴とする半導体集積回路装置。 - 所定の回路機能を実現するスタンダードセルを備え、
前記スタンダードセルは、
第1方向にそれぞれ延びており、前記第1方向と垂直をなす第2方向において、第1電源電位を供給する第1電源配線と第2電源電位を供給する第2電源配線とが交互に配置された、N(Nは3以上の整数)本の電源配線と、
互いに同一の機能を持ち、かつ、1つまたは複数種類の共通信号を受けてそれぞれ動作する、複数の部分回路とを備え、
前記複数の部分回路は、それぞれ、前記第1電源配線と前記第2電源配線とに挟まれた領域であるM(M=N−1)個のハイト領域のいずれかに、配置されており、
前記M個のハイト領域のうち少なくとも2つである第1ハイト領域は、それぞれ、前記部分回路が複数個、配置されており、かつ、前記共通信号のうちの1つである第1共通信号の供給経路を構成するメタル配線が、少なくとも2個の前記部分回路に接続されるように配置されている
ことを特徴とする半導体集積回路装置。 - 請求項10記載の半導体集積回路装置において、
前記スタンダードセルは、前記第1共通信号を生成する共通信号生成回路を備えている
ことを特徴とする半導体集積回路装置。 - 請求項10記載の半導体集積回路装置において、
前記スタンダードセルは、前記第1共通信号を、前記スタンダードセルの外部から受ける
ことを特徴とする半導体集積回路装置。 - 請求項10記載の半導体集積回路装置において、
前記第1共通信号の供給経路は、前記M個のハイト領域のうちの隣り合う2個以上のハイト領域にわたって、前記第2方向に延びるように形成されたゲート配線を含む
ことを特徴とする半導体集積回路装置。 - 請求項10記載の半導体集積回路装置において、
前記M個のハイト領域は、前記第1共通信号の供給経路を構成するメタル配線が設けられていないハイト領域を含む
ことを特徴とする半導体集積回路装置。 - 請求項10記載の半導体集積回路装置において、
前記共通信号は、前記第1共通信号と相補関係にある第2共通信号を含み、
前記M個のハイト領域のうち少なくとも1つである第2ハイト領域は、前記部分回路が複数個、配置されており、かつ、前記第2共通信号の供給経路を構成するメタル配線が、少なくとも2個の前記部分回路に接続されるように配置されている
ことを特徴とする半導体集積回路装置。 - 請求項15記載の半導体集積回路装置において、
前記第2ハイト領域は、前記第1ハイト領域と異なるハイト領域である
ことを特徴とする半導体集積回路装置。 - 請求項16記載の半導体集積回路装置において、
前記M個のハイト領域は、前記第1ハイト領域と前記第2ハイト領域とが、前記第2方向において交互に配置されている
ことを特徴とする半導体集積回路装置。 - 請求項10記載の半導体集積回路装置において、
前記第1ハイト領域に配置されており、前記第1共通信号の供給経路を構成するメタル配線は、前記第1方向に延びるように形成されている
ことを特徴とする半導体集積回路装置。 - 請求項10〜18のうちいずれか1項記載の半導体集積回路装置において、
前記複数の部分回路は、セレクタまたはラッチである
ことを特徴とする半導体集積回路装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016203262 | 2016-10-17 | ||
JP2016203262 | 2016-10-17 | ||
PCT/JP2017/035209 WO2018074172A1 (ja) | 2016-10-17 | 2017-09-28 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2018074172A1 true JPWO2018074172A1 (ja) | 2019-08-22 |
JP6978691B2 JP6978691B2 (ja) | 2021-12-08 |
Family
ID=62019239
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018546216A Active JP6978691B2 (ja) | 2016-10-17 | 2017-09-28 | 半導体集積回路装置 |
Country Status (4)
Country | Link |
---|---|
US (2) | US10840234B2 (ja) |
JP (1) | JP6978691B2 (ja) |
CN (1) | CN109863588B (ja) |
WO (1) | WO2018074172A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109863588B (zh) * | 2016-10-17 | 2022-09-30 | 株式会社索思未来 | 半导体集成电路装置 |
JP7370730B2 (ja) * | 2019-05-14 | 2023-10-30 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
CN114556563A (zh) * | 2019-10-18 | 2022-05-27 | 株式会社索思未来 | 半导体集成电路装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4743469B2 (ja) * | 2003-03-25 | 2011-08-10 | 株式会社日立製作所 | 半導体集積回路装置とクロック分配方法 |
JP4982663B2 (ja) * | 2004-06-25 | 2012-07-25 | 京セラ株式会社 | 表示パネル用ドライバ手段および画像表示装置 |
JP5216287B2 (ja) * | 2007-09-21 | 2013-06-19 | 株式会社日立製作所 | 半導体装置 |
JP5072578B2 (ja) * | 2007-12-21 | 2012-11-14 | キヤノン株式会社 | ヘッド素子基板、記録ヘッド、及び記録装置 |
US20090167394A1 (en) * | 2007-12-31 | 2009-07-02 | Texas Instruments Incorporated | Integrated circuits having devices in adjacent standard cells coupled by the gate electrode layer |
JP5630856B2 (ja) * | 2010-02-10 | 2014-11-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2012222151A (ja) * | 2011-04-08 | 2012-11-12 | Panasonic Corp | 半導体集積回路装置 |
JP2012227395A (ja) * | 2011-04-20 | 2012-11-15 | Panasonic Corp | 半導体集積回路装置 |
US9165102B1 (en) * | 2014-04-07 | 2015-10-20 | Freescale Semiconductor, Inc. | Routing standard cell-based integrated circuits |
US9202820B1 (en) * | 2014-05-28 | 2015-12-01 | Pdf Solutions, Inc | Flip-flop, latch, and mux cells for use in a standard cell library and integrated circuits made therefrom |
KR102497218B1 (ko) * | 2016-04-29 | 2023-02-07 | 삼성전자 주식회사 | 복합 논리 셀을 포함하는 집적 회로 |
CN109863588B (zh) * | 2016-10-17 | 2022-09-30 | 株式会社索思未来 | 半导体集成电路装置 |
-
2017
- 2017-09-28 CN CN201780063928.6A patent/CN109863588B/zh active Active
- 2017-09-28 JP JP2018546216A patent/JP6978691B2/ja active Active
- 2017-09-28 WO PCT/JP2017/035209 patent/WO2018074172A1/ja active Application Filing
-
2019
- 2019-04-16 US US16/386,116 patent/US10840234B2/en active Active
-
2020
- 2020-10-13 US US17/069,235 patent/US11916056B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN109863588A (zh) | 2019-06-07 |
US11916056B2 (en) | 2024-02-27 |
CN109863588B (zh) | 2022-09-30 |
WO2018074172A1 (ja) | 2018-04-26 |
US10840234B2 (en) | 2020-11-17 |
US20190244949A1 (en) | 2019-08-08 |
JP6978691B2 (ja) | 2021-12-08 |
US20210028162A1 (en) | 2021-01-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN109314110B (zh) | 用于基于鳍片计数的扩散的标准单元架构 | |
US6252448B1 (en) | Coincident complementary clock generator for logic circuits | |
US9966936B2 (en) | Semiconductor integrated circuits | |
US11916056B2 (en) | Semiconductor integrated circuit device | |
US7915925B2 (en) | Scannable D flip-flop | |
KR102368072B1 (ko) | 스캔 플립플롭 및 상기 스캔 플립플롭을 포함하는 스캔 테스트 회로 | |
TWI680562B (zh) | 具有備用電路單元的積體電路 | |
US20240088046A1 (en) | Standard Cell Layout for Better Routability | |
US9257986B2 (en) | Rescaling | |
JP4743469B2 (ja) | 半導体集積回路装置とクロック分配方法 | |
US8788987B2 (en) | Rescaling | |
US4356413A (en) | MOSFET Convolved logic | |
US11658656B2 (en) | Low power clock gating cell and an integrated circuit including the same | |
US20150263706A1 (en) | Semiconductor integrated circuit | |
JP2011258712A (ja) | 半導体集積回路 | |
US5502404A (en) | Gate array cell with predefined connection patterns | |
US7185307B2 (en) | Method of fabricating and integrated circuit through utilizing metal layers to program randomly positioned basic units | |
JPWO2017122417A1 (ja) | 集積回路 | |
JP2016046479A (ja) | 半導体装置及び半導体装置の設計方法とプログラム | |
JP3660184B2 (ja) | 論理セル | |
CN118318295A (en) | Semiconductor integrated circuit device with a plurality of semiconductor chips | |
Kwan et al. | Design of multi-ghz asynchronous pipelined circuits in MOS current-mode logic | |
JP2003332438A (ja) | 半導体装置及びその製造方法 | |
JPH07202001A (ja) | 半導体集積回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190311 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190722 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20200819 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20211012 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20211025 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6978691 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |