JPWO2016185585A1 - 電気回路及び表示装置 - Google Patents
電気回路及び表示装置 Download PDFInfo
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- JPWO2016185585A1 JPWO2016185585A1 JP2017518687A JP2017518687A JPWO2016185585A1 JP WO2016185585 A1 JPWO2016185585 A1 JP WO2016185585A1 JP 2017518687 A JP2017518687 A JP 2017518687A JP 2017518687 A JP2017518687 A JP 2017518687A JP WO2016185585 A1 JPWO2016185585 A1 JP WO2016185585A1
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- electric circuit
- buses
- scramble
- data
- timing
- Prior art date
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- 238000000034 method Methods 0.000 claims abstract description 38
- 238000004891 communication Methods 0.000 claims abstract description 26
- 230000005540 biological transmission Effects 0.000 claims abstract description 23
- 239000004973 liquid crystal related substance Substances 0.000 claims description 28
- 208000032365 Electromagnetic interference Diseases 0.000 description 20
- 238000005259 measurement Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G3/2096—Details of the interface to the display terminal specific for a flat panel
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
- H04L25/03866—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/38—Transmitter circuitry for the transmission of television signals according to analogue transmission standards
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Multimedia (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
図1は実施の形態1の液晶テレビジョン100の要部構成を示す機能ブロック図である。
本発明は実施の形態1に記載の液晶テレビジョン100に限るものでない。
20 Tcon(送信部、受信部)
21 DeSkew(解除部)
26 シリアライザ(遅延部)
24 スクランブラ(スクランブル部)
30 ソースドライバ(受信部)
40 ゲートドライバ
100 液晶テレビジョン
Claims (6)
- 送信部、及び、複数のバスを介して該送信部とデータフレームの通信を行う一又は複数の受信部を備え、前記データフレームの通信の際、スクランブル処理を行う電気回路において、
前記データフレームの通信時間に対してバス毎に異なるタイミングで前記スクランブル処理を行うことを特徴とする電気回路。 - 前記送信部は、任意の2つのバス間にnUIの出力遅延を生じさせる処理を行う遅延部を備えることを特徴とする請求項1に記載の電気回路。
但し、n:整数、ただし任意の2つ以上のバス間は0を除く、UI:データレートの1周期。 - 前記受信部は、前記送信部から受信したデータに対して、前記遅延部による処理を解除する解除部を備えることを特徴とする請求項2に記載の電気回路。
- 前記送信部は、任意の2つのバスのデータフレーム間でnUIのタイミング差になるように前記スクランブル処理を行うスクランブル部を備えることを特徴とする請求項1に記載の電気回路。
但し、n:整数、ただし任意の2つ以上のバス間は0を除く、UI:データレートの1周期。 - 前記受信部は、前記送信部から受信したデータに対して、前記スクランブル部によるスクランブル処理を解除する解除部を備えることを特徴とする請求項4に記載の電気回路。
- 請求項1〜5の何れかに記載の電気回路と、
該電気回路に接続された液晶表示パネルとを備え、
前記電気回路を介して受信したデータに基づいて、前記液晶表示パネルが画像表示を行うことを特徴とする表示装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2015/064485 WO2016185585A1 (ja) | 2015-05-20 | 2015-05-20 | 電気回路及び表示装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2016185585A1 true JPWO2016185585A1 (ja) | 2018-03-08 |
JP6473808B2 JP6473808B2 (ja) | 2019-02-20 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017518687A Active JP6473808B2 (ja) | 2015-05-20 | 2015-05-20 | 電気回路及び表示装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10515578B2 (ja) |
JP (1) | JP6473808B2 (ja) |
CN (1) | CN107615700B (ja) |
WO (1) | WO2016185585A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016185585A1 (ja) * | 2015-05-20 | 2016-11-24 | 堺ディスプレイプロダクト株式会社 | 電気回路及び表示装置 |
CN108694896B (zh) | 2017-06-09 | 2021-11-16 | 京东方科技集团股份有限公司 | 信号传输方法、发送单元、接收单元及显示装置 |
CN109036328B (zh) * | 2017-06-09 | 2021-09-03 | 京东方科技集团股份有限公司 | 寄存器值传输方法及组件、显示装置 |
US11250753B2 (en) | 2020-04-16 | 2022-02-15 | Synaptics Incorporated | EMI mitigation by shifted source line pre-charge |
Citations (3)
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JPH01213042A (ja) * | 1988-02-22 | 1989-08-25 | Fujitsu Ltd | 多重化方式 |
WO2010109668A1 (ja) * | 2009-03-27 | 2010-09-30 | 富士通株式会社 | 位相調整方法、データ転送装置およびデータ転送システム |
JP2014529269A (ja) * | 2011-09-30 | 2014-10-30 | インテル コーポレイション | 高速通信リンクのトレーニング中に電源ノイズを低減する方法及びシステム |
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US6636607B1 (en) * | 1998-10-08 | 2003-10-21 | Ati International Srl | Method and apparatus for controlling display of content signals |
JP2004138933A (ja) * | 2002-10-21 | 2004-05-13 | Hitachi Ltd | デジタル映像スクランブル装置、デスクランブル装置および該装置を実現するプログラム |
US7095407B1 (en) * | 2003-04-25 | 2006-08-22 | National Semiconductor Corporation | Method and apparatus for reducing noise in a graphics display system |
JP3821111B2 (ja) * | 2003-05-12 | 2006-09-13 | セイコーエプソン株式会社 | データドライバ及び電気光学装置 |
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2015
- 2015-05-20 WO PCT/JP2015/064485 patent/WO2016185585A1/ja active Application Filing
- 2015-05-20 CN CN201580080185.4A patent/CN107615700B/zh active Active
- 2015-05-20 JP JP2017518687A patent/JP6473808B2/ja active Active
- 2015-05-20 US US15/574,751 patent/US10515578B2/en active Active
Patent Citations (3)
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JPH01213042A (ja) * | 1988-02-22 | 1989-08-25 | Fujitsu Ltd | 多重化方式 |
WO2010109668A1 (ja) * | 2009-03-27 | 2010-09-30 | 富士通株式会社 | 位相調整方法、データ転送装置およびデータ転送システム |
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Also Published As
Publication number | Publication date |
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JP6473808B2 (ja) | 2019-02-20 |
WO2016185585A1 (ja) | 2016-11-24 |
US20180151107A1 (en) | 2018-05-31 |
CN107615700A (zh) | 2018-01-19 |
US10515578B2 (en) | 2019-12-24 |
CN107615700B (zh) | 2020-08-11 |
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