JPWO2003005786A1 - Manufacturing method of printed wiring board - Google Patents
Manufacturing method of printed wiring board Download PDFInfo
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- JPWO2003005786A1 JPWO2003005786A1 JP2003511605A JP2003511605A JPWO2003005786A1 JP WO2003005786 A1 JPWO2003005786 A1 JP WO2003005786A1 JP 2003511605 A JP2003511605 A JP 2003511605A JP 2003511605 A JP2003511605 A JP 2003511605A JP WO2003005786 A1 JPWO2003005786 A1 JP WO2003005786A1
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- jig
- silicon wafer
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- film
- thin film
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000010408 film Substances 0.000 claims abstract description 28
- 239000010409 thin film Substances 0.000 claims abstract description 20
- 230000002093 peripheral effect Effects 0.000 claims abstract description 18
- 239000004020 conductor Substances 0.000 claims abstract description 14
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 65
- 238000000034 method Methods 0.000 claims description 35
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 230000003746 surface roughness Effects 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 238000005553 drilling Methods 0.000 claims 1
- 230000000630 rising effect Effects 0.000 claims 1
- 239000000463 material Substances 0.000 description 24
- 235000012431 wafers Nutrition 0.000 description 24
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 238000007772 electroless plating Methods 0.000 description 6
- 239000002131 composite material Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000007888 film coating Substances 0.000 description 3
- 238000009501 film coating Methods 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910001369 Brass Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000010951 brass Substances 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- -1 gold ions Chemical class 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge clamping, e.g. clamping ring
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68735—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68778—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by supporting substrates others than wafers, e.g. chips
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
本発明は、多段積層可能なプリント回路板を製造し得る極薄のプリント配線板の製造方法であって、下記のステップを含んでなることを特徴とする：Ａ．厚みが５０μｍ〜３００μｍのシリコンウエーハ（２０）を準備する；Ｂ．該シリコンウエーハ（２０）をその周縁部のみを保持し得る治具（１０）に取付け、その全面をフィルムにて被覆し、該シリコンウエーハ（２０）を該治具（１０）に固定する；Ｃ．該フィルムをパターニングしてシリコンウエーハ（２０）の表裏面を露出させる；Ｄ．該露出せしめられたシリコンウエーハ（２０）の所定位置にスルーホールを形成するとともに、該スルーホールを含む該シリコンウエーハ（２０）の露出面に金属薄膜を形成する；Ｅ．該金属薄膜をパターニングし、次いでエッチングを行って、所定の導体パターンを得る。The present invention is a method of manufacturing an ultra-thin printed wiring board capable of manufacturing a multi-layered printed circuit board, comprising the following steps: B. prepare a silicon wafer (20) having a thickness of 50 μm to 300 μm; Attaching the silicon wafer (20) to a jig (10) capable of holding only the peripheral portion thereof, covering the entire surface with a film, and fixing the silicon wafer (20) to the jig (10); C . Patterning the film to expose the front and back surfaces of the silicon wafer (20); B. forming a through hole at a predetermined position of the exposed silicon wafer (20), and forming a metal thin film on an exposed surface of the silicon wafer (20) including the through hole; The metal thin film is patterned and then etched to obtain a predetermined conductor pattern.
Description
技術分野
本発明は、極薄のシリコンウェハを基材とするプリント配線板の製造方法に関する。
背景技術
電子部品の高密度実装の要請に対応して、プリント配線板も多層化したもの（多層プリント配線板）が使用されている。しかしながら、多層プリント配線板は、その基板としてセラミック基板、積層板、コンポジット積層板等を用いており、基板の厚みと電気特性上の要求がマッチしていなかった。
発明の開示
本発明は、多段積層可能なプリント回路板を製造し得る極薄のプリント配線板の製造方法を提供することを目的とする。
すなわち本発明は、下記のステップを含んでなることを特徴とするプリント配線板の製造方法である。
Ａ．厚みが５０μｍ〜３００μｍのシリコンウェーハを準備する；
Ｂ．該シリコンウェーハをその周縁部のみを保持し得る治具に取付け、その全面を治具ごとフィルムにて被覆し、該シリコンウェーハを該治具に固定する；
Ｃ．該フィルムをパターニングしてシリコンウェーハの表裏面を露出させる（該露出せしめられた部分が配線パターン、スルーホール及びバンプランド形成のためのワークエリアとなる）；
Ｄ．該露出せしめられたシリコンウェーハの所定位置にスルーホールを形成するとともに、該スルーホールを含む該シリコンウーェハの露出面に金属薄膜を形成する；そして
Ｅ．該金属薄膜をパターニングし、次いでエッチングを行って、所定の導体パターンを得る。
発明を実施するための最良の形態
本発明を、一実施態様を示す添付図面（図１を除き、各部材の相互関係及び構造を示すのが目的ゆえ、図示の寸法は実寸ではない）を参照しつつ詳細に説明する。
図１に示したものが本発明の標準的なプロセスダイヤグラムである。
Ａ．基板の準備
本発明においては、基板材料（２０）としてインゴットから切り出されたシリコンウェーハを用いる。その厚さは５０〜３００μｍである（因みに半導体用のそれは８インチのもので７３５μｍである。チップの状態では最小３０μｍ程度の厚さであるが、これはインゴットから切り出されたウェーハに別途研削加工を施して減じたものである）。尚、その表面の粗さは、１０００Å〜５０００Å（ＪＩＳ Ｂ ０６０１に規定する十点平均粗さ：Ｒｚ）程度で充分であり、半導体用のそれのような鏡面仕上げを要しない。
Ｂ．治具への取付
前工程にて準備された基板材料（２０）はその厚さが薄いため、その後の加工におけるハンドリング性や加工精度を考慮し、該基板を特殊な治具（１０）にて保持する。具体的には、図２に示すように、該基板の周縁部（２０ａ）を該治具の主体部（１０ａ）内周縁部に設けられた段部（１０ｂ）（図示では、全周に形成された態様となっているが、周方向に所定間隔にて爪状に飛び飛びに形成してもよい。その場合には、保持の安定性確保の観点から少なくとも３ヶ所に設ける）上に載置する（後述のように、次工程にて該治具と該基板とはフィルムで一体化するので、通常は載置で充分である）。尚、図３に示す治具（１０）は、一つの部材（１０ａ）（以下では、治具の主体部という）からなるものであるが、該治具上への該基板の保持をより確実にするために、該部材を二つの部材（１１）と（１２）に分割し、両部材の内周縁部にそれぞれ段部（１１ａ，１２ａ）（断部の高さはそれぞれ該基板の厚みの１／２）を設け、両部材にて該基板の周縁部（２０ａ）を挟み込む形態（図４参照）にしてもよいし、一方の部材（１１）の内周縁部にのみ段部（１１ａ）（その高さは該基板の厚みに同じ）を設け、他方の部材（１２）はその下面が平坦で該下面の先端部で該段部に載置された該基板の周縁部（２０ａ）の上面を押える態様（図５参照）にしてもよいし、該治具を、段部を有する主体部（１１ｂ）（実質的に図４及び図５図示の治具を構成する二つの部材（１１，１２）が一体となった形態であって、該段部の底部が、該主体部の厚みの中心より該基板の厚みの１／２下がった位置となるよう形成）と、該段部の奥行きをその幅とし、その外周縁部を該治具の段部の最深部に当接する実質的にドーナツ状の円板（１２ｂ）（図５図示の他方の部材（１２）がその先端部のみとなった形態）とからなるものにしてもよい（図６参照）。図中、符号１４は該治具の開口部である（図２は該治具に該基板が取付けられた状態にて描かれているため、符号２０と１４、及び２０ａと１０ｂと１１ａと１２ａと１２ｂとが、それぞれ同一個所に付されている。また符号１０ａと１１と１１ｂと１２もそれらの指示する部材の上面と下面が当接した状態で上から見ているので同一個所に付されている）。尚、該治具を構成する部材のスロープ部（１０ｃ，１０ｄ，１１ｃ，１１ｄ，１２ｃ，１１ｄ）は、後述のフィルムによる被覆工程における該治具及び該基板の円滑な被覆並びに金属薄膜の形成工程（１）及び／又は（２）及び導体パターンの形成工程において塗付されるレジストの厚みの均一化のためにそのようにされているものである（スロットコーティング−コーターを径方向に配置・適用する−；スピンコーティング−余剰レジストの円滑排出−等）。その角度は、該治具上に保持すべき該基板の径、したがって該治具の径、更には塗付するレジストの性質に応じて適宜設定すれば良い。一般的には、３〜１０°の範囲で選定する。また、該治具の角部、例えば外周面から上下面への移行部分や、隅部には、次工程であるフィルムによる被覆を確実なものとするため、適度なＲをつけておくことが好ましい。
ここで、該治具は、ある程度の剛性を有し、導電性及び耐化学薬剤性に優れる、という点において、アルミニウム、銅、真鍮等の金属にて作製される（治具が二つの部材からなり、それらの一方の部材がドーナツ状の円板である態様においては、その重量も該基板の保持に資するので、金属製とするのが好ましい）。
また、該治具の段部は、その上に該基板を載置した状態において、該治具の上面と該基板の上面との距離：Ｈ（図４及び図５図示の態様においては、該治具の他方の部材の上面と該基板の上面との距離、図６図示の態様においては、該治具の主体部の上面と該基板の上面との距離）が該治具の下面と該基板の下面との距離：Ｈ（図４及び図５図示の態様においては、該治具の一方の部材の下面と該基板の下面との距離、図６図示の態様においては、該治具の主体部の下面と該基板の下面との距離）とが等しくなるように設定する。導体パターンの高密度化をはかるため該基板の上下面をその形成個所として活用するにあたり、その形成操作としてのパターニングにおける露光を該基板の上下面の転倒にて簡単になすことができるからである。更に、図示では該基板材料としてのシリコンウェーハ１枚に対し該治具が１個の態様が示されているが、勿論複数枚のシリコンウェーハに対して該治具を１個とした態様を取り得ること言うまでもない（露光ワークエリアの確保の柔軟性からは１対１の対応がよく、一方、後述の金属薄膜の形成の効率化という点においては複数対１の対応がよいので、状況に応じて適宜選定すればよい）。また、図示では実質的に角形の治具とされているが、その外形は円形や多角形としても良いこと勿論である。尚、該治具の上面と下面及びそれらに連なるスロープに放射状に複数（その数は、該治具上に保持すべき該基板の径、したがって該治具の径に応じて適宜選定すればよい）の空気抜き用の溝（１３）を該治具の合成分布に配慮して設ける（その始点又は終点は、該治具の外周端部であり、その終点又は始点は、該治具のスロープの内周端部である）。後述のフィルム被覆を確実に行なうためである。ここで、該溝の形状（断面）は半円、半楕円、角、三角等フィルム被覆時の該治具及び該基板とフィルム間に存在する空気がスムースに抜けるものであればいずれの形状であってもよい。但し、該溝の壁の上端から該治具のスロープ部を含む上下面への移行部は、フィルムの密着性を確保するためにＲをつけておくことが好ましい。
Ｃ．フィルムによる被覆
その後の加工の精度を確保するため、該治具に保持された該基板材料を、該治具共々フィルム（１４）にて被覆・固定する。該フィルムとしては、取扱性の面からドライレジスト、例えばネガ型のドライフィルムを候補として挙げることができる。尚、該フィルムによる被覆は、該フィルムを、例えば真空ラミネート法等にて該基板材料が保持された該治具全体に密着させ、そして該フィルムを、該基板の周縁部（２０ａ）の内方近傍部を除く該基板材料の表裏面が露出するようにパターニングすることによって行う（図７参照。該基板材料は、その表裏面の大半（図中の矢印を付した範囲）が露出せしめられた状態にて該治具に緊密に保持されている。尚、図７は断面図ゆえ、該被覆フィルムも、本来は斜線を入れて表示すべきであるが、表示の煩雑さを避けるため斜線は割愛した）。
Ｄ．スルーホールの形成
プリント回路板の多段積層のために該基板材料の所定の位置にスルーホールを形成する。該基板材料はその厚さが薄いので、該スルーホールの形成方法としてはレーザー、例えば炭酸ガスレーザーやＹＡＧレーザーによる穿孔法、プラズマエッチング法、フォトリソグラフィー法等を適用し得る。
Ｅ．金属薄膜−１の形成
後述する金属薄膜−２の密着性を確保するため、該基板材料の露出した表面に金属薄膜−１、例えばＩＴＯや銅［Ｃｕ］等の薄膜（厚み：少なくとも５０Å）を形成する。その方法としては蒸着法が挙げられる。一方、得られる金属薄膜の厚みがさほど厚くなくてもよい用途については、該金属薄膜−１は、無電解メッキ法（ニッケル［Ｎｉ］の薄膜を形成した後、金［Ａｕ］で該ニッケル薄膜の一部を置換する）にても形成することができる（この場合、形成される薄膜は、下層又は基層がニッケル、上層又は表層が金の複合膜となる）。尚、この金属薄膜−１は、該基板材料の表面のみならず、先に形成したスルーホールの壁面にも形成する。
Ｆ．金属薄膜−２の形成
その上に金属薄膜−１が形成された該基板材料の表面に導体パターンの主体となる金属薄膜−２、例えばＣｕ等を形成する。その方法としては無電解メッキ法が挙げられる（工程Ｅで無電解メッキ法を適用する場合には、この工程は不要）。より厚い金属薄膜（厚み：３μｍ以上）を所望の場合には更に電気メッキ法を適用する。尚、この金属薄膜は、該基板材料の表面のみならず、先に形成したスルーホールの壁面にも形成する。
Ｇ．導体パターンの形成
従来の導体パターンの形成と同様、レジスト塗付（常法に従って行えばよい。但し、スロットコーター単用又はスロットコーターによる塗付の後で該治具を回転させるスロット・アンド・スピン法の適用がレジストの消費量が少なく済むと共に、凹部にも塗付し得るので好ましい。尚、スロットコーターは治具（１０）及び基板（２０）の径方向に配置し、該スロットコーターを、該治具及び該基板のセンターを中心として回転させるとよい）、露光・現像（所望する導体パターン以外の部分の金属薄膜を露出せしめる）、露出せしめられた金属薄膜のエッチング除去、レジストの剥離・除去を行う。尚、該基板材料を該治具に固定するためのフィルムとしてネガ型のドライフィルムを使用した場合には、ここで使用するレジストとしてはポジ型のものを使う。この工程で使用する現像液への該フィルムの溶解を防止できるからである。
Ｈ．その他
一応、ここまでの工程にてプリント配線板としての機能を有するものが製造されるので、後は所望の大きさに切断することでプリント配線板が得られるが、更に該プリント配線板にバンプの形成を行う必要があるならば、切断の前に、レジスト塗付、露光・現像（導体パターン中のバンプ形成個所を露出せしめる）、バンプ形成（金イオンを含む溶液を用いたメッキでよい。尚、バンプはある程度の高さを必要とするので、先ず銅又はニッケル等からなる下地を形成し、該下地の表層にのみ金メッキを施せばよい）、レジストの剥離・除去という一連の操作を行なうか又は半田ボールを常法に従って所定の位置に被着させればよい。
ここまで、基板上に導体パターンを新たに形成するケースにて説明してきたが、本発明の治具を用いる製法の特徴は、従来は例のないほど極薄の基板（シリコンウェーハ）であってもその薄さに起因する問題を解消し得ることにあるので、基板上に既に導体パターンが形成されたもの、例えば回路形成済みのＩＣにバンプのみを形成するケースにおいても適用し得ること勿論である。因みに、従来のＩＣ製造においては、厚いままの基板（シリコンウェーハ）の裏面を所望の厚みに物理研削した後にバンプを形成する方法（バンプを形成する基板は薄いので当然にハンドリング性が悪い）や厚いままの基板（シリコンウェーハ）にバンプを形成した後、ドライエッチング等にて該基板の裏面を所望の厚みに研削する方法（ドライエッチング設備を設けるために相当の費用を要す）が適用されていた。
実施例
８インチのシリコンウェーハ（厚さ：２００μｍ：公称径：２００ｍｍ）を用い、下記の要領にてプリント配線板２０個を製造した。
１．基板材料保持用治具
下記の仕様の治具（具体的態様は図３図示のもの）を使用。
・縦：２３０ｍｍ；
・横：２３０ｍｍ；
・厚み：１ｍｍ；
・開口部の径：１９６ｍｍ；
・段部の幅：２ｍｍ；
・段部の形成範囲：全周；
・上部スロープの傾斜：約７．６°
・下部スロープの傾斜：約４．６°
２．フィルム被覆
前記の治具の段部に載置したシリコンウェーハの両面を、真空ラミネーター（ニチゴーモートン社製ＣＶＡ ＭＯＤＥＬ ７２５）を用い、ドライフィルム（ニチゴーモートン社製ＮＩＴ３１５；厚さ：１５μｍ）で該治具ごと被覆して該シリコンウェーハを該治具に密着固定し、次いで、常法に従い該被覆ドライフィルムを露光・現像し、直径：１９０ｍｍのワークエリア（両面）を該シリコンウェーハー上に確保した。
３．スルーホールの形成
ウエットエッチング法にて該ワークエリア内のシリコンウェーハにスルーホール（径：１００μｍ）を１０個／枚形成した。
４．金属薄膜−１の形成
スパッタ装置（日本真空社製ＳＨ−４５０）を使用し、該ワークエリア内のシリコンウェーハ（両面。スルーホールの内壁を含む）上に金属薄膜−１（ＩＴＯ；厚さ：１００Å）を形成した（対象ウェーハ枚数：１枚）。
また、無電解メッキ法（メルテックス社製メルプレートＮｉ−８６７Ｍ１〜Ｍ２及びＡｕ−６０１を使用）にても、金属薄膜−１（Ｎｉ＋Ａｕ；厚さ：０．５μｍ）を形成した（対象ウェーハ枚数：１枚）。
５．金属薄膜−２の形成
無電解メッキ法（シプレイファーイースト社製Ｃｕ Ｐｏｓｉｔ ２５１を使用）にて、先にスパッタリング法で形成した金属薄膜−１上に更に金属薄膜−２（Ｃｕ；厚さ：２０μｍ）を形成した。
６．導体パターンの形成
前記の金属薄膜−２上及び無電解メッキ法のみにて形成した金属薄膜−１上にそれぞれレジスト（シプレイファーイースト社製ポジ型レジスト：ＳＰＲ−６８００）を塗付し、次いで露光・現像・エッチング・レジスト剥離を行い、該シリコンウェーハ（両面）上に配線パターンを形成した。尚、詳細要領は下記の通り。
・使用コーター：平田機工社製スロットコーター（αコーター）
・レジスト塗付厚さ：１０μｍ（乾燥後：３μｍ）
・マスクパターン：３μｍのＬ／Ｓを使用
・露光光源：目白インベストメント社製２００Φ ＰＲＯＪ−２００１を使用
・エッチング液：シプレイ・ファーイースト社製Ｖ Ｐｏｓｉｔ Ｅｔｃｈ ７４６を使用
・剥離液：シプレイ・ファーイースト社製リムーバー１１７７Ａを使用
７．バンプの形成
レジスト（シプレイファーイースト社製ポジ型レジスト：ＳＰＲ−６８００）を塗付し、次いで露光・現像・電気メッキ・レジスト剥離を行い、該配線パターンのバンプランド上に金バンプを形成した。尚、詳細要領は下記の通り。
・使用コーター：平田機工社製スロットコーター（αコーター）。スロットの向きは該基板の半径方向。
・レジスト塗付厚さ：１０μｍ
・マスクパターン：バンプランド径が１００μｍΦ及び２００μｍΦ
・露光光源：目白インベストメント社製２００Φ ＰＲＯＪ−２００１を使用
・メッキ液：リロナール社製のエバロンＮｉ ＢＭ−２（下地用）及びオーロレプトロレスＳＭＴ２５０（金メッキ）をそれぞれ使用
・剥離液：シプレイファーイースト社製リムーバー１１７７Ａを使用
８．ダイシング
従来のＩＣウェーハダイシングに準拠。
できあがったプリント配線板（２０ｍｍ×２０ｍｍ）を上下方向に５層積層し、通電したところ、全配線板への導通が確認された。
産業上の利用可能性
上記の通り、本発明によれば、基板の厚みと電気特性上の要求がマッチした多段積層可能な極薄のプリント回路板を製造し得るプリント配線板の製造方法を提供し得る。
【図面の簡単な説明】
図１は、本発明のプリント配線板の製造方法を主要工程の流れに沿って示したブロックダイヤグラムである。
図２は、本発明のプリント配線板の製造方法に用いる治具をそれに保持した基板材料とともに示した平面図である。
図３は、図２図示の基板材料を保持した治具の一態様を示す部分拡大断面図（Ａ−Ａ線で切断）である。
図４は、図２図示の基板材料を保持した治具の他の態様を示す部分拡大断面図（Ａ−Ａ線で切断）である。
図５は、図２図示の基板材料を保持した治具の更に他の態様を示す部分拡大断面図（Ａ−Ａ線で切断）である。
図６は、図２図示の基板材料を保持した治具のまた更に他の態様を示す部分拡大断面図（Ａ−Ａ線で切断）である。
図７は、図３図示の基板材料を保持した治具をフィルムにて被覆し、そして該基板材料の表裏面を露出させた状態を示す部分拡大断面図である。
ここで、各符号は
１０ 治具
１０ａ 治具の主体部
１０ｂ 治具の段部
１０ｃ 治具のスロープ部（一方のスロープ部）
１０ｄ 治具のスロープ部（他方のスロープ部）
１１ 治具の一方の構成部材
１１ａ 治具の一方の構成部材の段部
１１ｂ 治具の一方の構成部材（主体部）
１１ｃ 治具の一方の構成部材のスロープ部又は主体部のスロープ部（一方のスロープ部）
１１ｄ 治具の一方の構成部材（主体部）のスロープ部（他方のスロープ部）
１２ 治具の他方の構成部材
１２ａ 治具の他方の構成部材の段部
１２ｂ 治具の他方の構成部材（ドーナツ状の部材）
１２ｃ 治具の他方の構成部材のスロープ部
１３ 治具の溝
１４ 開口部
１５ 被覆フィルム
２０ 基板材料
２０ａ 基板材料の周縁部
を、それぞれ表わす。TECHNICAL FIELD The present invention relates to a method for manufacturing a printed wiring board using an extremely thin silicon wafer as a base material.
BACKGROUND ART In response to demands for high-density mounting of electronic components, multilayer printed wiring boards (multilayer printed wiring boards) have been used. However, the multilayer printed wiring board uses a ceramic substrate, a laminate, a composite laminate, or the like as its substrate, and the thickness of the substrate does not match the requirement on the electrical characteristics.
DISCLOSURE OF THE INVENTION An object of the present invention is to provide a method of manufacturing an extremely thin printed wiring board capable of manufacturing a printed circuit board that can be stacked in multiple stages.
That is, the present invention is a method for manufacturing a printed wiring board, comprising the following steps.
A. Preparing a silicon wafer having a thickness of 50 μm to 300 μm;
B. Attaching the silicon wafer to a jig capable of holding only its peripheral portion, covering the entire surface with the jig together with a film, and fixing the silicon wafer to the jig;
C. Patterning the film to expose the front and back surfaces of the silicon wafer (the exposed portions serve as work areas for forming wiring patterns, through holes and bump lands);
D. B. forming a through hole at a predetermined position of the exposed silicon wafer and forming a metal thin film on an exposed surface of the silicon wafer including the through hole; The metal thin film is patterned and then etched to obtain a predetermined conductor pattern.
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described with reference to the accompanying drawings showing an embodiment (the dimensions shown are not to scale except for the purpose of showing the interrelationship and structure of each member except FIG. 1). This will be described in detail.
FIG. 1 shows a standard process diagram of the present invention.
A. Preparation of substrate In the present invention, a silicon wafer cut from an ingot is used as the substrate material (20). Its thickness is 50 to 300 μm (for semiconductors, it is 735 μm for an 8-inch chip. In the state of a chip, the thickness is at least about 30 μm, but this is separately ground on a wafer cut from an ingot. Is reduced by applying). The surface roughness is approximately 1000 to 5000 (ten-point average roughness: Rz specified in JIS B0601), and does not require a mirror finish like that for semiconductors.
B. Attachment to jig Since the substrate material (20) prepared in the previous process has a small thickness, taking into account handling properties and processing accuracy in subsequent processing, the substrate is attached to a special jig ( Hold in 10). Specifically, as shown in FIG. 2, the peripheral portion (20a) of the substrate is formed with a step (10b) provided on the inner peripheral portion of the main portion (10a) of the jig (in FIG. However, it may be formed in the shape of a claw at predetermined intervals in the circumferential direction, in which case it is provided at least at three places from the viewpoint of securing the holding stability.) (As will be described later, the jig and the substrate are integrated by a film in the next step, so that the mounting is usually sufficient). Note that the jig (10) shown in FIG. 3 is composed of one member (10a) (hereinafter, referred to as a main part of the jig), but more securely holds the substrate on the jig. In order to achieve this, the member is divided into two members (11) and (12), and stepped portions (11a, 12a) (the height of the cut portions are each equal to the thickness of the substrate) 1/2), and the peripheral portion (20a) of the substrate may be sandwiched between both members (see FIG. 4), or the step (11a) may be provided only on the inner peripheral portion of one member (11). (The height is the same as the thickness of the substrate), and the other member (12) has a flat lower surface and a peripheral portion (20a) of the substrate mounted on the step at the tip of the lower surface. The upper surface may be held down (see FIG. 5), or the jig may be used as a main body (11b) having a step (substantially shown in FIGS. 4 and 5). In a form in which two members (11, 12) constituting a jig are integrated, a bottom of the step portion is positioned at a position lower than a center of a thickness of the main portion by a half of a thickness of the substrate. And a substantially donut-shaped disk (12b) (the other side in FIG. 5) in which the depth of the step portion is set to the width and the outer peripheral edge of the step portion contacts the deepest portion of the step portion of the jig. (See FIG. 6) (see FIG. 6). In the figure,
Here, the jig is made of a metal such as aluminum, copper, or brass in that it has a certain degree of rigidity and is excellent in conductivity and resistance to chemical agents (the jig is made of two members). In a mode in which one of the members is a donut-shaped disk, it is preferably made of metal because its weight also contributes to holding the substrate.)
Further, the step of the jig has a distance H between the upper surface of the jig and the upper surface of the substrate when the substrate is placed thereon (in the embodiment shown in FIGS. The distance between the upper surface of the other member of the jig and the upper surface of the substrate, in the embodiment shown in FIG. 6, the distance between the upper surface of the main part of the jig and the upper surface of the substrate) is the distance between the lower surface of the jig and the upper surface of the substrate. Distance to the lower surface of the substrate: H (in the embodiment shown in FIGS. 4 and 5, the distance between the lower surface of one member of the jig and the lower surface of the substrate; in the embodiment shown in FIG. 6, The distance between the lower surface of the main body and the lower surface of the substrate) is set to be equal. This is because, in utilizing the upper and lower surfaces of the substrate as formation points thereof in order to increase the density of the conductor pattern, exposure in patterning as a forming operation can be easily performed by overturning the upper and lower surfaces of the substrate. . Furthermore, in the drawing, one jig is shown for one silicon wafer as the substrate material, but of course, one jig is used for a plurality of silicon wafers. Needless to say (one-to-one correspondence is good from the flexibility of securing the exposure work area, while plural-to-one correspondence is good in terms of the efficiency of forming a metal thin film described later. Can be selected as appropriate). Although the jig is shown as being substantially square in the drawing, the outer shape of the jig may be, of course, circular or polygonal. In addition, the upper and lower surfaces of the jig and the slopes connected to them are radially plural (the number thereof may be appropriately selected according to the diameter of the substrate to be held on the jig, and therefore the diameter of the jig. The air vent groove (13) is provided in consideration of the composite distribution of the jig (the start point or the end point is the outer peripheral end of the jig, and the end point or the start point is the slope of the jig). Inner peripheral end). This is for surely performing the film coating described later. Here, the shape (cross section) of the groove may be any shape as long as the air existing between the jig and the substrate and the film at the time of coating the film smoothly escapes, such as a semicircle, a semiellipse, a corner, and a triangle. There may be. However, it is preferable that a transition portion from the upper end of the wall of the groove to the upper and lower surfaces including the slope portion of the jig is provided with R in order to secure the adhesion of the film.
C. Coating with film To ensure the accuracy of the subsequent processing, the substrate material held by the jig is coated and fixed together with the jig with the film (14). As the film, a dry resist, for example, a negative type dry film can be cited as a candidate from the viewpoint of handleability. The coating with the film is performed by, for example, bringing the film into close contact with the entire jig holding the substrate material by, for example, a vacuum laminating method, and bonding the film to the inner side of the peripheral portion (20a) of the substrate. This is performed by patterning so that the front and back surfaces of the substrate material except for the vicinity are exposed (see FIG. 7). Most of the front and back surfaces of the substrate material (the range indicated by arrows in the drawing) are exposed. 7 is a cross-sectional view, the covering film should be originally displayed with diagonal lines, but the diagonal lines are shown in order to avoid complication of the display. Omitted).
D. Formation of through hole A through hole is formed at a predetermined position of the substrate material for multi-layered printed circuit boards. Since the substrate material has a small thickness, a laser, for example, a perforation method using a carbon dioxide laser or a YAG laser, a plasma etching method, a photolithography method, or the like can be applied as the method for forming the through hole.
E. FIG. Formation of metal thin film-1 In order to secure the adhesion of metal thin film-2 described later, a metal thin film-1 such as a thin film of ITO or copper [Cu] (thickness: At least 50 °). As the method, a vapor deposition method can be used. On the other hand, for applications in which the thickness of the obtained metal thin film does not need to be so large, the metal thin film-1 is formed by an electroless plating method (a nickel [Ni] thin film is formed, and then the nickel thin film is formed by gold [Au]). (In this case, a part of the thin film is replaced) (in this case, the formed thin film is a composite film of nickel in the lower or base layer and gold in the upper or surface layer). The metal thin film-1 is formed not only on the surface of the substrate material but also on the wall surface of the previously formed through hole.
F. Formation of metal thin film-2 On the surface of the substrate material on which the metal thin film-1 is formed, a metal thin film-2 serving as a main component of a conductor pattern, for example, Cu or the like is formed. An example of the method is an electroless plating method (this step is unnecessary when the electroless plating method is applied in the step E). If a thicker metal thin film (thickness: 3 μm or more) is desired, an electroplating method is further applied. The metal thin film is formed not only on the surface of the substrate material but also on the wall surface of the previously formed through hole.
G. FIG. Formation of conductor pattern In the same manner as the formation of a conventional conductor pattern, a resist is applied (this may be performed according to a conventional method. However, a slot for rotating the jig after application by a single slot coater or by a slot coater). It is preferable to apply the & spin method because the consumption of the resist can be reduced and the concave portion can be applied to the concave portion.The slot coater is arranged in the radial direction of the jig (10) and the substrate (20). The slot coater may be rotated around the center of the jig and the substrate), exposure and development (exposing the metal thin film other than the desired conductor pattern), etching and removal of the exposed metal thin film, Strip and remove the resist. When a negative type dry film is used as a film for fixing the substrate material to the jig, a positive type resist is used here. This is because the dissolution of the film in the developer used in this step can be prevented.
H. Others A product having a function as a printed wiring board is manufactured in the steps up to this point. After that, the printed wiring board can be obtained by cutting it into a desired size. If it is necessary to form bumps on the wiring board, before cutting, apply resist, expose and develop (expose the bump formation locations in the conductor pattern), and form the bumps (using a solution containing gold ions). Since the bumps need to have a certain height, it is only necessary to first form a base made of copper or nickel, and then apply gold plating only to the surface layer of the base. Or the solder ball may be attached to a predetermined position according to a conventional method.
So far, the case where a conductor pattern is newly formed on a substrate has been described. However, the feature of the manufacturing method using the jig of the present invention is that an extremely thin substrate (silicon wafer) which has not been conventionally known. Is also applicable to a case where a conductor pattern is already formed on a substrate, for example, a case in which only bumps are formed on an IC on which a circuit has been formed. is there. Incidentally, in the conventional IC manufacturing, a method of physically bumping the back surface of a still thick substrate (silicon wafer) to a desired thickness and then forming a bump (the substrate on which the bump is formed is thin, so the handling is naturally poor) or After bumps are formed on a still thick substrate (silicon wafer), a method of grinding the back surface of the substrate to a desired thickness by dry etching or the like (which requires considerable cost to provide dry etching equipment) is applied. I was
Example 20 Using an 8-inch silicon wafer (thickness: 200 μm; nominal diameter: 200 mm), 20 printed wiring boards were manufactured in the following manner.
1. Substrate material holding jig A jig with the following specifications (specific embodiment shown in FIG. 3) is used.
-Length: 230 mm;
-Horizontal: 230 mm;
・ Thickness: 1 mm;
Opening diameter: 196 mm;
・ Step width: 2 mm;
・ Step formation range: all around;
・ Incline of upper slope: about 7.6 °
・ Incline of lower slope: about 4.6 °
2. Film Coating Both sides of the silicon wafer placed on the step of the jig were dried with a dry film (NIT 315 manufactured by Nichigo Morton; thickness: 15 μm) using a vacuum laminator (CVA MODEL 725 manufactured by Nichigo Morton). The silicon wafer was covered with the jig and fixed tightly to the jig, and then the coated dry film was exposed and developed according to a conventional method to secure a work area (both sides) having a diameter of 190 mm on the silicon wafer.
3. Formation of Through
4. Using a sputtering apparatus (SH-450 manufactured by Nihon Vacuum Co., Ltd.) on the silicon wafer (both sides, including the inner wall of the through hole) in the work area, the metal thin film-1 (ITO; thickness: 100 °) (the number of target wafers: 1).
The metal thin film-1 (Ni + Au; thickness: 0.5 μm) was also formed by the electroless plating method (using Melplates Ni-867M1 to M2 and Au-601 manufactured by Meltex Co., Ltd.) (the number of target wafers). : 1).
5. Formation of Metal Thin Film-2 By electroless plating (using Cu Position 251 manufactured by Shipley Fur East Co., Ltd.), the metal thin film-2 (Cu; thickness: 20 μm) was further formed on the metal thin film-1 previously formed by the sputtering method. ) Was formed.
6. Formation of Conductive Pattern A resist (positive resist: SPR-6800 manufactured by Shipley Far East Co., Ltd.) is applied onto the metal thin film-2 and the metal thin film-1 formed only by the electroless plating method, and then exposed. Development, etching, and resist stripping were performed to form a wiring pattern on the silicon wafer (both sides). The details are as follows.
・ Coater used: Hirata Kiko Co., Ltd. slot coater (α coater)
・ Resist coating thickness: 10 μm (after drying: 3 μm)
・ Mask pattern: L / S of 3 μm is used. ・ Exposure light source: 200Φ PROJ-2001 manufactured by Mejiro Investment Co., Ltd. ・ Etching liquid: V Position Etch 746 manufactured by Shipley Far East Co., Ltd. ・ Release liquid: Shipley Far East Co., Ltd. 6. Use 1177A made of remover. A bump forming resist (a positive type resist manufactured by Shipley Far East Co., Ltd .: SPR-6800) was applied, followed by exposure, development, electroplating, and resist peeling to form a gold bump on the bump land of the wiring pattern. The details are as follows.
・ Coater used: Hirata Kiko Co., Ltd. slot coater (α coater). The direction of the slot is the radial direction of the substrate.
・ Resist coating thickness: 10 μm
・ Mask pattern: bump land diameter of 100 μmΦ and 200 μmΦ
・ Exposure light source: 200Φ PROJ-2001 manufactured by Mejiro Investment Co., Ltd. ・ Plating solution: Evalon Ni BM-2 (base) and Auroreptrores SMT250 (gold plating) manufactured by Rironal Co., Ltd. ・ Release solution: Shipley Far East 7. Use remover 1177A Dicing Complies with conventional IC wafer dicing.
Five printed wiring boards (20 mm × 20 mm) were stacked in the vertical direction, and when current was applied, conduction to all the wiring boards was confirmed.
INDUSTRIAL APPLICABILITY As described above, according to the present invention, there is provided a method for manufacturing a printed wiring board capable of manufacturing an ultra-thin printed circuit board capable of being stacked in multiple stages, in which the requirements of the thickness of the substrate and the requirements of the electrical characteristics are matched. I can do it.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a method of manufacturing a printed wiring board according to the present invention along a flow of main steps.
FIG. 2 is a plan view showing a jig used in the method of manufacturing a printed wiring board of the present invention together with a substrate material held thereon.
FIG. 3 is a partially enlarged cross-sectional view (cut along line AA) showing one embodiment of a jig holding the substrate material shown in FIG.
FIG. 4 is a partially enlarged sectional view (cut along the line AA) showing another embodiment of the jig holding the substrate material shown in FIG.
FIG. 5 is a partially enlarged sectional view (cut along the line AA) showing still another embodiment of the jig holding the substrate material shown in FIG.
FIG. 6 is a partially enlarged cross-sectional view (cut along the line AA) showing still another embodiment of the jig holding the substrate material shown in FIG.
FIG. 7 is a partially enlarged cross-sectional view showing a state where the jig holding the substrate material shown in FIG. 3 is covered with a film and the front and back surfaces of the substrate material are exposed.
Here, each symbol is 10
10d Slope part of jig (other slope part)
11 One
11c Slope of one component member or slope of main part (one slope) of jig
11d Slope part of one component (main part) of jig (other slope part)
12 The other component of the
Claims (13)
Ａ．厚みが５０μｍ〜３００μｍのシリコンウェーハを準備する；
Ｂ．該シリコンウェーハをその周縁部のみを保持し得る治具に取付け、その全面をフィルムにて被覆し、該シリコンウェーハを該治具に固定する；
Ｃ．該フィルムをパターニングしてシリコンウェーハの表裏面を露出させる；
Ｄ．該露出せしめられたシリコンウェーハの所定位置にスルーホールを形成するとともに、該スルーホールを含む該シリコンウーェハの露出面に金属薄膜を形成する；
Ｅ．該金属薄膜をパターニングし、次いでエッチングを行って、所定の導体パターンを得る。A method for manufacturing a printed wiring board, comprising the following steps:
A. Preparing a silicon wafer having a thickness of 50 μm to 300 μm;
B. Attaching the silicon wafer to a jig capable of holding only the periphery thereof, covering the entire surface with a film, and fixing the silicon wafer to the jig;
C. Patterning the film to expose the front and back of the silicon wafer;
D. Forming a through hole at a predetermined position of the exposed silicon wafer, and forming a metal thin film on an exposed surface of the silicon wafer including the through hole;
E. FIG. The metal thin film is patterned and then etched to obtain a predetermined conductor pattern.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001204436 | 2001-07-05 | ||
| JP2001204436 | 2001-07-05 | ||
| PCT/JP2002/006711 WO2003005786A1 (en) | 2001-07-05 | 2002-07-03 | Method for manufacturing printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2003005786A1 true JPWO2003005786A1 (en) | 2004-10-28 |
| JP4153422B2 JP4153422B2 (en) | 2008-09-24 |
Family
ID=19040905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003511605A Expired - Fee Related JP4153422B2 (en) | 2001-07-05 | 2002-07-03 | Method for manufacturing printed wiring board |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP4153422B2 (en) |
| KR (1) | KR100914376B1 (en) |
| CN (1) | CN1290390C (en) |
| TW (1) | TW558920B (en) |
| WO (1) | WO2003005786A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI277167B (en) * | 2004-09-10 | 2007-03-21 | Toshiba Corp | Semiconductor wafer supporting plate and method for manufacturing semiconductor device |
| JP4863910B2 (en) * | 2007-03-19 | 2012-01-25 | 株式会社伸光製作所 | Thin plate base material conveying jig and printed wiring board manufacturing method |
| CN103187346B (en) * | 2011-12-29 | 2016-02-10 | 无锡华润华晶微电子有限公司 | For clamping wafer with the fixture corroded it |
| CN106449512B (en) * | 2016-10-28 | 2019-01-15 | 中国电子科技集团公司第四十四研究所 | Technique fixture for ultra thin silicon wafers processing |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4709468A (en) * | 1986-01-31 | 1987-12-01 | Texas Instruments Incorporated | Method for producing an integrated circuit product having a polyimide film interconnection structure |
| JPH0245921A (en) * | 1988-08-05 | 1990-02-15 | Nec Yamaguchi Ltd | Ion implantation device |
| JPH07180053A (en) * | 1993-12-24 | 1995-07-18 | Nissin Electric Co Ltd | Wafer holder |
| JPH0831976A (en) * | 1994-07-15 | 1996-02-02 | Sony Corp | Silicon double-sided packaging substrate and its manufacturing method |
| JPH08181440A (en) * | 1994-12-26 | 1996-07-12 | Sumitomo Metal Ind Ltd | Manufacture of multilayer thin film circuit board |
| JPH09214140A (en) * | 1995-11-29 | 1997-08-15 | Toppan Printing Co Ltd | Multilayered printed wiring board and its manufacture |
-
2002
- 2002-07-03 WO PCT/JP2002/006711 patent/WO2003005786A1/en active Application Filing
- 2002-07-03 KR KR1020037016940A patent/KR100914376B1/en not_active IP Right Cessation
- 2002-07-03 TW TW091114727A patent/TW558920B/en not_active IP Right Cessation
- 2002-07-03 CN CNB028132009A patent/CN1290390C/en not_active Expired - Fee Related
- 2002-07-03 JP JP2003511605A patent/JP4153422B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| TW558920B (en) | 2003-10-21 |
| JP4153422B2 (en) | 2008-09-24 |
| KR20040017247A (en) | 2004-02-26 |
| CN1290390C (en) | 2006-12-13 |
| KR100914376B1 (en) | 2009-08-28 |
| WO2003005786A1 (en) | 2003-01-16 |
| CN1522557A (en) | 2004-08-18 |
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