JP2000252411A - Stacked semiconductor device and its manufacture - Google Patents

Stacked semiconductor device and its manufacture

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Publication number
JP2000252411A
JP2000252411A JP5500499A JP5500499A JP2000252411A JP 2000252411 A JP2000252411 A JP 2000252411A JP 5500499 A JP5500499 A JP 5500499A JP 5500499 A JP5500499 A JP 5500499A JP 2000252411 A JP2000252411 A JP 2000252411A
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JP
Japan
Prior art keywords
wafer
semiconductor device
conductive metal
dicing
le
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5500499A
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Japanese (ja)
Inventor
Takashi Nakajima
中島高士
Original Assignee
Mitsui High Tec Inc
株式会社三井ハイテック
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Application filed by Mitsui High Tec Inc, 株式会社三井ハイテック filed Critical Mitsui High Tec Inc
Priority to JP5500499A priority Critical patent/JP2000252411A/en
Publication of JP2000252411A publication Critical patent/JP2000252411A/en
Application status is Granted legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Abstract

PROBLEM TO BE SOLVED: To enable high density mounting of a thin and small semiconductor device and improve connection reliability, by forming longitudinal wiring lines electrically connecting chip wiring leads in wafers of the respective layers in the outer peripheral part and the inside of a laminated member of the wafers. SOLUTION: After wafers 5 are laminated by a desired number of steps, insulating adhesive agent 6 is arranged on the upper surface of the laminated wafers, and through holes 8 are bored in dicing parts of a wafer laminated member 7. In order to electrically connect chips with each other in the laminated wafers 5, conducting metals 9 (aluminum, copper, etc.), are formed by sputtering, plating, etc., on inner walls of the through holes 8. Resist 10 is spread on the upper surface of the wafer laminated member 7, exposed to light, developed and etched, and the conducting metals 9 stuck on parts except the through holes 8 are eliminated. The conducting metals 9 covering the inner walls of the through holes 8 form longitudinal lines. As a result, a stacked semiconductor device 14 can be thinned and miniaturized, high density mounting can be realized, and connection reliability can be improved.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明はスタックド半導体装置及びその製造方法に関する。 The present invention relates to relates to stacked semiconductor device and a manufacturing method thereof.

【0002】 [0002]

【従来の技術】半導体装置は実装密度を高めることが要請されている。 BACKGROUND OF THE INVENTION Semiconductor devices are requested to increase the mounting density. 半導体装置の超高密度実装のために半導体チップを複数積層したスタックド半導体装置が提案されている。 Stacked semiconductor device where the semiconductor chips are stacked for ultrahigh-density mounting a semiconductor device has been proposed.

【0003】従来提案されているスタックド半導体装置は半導体チップを搭載したキャリアが複数個積層された構造よりなる半導体パッケージであって、プリント基板、多層基板或は配線パタ−ンを設けたフィルムが前記キャリアとして用いられ、これに半導体チップを搭載し、複数積層したものである。 Conventionally proposed stacked semiconductor device comprising a semiconductor package carrier having a semiconductor chip mounted is formed of a plurality laminated structure, a printed circuit board, multilayer board or wiring patterns - the provided film is the emission used as a carrier, to which a semiconductor chip is mounted, it is obtained by stacking a plurality. これでは実装密度は高まるが、重ね合わされた半導体装置は厚くなり薄型化や小型化に問題がある。 This packing density is increased in but superimposed semiconductor device is problematic becomes thinner and miniaturized thick.

【0004】 [0004]

【この発明が解決しようとする課題】最近、薄型及び小型で且つ超高密度実装が出来る半導体装置への要請が益々強くなっているが、このニ−ズに十分に適合できるスタックド半導体装置が見当たらないのが実状である。 The present invention to which the present invention is to provide a Recently, demand for semiconductor devices that can and ultra-high-density mounting a flat-screen and small has become more and more strongly, this two - missing is stacked semiconductor device which can be well adapted to's no of is actual situation. また、スタックド半導体装置の製造は半導体チップの積層がキャリア単位でなされることから高度の熟練を要し且つ生産性が低いという課題がある。 The manufacturing of stacked semiconductor device has a problem of low and productivity require a high degree of skill from the stack of semiconductor chips are made in the carrier units.

【0005】本発明は薄型且つチップサイズの小型で超高密度実装がなされるスタックド半導体装置を得ること、またこれを生産性よく製造することを目的とする。 [0005] The present invention is to obtain a thin and stacked semiconductor device ultra high density mounting is performed in a small chip size, and also aims to produce good productivity this.

【0006】 [0006]

【課題を解決するための手段】本発明の要旨は、ウエハ−が絶縁層を介在して複数段積層され、該ウエハ−の積層体の外周及び内部に、各階層のウエハ−内のチップの配線リ−ドを電気的に接続する縦の配線ラインを設けているスタックド半導体装置にある。 Means for Solving the Problems The gist of the present invention, the wafer - is a plurality of stages stacked by interposing the insulating layer, the wafer - the outer periphery and the interior of the laminate, in each layer the wafer - the chips routing resources - in stacked semiconductor device is provided with the vertical interconnection line that electrically connects the de.

【0007】製造方法に関する他の要旨は、ウエハ−を絶縁層を介在して複数段積層してなるスタックド半導体装置の製造方法において、接着フィルムに外部接続パタ−ンを形成したパタ−ンフィルムをはり付け、該パタ− [0007] Other aspect of manufacturing method, the wafer - method of manufacturing a stacked semiconductor device in which a plurality of stages stacked by interposing the insulating layer, the external connection pattern to the adhesive film - the emission film - pattern forming the down Paste, the pattern -
ンフィルムにウェハ−を絶縁性接着材を介して積層し、 Wafer down film - the laminated through an insulating adhesive material,
前記ウェハ−を所望サイズにダイシングし、該ダイシングしたウエハ−をシリコンエッチングして薄くするとともにダイシングみぞの間隔を広げ且つ配線リ−ドを残し、該シリコンエッチングしたウエハ−上に絶縁性接着材を介して次のウエハ−を積層し、該積層したウエハ− The wafer - the diced into a desired size, the diced wafer - a and wiring re increasing spacing of the dicing groove with thinning by silicon etching - leaving de, the silicon etched wafer - an insulating adhesive material on through to next wafer - wafer was laminated and the laminated -
をダイシングし、シリコンエッチングし、絶縁性接着材を塗布し、前記ウエハ−の積層、ダイシング、シリコンエッチング及び絶縁性接着材の塗布を繰り返し行って所望複数段のウェハ−積層体とし、スル−ホ−ルを前記ダイシング箇所部及びダイシング箇所部以外のチップ近傍に穿設し、該スル−ホ−ルに導電金属を設けて各階層のウエハ−内のチップを電気的に接続する縦の配線ラインを形成し、前記接着フィルムを剥ぎ前記パタ−ンフィルムの外部接続パタ−ンに外部接続端子を設け、前記縦の配線ラインが形成されたダイシング部をカットして分割することを特徴とするスタックド半導体装置の製造方法にある。 The diced, and silicon etching, the insulating adhesive material is applied, the wafer - the laminate, dicing, by repeating the coating of silicon etching and insulating adhesive material desired plurality of stages of the wafer - a layered structure - ho - bored Le to tip vicinity other than the dicing portion unit and the dicing portion unit, the sul - e - vertical interconnection lines for electrically connecting the chips in - providing a conductive metal each layer of the wafer to Le forming a said adhesive film strip the pattern - external connection pattern of emission film - the external connection terminals provided on the emission, characterized by dividing by cutting the dicing portion wiring line is formed of the vertical stacked in a method of manufacturing a semiconductor device.

【0008】また他の要旨は、前記製造方法の要旨における絶縁性接着材を介して積層したウェハ−を所望サイズにダイシングし、該ダイシングしたウエハ−をシリコンエッチングして薄くするとともにダイシングみぞの間隔を広げることに代えて、前記絶縁性接着材を介して積層したウェハ−上にレジストを設け、次いで露光し、現像し、シリコンエッチングして当該ウェハ−を所望大きさにダイシングするところにある。 [0008] Other aspect, the wafer was laminated with an insulating adhesive material in the gist of the production method - a diced into a desired size, the diced wafer - apart dicing grooves with thinning by silicon etching instead of expanding the said insulating adhesive material the wafers were laminated via - the resist provided above, then exposed and developed, and silicon etching the wafer - there is to be diced into a desired size.

【0009】 [0009]

【発明の実施の形態】次に、本発明の1実施例について図面を参照して説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, description with reference to the drawings an embodiment of the present invention. 図1は本発明の1実施例におけるスタックド半導体装置の製造過程を説明するための図、図2は前記図1に続くスタックド半導体装置の製造過程を説明するための図、図3は本発明によるスタックド半導体装置の1例を示す図である。 1 is a diagram for explaining a manufacturing process of a stacked semiconductor device in one embodiment of the present invention, diagram for explaining a manufacturing process of a stacked semiconductor device 2 subsequent to FIG. 1, according to FIG. 3 according to the present invention is a view showing an example of a stacked semiconductor device.

【0010】図1において、(a)における1は接着フィルムで、スタックド半導体装置を製造する際の支持材であり、その両側には強度確保等のためリング2が設けられている。 [0010] In FIG. 1, 1 is an adhesive film in (a), a support material in the manufacture of stacked semiconductor device, the ring 2 is provided for ensuring the strength or the like on both sides. 該接着フィルム1に同図の(b)に示すように外部接続パタ−ン3を設けたパタ−ンフィルム4を貼り付ける。 Adhesive film 1 in the drawing of (b) are shown as external connection pattern - patterns and the down 3 provided - pasting down film 4. この場合、外部接続パタ−ン3が接着フィルム1と接着されるものでは前記外部接続パタ−ン3上には他の絶縁樹脂で端子部以外はカバ−されており、他方、パタ−ンフィルム面4と接着フィルム1が接着される場合には前記外部接続パタ−ン3面にはそのまま絶縁性接着材でウェハ−と接着される。 In this case, the external connection pattern - are, on the other hand, pattern - - intended to emission 3 is adhered to the adhesive film 1 the external connection pattern - down 3 except terminal portions with other insulating resin on cover down film the three sides down the wafer as it is insulating adhesive material - - are bonded the external connection pattern in the case of surface 4 and the adhesive film 1 is adhered. この際には前記接着フィルム1に開口部が形成される。 The opening in the adhesive film 1 is formed when.

【0011】その後、同図の(c)に示すようにウェハ−5が絶縁性接着材6を介して前記パタ−ンフィルム4 [0011] Thereafter, the wafer -5 as shown in the same figure (c) is the pattern through the insulating adhesive material 6 - emission film 4
に貼り付けられる。 It is adhered to. 該貼り付けられたウェハ−5を同図の(d)に示すようにダイシングして分割する。 The 該貼 Ri lighted wafer -5 was split by dicing as shown in the same figure (d).

【0012】次いで、前記ウエハ−5に対してシリコンエッチングを行い薄くするとともにダイシングみぞの間隔を広げ、同図の(e)に示すようにする。 [0012] Then, an increasing spacing dicing grooves with thinning performed silicon etching to said wafer -5, to exhibit in the same figure (e). このとき該シリコンエッチングで露呈したウェハ−5のチップの配線リ−ドは残される。 In this case the chips of the wafer -5 were exposed with the silicon etching wiring Li - De is left. その後、絶縁性接着材6を前記ウエハ−5上にスピンコ−タ−等で塗布し、次のウエハ− Then, a spin of the insulating adhesive material 6 on the wafer -5 - data - and applied in such, next wafer -
5をキャリア等基板を介在させることなく同図の(f) 5 of the drawing without intervention of the carrier such as a substrate (f)
のように貼り付け積層する。 To Paste stacked like.

【0013】次いで、前述と同様に前記ウエハ−のダイシング、シリコンエッチング、絶縁性接着材の塗布を、 [0013] Then, the wafer in the same manner as described above - the dicing, the silicon etching, a coating of insulating adhesive material,
繰り返して行いウエハ−を所望段数積層する。 Repeatedly perform wafer - to the desired number of stages stacked. この実施例ではウエハ−5を同図の(h)に示すように2段積層しているが、その積層数は3層、4層、5層等と任意にできる。 Although this embodiment has a wafer -5 laminated two stages as shown in the figure (h), the number of stacked layers 3 layers, 4 layers, can optionally and five layers like.

【0014】前記のようにウェハ−5を所望段積層した後、その上面に絶縁性接着材を設け図2の(i)に示すようにウェハ−積層体7のダイシング箇所にスル−ホ− [0014] After the desired stage stacked wafers -5 as described above, the wafer as shown in the upper surface thereof an insulating adhesive material and provided in Figure 2 (i) - to the dicing position of the stacked body 7 - e -
ル8を穿設する。 Bored Le 8. 該穿設はドリル、レ−ザ、或はケミカルエッチング等によりなされる。 Perforations set drill, Le - The, or made by chemical etching or the like. また、図面には示していないが各ウェハ−積層体7のウェハ−5内のチップ間で共通でない信号ラインを形成するためにスル−ホ−ルを穿設する。 Further, although not shown in the drawings each wafer - Sul to form the signal lines are not common between chips within the wafer -5 laminate 7 - e - drilling Le.

【0015】その後、前記積層したウェハ−5内のチップ同志を電気的に接続するため同図の(j)のようにスル−ホ−ル8の内壁に導電金属9、例えばアルミニュウムや銅等をスパッタ−或はめっき等により設ける。 The conductive metal 9 on the inner wall of Le 8, for example, aluminum or copper - [0015] Then, the sul as stacked in the figure for electrically connecting the chip comrades in the wafer -5 (j) - E sputtering - or provided by plating or the like.

【0016】前記導電金属9を設ける際にはウェハ−積層体7の上面等にも当該導電金属9が付着するので、この余分のものを除去すべく同図の(k)に示すようにレジスト10を前記ウェハ−積層体7の上面に塗布し、露光し、現像し及びエッチングしてスル−ホ−ル8以外に付着した導電金属9を取り除く。 [0016] When providing the electrically conductive metal 9 wafer - since the conductive metal 9 adheres to the upper surface or the like of the stacked body 7, the resist as shown in (k) in FIG. In order to remove those in this extra 10 the wafer - is applied to the upper surface of the stacked body 7, exposed, and developed and etched sul - Ho - removing conductive metal 9 adhering to other than Le 8. 該取り除き後を同図の(l)に示しているが、スル−ホ−ル8内壁を被覆した導電金属9が縦の配線ラインを形成している。 Although after removing the show in the same figure (l), sul - Ho - conductive metal 9 coated with Le 8 inner wall forms a vertical wiring lines. なお、配線ラインはアディティブ法によって必要部分にのみ設けてもよい。 The wiring lines may be provided only in a necessary portion by additive process. さらに、前記アルミニュウムにニッケルめっき等の耐腐食金属がコ−トされる場合もある。 Further, corrosion and nickel plating to the aluminum is co - sometimes be bets.

【0017】その後、前記接着フィルム1をウェハ−積層体7から剥いで、前記パタ−ンフィルム4の下面に外部接続端子11、例えば半田ボ−ル、バンプ、或はランド等を同図の(m)に示すように設ける。 [0017] Then, the adhesive film 1 wafer - yes a laminate 7, the pattern - emission film external connection terminal 11 to the lower surface of the 4, for example, a solder ball - le, bumps, or the lands or the like of FIG. ( provided as shown in m).

【0018】その後、必要に応じて接着保持フィルム1 [0018] After that, the adhesive if desired retention film 1
2をウェハ−積層体7の外部接続端子11設置の反対側に貼り付けてから、前記導電金属9を設けたスル−ホ− 2 wafer - the paste on the opposite side of the external connection terminals 11 disposed in the stacked body 7, provided with the conductive metal 9 - e -
ル8部の切断位置13をカットしてウェハ−積層体7を個々に分割し、スタックド半導体装置14が製造される。 Cut the cutting position 13 of the 8 parts Le wafer - to divide the stacked body 7 individually, stacked semiconductor device 14 is manufactured. また、図3には、ウェハ−5を4層積層したスタックド半導体装置14を示している。 Further, FIG. 3 shows a stacked semiconductor device 14 obtained by stacking wafers -5 four layers.

【0019】このように製造されたスタックド半導体装置14はウェハ−5がキャリア等の基板を介在せずに積層されたものであるから薄く、且つ小型である。 [0019] The thus produced stacked semiconductor device 14 is thin because those wafers -5 are stacked without interposing a substrate such as a carrier, is and compact. また各ウェハ−5内のチップの電気的な接続が外周に位置するダイシング部、及びダイシング箇所部以外のチップ近傍のスル−ホ−ルの内面に設けた導電金属9でなされるので、接続の信頼性がすぐれる。 The dicing unit electrical connection of the chip in each wafer -5 are located on the outer periphery, and the tip vicinity of the other dicing point unit - E - since it is made of a conductive metal 9 provided on the inner surface of the Le, the connection reliability is excellent. さらに該スタックド半導体装置13はウェハ−を絶縁性接着材を介しての積層、 Furthermore the stacked semiconductor device 13 is a wafer - stacking of the via insulating adhesive,
ダイシング、スル−ホ−ル穿設、スル−ホ−ル内への導電金属層の形成により製造されるので、高度の熟練を要さず生産性よく製造される。 Dicing, sul - Ho - Le bored Sul - Ho - because it is produced by the formation of the conductive metal layer into Le, it is produced with good productivity without requiring a high degree of skill.

【0020】前記実施例では、絶縁性接着材6を介して積層したウェハ−5をダイシングし、次いでシリコンエッチングして当該ウェハ−5を薄くするとともにダイシングみぞの間隔を広げたが、ウェハ−5が予め薄くされていればこれに代えて、前記積層したウェハ−上にレジストを設け、次いで露光し、現像し、シリコンエッチングして当該ウェハ−を所望大きさにダイシングしてもよい。 [0020] In the above embodiment, dicing the wafer -5 laminated via an insulating adhesive material 6 and then is spread apart dicing grooves with by silicon etching thinning the wafer -5, wafer -5 There Alternatively if it is pre-thinned, the stacked wafers - provided a resist on and then exposed and developed, the wafer by silicon etching - may also be diced into a desired size.

【0021】 [0021]

【発明の効果】本発明によればキャリアを用いることなくウエハ−が絶縁性接着材を介在して複数段積層されてスタックド半導体装置を構成しているので、スタックド半導体装置の厚みを薄くできる。 Wafer without using a carrier according to the present invention - because constitutes a plurality of stages stacked in a stacked semiconductor device by interposing the insulating adhesive material, can reduce the thickness of the stacked semiconductor device. また、ウエハ−を複数段積層したウェハ−積層体の外周に各階層のウエハ−内のチップ配線リ−ドを電気的に接続する縦の配線ラインを設けているので接続の信頼性が高く、小型で高密度実装がなされるスタックド半導体装置が得られる。 Further, the wafer - a plurality of stages stacked wafers - reliable connection since the provided vertical wiring lines for electrically connecting the de - chip line Li in - each layer of the wafer to the outer periphery of the stack stacked semiconductor device compact high-density mounting is performed is obtained.

【0022】また、本発明の製造方法によれば前述のように、高度の熟練を要さず生産性よく製造できる等の効果がある。 Further, as described above according to the production method of the present invention, there is an effect such that can be manufactured productivity without requiring a high degree of skill.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の1実施例におけるスタックド半導体装置の製造過程を説明するための図。 Diagram for the manufacturing process will be described in stacked semiconductor device in one embodiment of the present invention; FIG.

【図2】前記図1に続くスタックド半導体装置の製造過程を説明するための図。 Figure 2 is a view for explaining a manufacturing process of a stacked semiconductor device continued from FIG. 1.

【図3】本発明によるスタックド半導体装置を示す図。 It shows a stacked semiconductor device according to the invention, FIG.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 接着フィルム 2 リング 3 外部接続パタ−ン 4 パタ−ンフィルム 5 ウェハ− 6 絶縁性接着材 7 ウェハ−積層体 8 スル−ホ−ル 9 導電金属 10 レジスト 11 外部接続端子 12 接着保持フィルム 13 切断位置 14 スタックド半導体装置 1 adhesive film 2 ring 3 externally connected patterns - down 4 pattern - emission film 5 wafers - 6 insulating adhesive material 7 wafer - laminate 8 - E - le 9 conductive metal 10 resist 11 external connection terminal 12 adhesive holding film 13 cut position 14 stacked semiconductor device

Claims (5)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 ウエハ−が絶縁性接着材を介在して複数段積層され、該ウエハ−の積層体の外周及び内部に、各階層のウエハ−内のチップの配線リ−ドを電気的に接続する縦の配線ラインを設けていることを特徴とするスタックド半導体装置。 1. A wafer - is a plurality of stages stacked by interposing an insulating adhesive material, the wafer - the outer periphery and the interior of the laminate, in each layer wafers - the chip wiring Li - de electrically the stacked wherein a is provided with the vertical interconnection lines connecting.
  2. 【請求項2】 ウエハ−を絶縁層を介在して複数段積層してなるスタックド半導体装置の製造方法において、接着フィルムに外部接続パタ−ンを形成したパタ−ンフィルムをはり付け、該パタ−ンフィルムにウェハ−を絶縁性接着材を介して積層し、前記ウェハ−を所望サイズにダイシングし、該ダイシングしたウエハ−をシリコンエッチングして薄くするとともにダイシングみぞの間隔を広げ且つ配線リ−ドは残し、前記シリコンエッチングしたウエハ−上に絶縁性接着材を介して次のウエハ−を積層し、該積層したウエハ−をダイシングし、シリコンエッチングし、該ウエハ−の積層、ダイシング、シリコンエッチング及び絶縁性接着材の塗布を繰り返し行って所望複数段のウェハ−積層体とし、スル−ホ−ルを前記ダイシング箇所部及び 2. A wafer - a method of manufacturing a stacked semiconductor device in which a plurality of stages stacked by interposing an insulating layer, an external connection pattern to the adhesive film - forming the emission pattern - emission film Paste and the pattern - wafer down film - the laminated through an insulating adhesive material, the wafer - the diced into a desired size, the diced wafer - the increasing spacing of the dicing groove with thinning by silicon etching and wiring Li - de leaves, the silicon etched wafer - through the insulating adhesive material on the next wafer - laminating, the laminated wafer - diced, and silicon etching, the wafer - stacking, dicing, and silicon etching wafer of the desired plurality of stages by repeating the coating of insulating adhesive material - a layered structure - Ho - the Le dicing portion unit and ダイシング箇所部以外のチップ近傍に穿設し、該スル−ホ−ルに導電金属を設けて各階層のウエハ−内のチップを電気的に接続する縦の配線ラインを形成し、前記接着フィルムを剥ぎ前記パタ−ンフィルムの外部接続パタ−ンに外部接続端子を設け、前記縦の配線ラインが形成されたダイシング部をカットして分割することを特徴とするスタックド半導体装置の製造方法。 Drilled in tip vicinity other than the dicing location portion, the sul - E - by a conductive metal provided Le of each layer wafer - chip to form a vertical wiring lines for electrically connecting the inside, the adhesive film external connection pattern of emission film - - the external connection terminals provided on emissions, method of manufacturing a stacked semiconductor device characterized by dividing by cutting the dicing portion wiring lines are formed of the longitudinal said pattern strip.
  3. 【請求項3】 前記ウェハ−積層体のスル−ホ−ルへの導電金属の設け方が、スパッタリング又はめっきでなされ、該導電金属の被覆上にレジストコ−トを設け、該レジストコ−トを露光、現像して、露呈した導電金属をエッチングしてスル−ホ−ル以外の導電金属を除去することを特徴とする請求項2記載のスタックド半導体装置の製造方法。 Wherein the wafer - Sur laminate - e - method of providing conductive metal into Le is made by sputtering or plating, Rejisutoko on the coating of conductive metal - the door is provided, the Rejisutoko - DOO exposure and developed to be etched the exposed conductive metal - e - method of manufacturing a stacked semiconductor device according to claim 2, wherein removing the conductive metal other than Le.
  4. 【請求項4】 ウエハ−を絶縁層を介在して複数段積層してなるスタックド半導体装置の製造方法において、接着フィルムに外部接続パタ−ンを形成したパタ−ンフィルムをはり付け、該パタ−ンフィルムにウェハ−を絶縁性接着材を介して積層し、該ウエハ−上にレジストを設け、次いで、露光し、現像し、シリコンエッチングしてウエハ−を所望大きさにダイシングし且つ配線リ−ドは残し、該ウエハ−の上に絶縁性接着材を介して次のウエハ−の積層、該ウエハ−へのレジストの設け、露光、現像、シリコンエッチングによるダイシング及び絶縁性接着材塗布を繰り返し行って所望複数段のウェハ−積層体とし、スル−ホ−ルを前記ダイシング箇所部及びダイシング箇所部以外のチップ近傍に穿設し、該スル−ホ−ルに導電金属を設けて The method of manufacturing a stacked semiconductor device in which a plurality of stages stacked by interposing the insulating layer, the external connection pattern to the adhesive film - - 4. The wafer was formed down pattern - emission film Paste and the pattern - was laminated via an insulating adhesive material, the wafer - - wafers down film resist provided above, then exposed, developed, and silicon etching to the wafer - the diced into a desired size and wiring Li - de leaves, the wafer - next wafer via an insulating adhesive material on the - stacking, the wafer - resist provided for to, exposure, development, repeated dicing and insulating adhesive material applied by silicon etching a laminated body, sul - - e - drilled Le to tip vicinity other than the dicing portion unit and the dicing portion unit, the sul - e - by a conductive metal provided Le desired plurality of stages of wafers Te 各階層のウエハ−内のチップを電気的に接続する縦の配線ラインを形成し、前記接着フィルムを剥いで前記パタ−ンフィルムの外部接続パタ−ンに外部接続端子を設け、前記縦の配線ラインが形成されたダイシング部をカットして分割することを特徴とするスタックド半導体装置の製造方法。 Each layer of the wafer - the vertical interconnection line that electrically connects the chip to form, said yes adhesive film pattern - emission film external connection pattern of - the external connection terminals provided on emissions, the vertical wirings method for manufacturing a stacked semiconductor device characterized by dividing by cutting the dicing unit lines are formed.
  5. 【請求項5】 前記ウェハ−積層体のスル−ホ−ルへの導電金属の設け方が、スパッタリング又はめっきでなされ、該導電金属の被覆上にレジストコ−トを設け、該レジストコ−トを露光、現像し、露呈した導電金属をエッチングしてスル−ホ−ル以外の導電金属を除去することを特徴とする請求項5記載のスタックド半導体装置の製造方法。 Sur laminate - - wherein said wafer E - method of providing conductive metal into Le is made by sputtering or plating, Rejisutoko on the coating of conductive metal - the door is provided, the Rejisutoko - DOO exposure , developed, sul by etching the exposed conductive metal - e - method of manufacturing a stacked semiconductor device according to claim 5, wherein removing the conductive metal other than Le.
JP5500499A 1999-03-03 1999-03-03 Stacked semiconductor device and its manufacture Granted JP2000252411A (en)

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DE10101875A1 (en) * 2001-01-16 2002-08-01 Infineon Technologies Ag Electronic component having successive stacked semiconductor chips
JP2007158331A (en) * 2005-11-30 2007-06-21 Freescale Semiconductor Inc Packaging method of semiconductor device
JP2007266572A (en) * 2006-03-29 2007-10-11 Hynix Semiconductor Inc Stack type semiconductor package
US7378732B2 (en) 2003-04-15 2008-05-27 Shinko Electric Industries Co., Ltd. Semiconductor package
JP2009065111A (en) * 2007-09-05 2009-03-26 Headway Technologies Inc Method of manufacturing electronic component package
JP2010502006A (en) * 2006-08-22 2010-01-21 トロワデー、プリュ3D Plus 3-dimensional collective production method for an electronic module
KR100943009B1 (en) 2002-06-14 2010-02-18 신꼬오덴기 고교 가부시키가이샤 Semiconductor device and method of manufacturing the same

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10101875A1 (en) * 2001-01-16 2002-08-01 Infineon Technologies Ag Electronic component having successive stacked semiconductor chips
US6686648B2 (en) 2001-01-16 2004-02-03 Infineon Technologies Ag Electronic component with stacked semiconductor chips and method of producing the component
US6872594B2 (en) 2001-01-16 2005-03-29 Infineon Technologies Ag Method of fabricating an electronic component
DE10101875B4 (en) * 2001-01-16 2006-05-04 Infineon Technologies Ag Electronic component having successive stacked semiconductor chips and process for its preparation
KR100943009B1 (en) 2002-06-14 2010-02-18 신꼬오덴기 고교 가부시키가이샤 Semiconductor device and method of manufacturing the same
US7378732B2 (en) 2003-04-15 2008-05-27 Shinko Electric Industries Co., Ltd. Semiconductor package
JP2007158331A (en) * 2005-11-30 2007-06-21 Freescale Semiconductor Inc Packaging method of semiconductor device
JP2007266572A (en) * 2006-03-29 2007-10-11 Hynix Semiconductor Inc Stack type semiconductor package
JP2010502006A (en) * 2006-08-22 2010-01-21 トロワデー、プリュ3D Plus 3-dimensional collective production method for an electronic module
KR101424298B1 (en) 2006-08-22 2014-08-01 3디 플러스 Process for the collective manufacturing of electronic 3d modules
JP2009065111A (en) * 2007-09-05 2009-03-26 Headway Technologies Inc Method of manufacturing electronic component package

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