JP2000252411A - Stacked semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable high density mounting of a thin and small semiconductor device and improve connection reliability, by forming longitudinal wiring lines electrically connecting chip wiring leads in wafers of the respective layers in the outer peripheral part and the inside of a laminated member of the wafers. SOLUTION: After wafers 5 are laminated by a desired number of steps, insulating adhesive agent 6 is arranged on the upper surface of the laminated wafers, and through holes 8 are bored in dicing parts of a wafer laminated member 7. In order to electrically connect chips with each other in the laminated wafers 5, conducting metals 9 (aluminum, copper, etc.), are formed by sputtering, plating, etc., on inner walls of the through holes 8. Resist 10 is spread on the upper surface of the wafer laminated member 7, exposed to light, developed and etched, and the conducting metals 9 stuck on parts except the through holes 8 are eliminated. The conducting metals 9 covering the inner walls of the through holes 8 form longitudinal lines. As a result, a stacked semiconductor device 14 can be thinned and miniaturized, high density mounting can be realized, and connection reliability can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a stacked semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor device is required to have a higher mounting density. 2. Description of the Related Art A stacked semiconductor device in which a plurality of semiconductor chips are stacked for ultra-high-density mounting of a semiconductor device has been proposed.

A conventionally proposed stacked semiconductor device is a semiconductor package having a structure in which a plurality of carriers on which semiconductor chips are mounted are stacked, and a printed board, a multilayer board, or a film provided with a wiring pattern is formed by the above-described film. It is used as a carrier, on which a semiconductor chip is mounted and a plurality of semiconductor chips are stacked. Although this increases the mounting density, the stacked semiconductor devices become thicker and have problems in thinning and miniaturization.

[0004]

Recently, there has been an increasing demand for a semiconductor device that is thin, small, and capable of ultra-high-density mounting. However, when a stacked semiconductor device that can sufficiently meet this need is found. There is no actual situation. In addition, the production of a stacked semiconductor device has a problem that a high degree of skill is required and productivity is low because lamination of semiconductor chips is performed in units of carriers.

It is an object of the present invention to provide a stacked semiconductor device which is thin and small in chip size and can be mounted at a very high density, and which is manufactured with high productivity.

[0006]

SUMMARY OF THE INVENTION The gist of the present invention is that a plurality of wafers are laminated with an insulating layer interposed therebetween, and the outer periphery and the inside of the laminated body of the wafers are provided with the chips of the wafers of each layer. The stacked semiconductor device is provided with vertical wiring lines for electrically connecting the wiring leads.

[0007] Another gist of the manufacturing method is that in a method of manufacturing a stacked semiconductor device in which wafers are stacked in a plurality of stages with an insulating layer interposed, a pattern film in which an external connection pattern is formed on an adhesive film is used. Attach, the pattern
Laminating a wafer on an insulating film via an insulating adhesive,
The wafer is diced to a desired size, the diced wafer is thinned by silicon etching, the distance between dicing grooves is widened, and wiring leads are left, and an insulating adhesive is applied on the silicon-etched wafer. The next wafer is stacked through the
, Silicon etching, application of an insulating adhesive, and repeated lamination of the wafer, dicing, silicon etching and application of the insulating adhesive to form a desired multi-layer wafer-laminated product, A vertical wiring line for forming a hole in the vicinity of the chip other than the dicing portion and the dicing portion, and providing a conductive metal on the through hole to electrically connect the chips in the wafers of each layer. Wherein the adhesive film is peeled off, an external connection terminal is provided on an external connection pattern of the pattern film, and a dicing portion in which the vertical wiring line is formed is cut and divided. A method for manufacturing a semiconductor device.

Another aspect is that the laminated wafer is diced to a desired size via the insulating adhesive in the aspect of the above-described manufacturing method, the diced wafer is thinned by silicon etching, and the distance between the dicing grooves is reduced. Instead, a resist is provided on the wafers laminated via the insulating adhesive, then exposed, developed, and silicon-etched to dice the wafers to a desired size.

[0009]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram for explaining a manufacturing process of a stacked semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining a manufacturing process of a stacked semiconductor device subsequent to FIG. 1, and FIG. FIG. 3 is a diagram illustrating an example of a stacked semiconductor device.

In FIG. 1, reference numeral 1 in FIG. 1A denotes an adhesive film, which is a support member for manufacturing a stacked semiconductor device. Rings 2 are provided on both sides of the support member for securing strength and the like. A pattern film 4 provided with an external connection pattern 3 is attached to the adhesive film 1 as shown in FIG. In this case, when the external connection pattern 3 is bonded to the adhesive film 1, the external connection pattern 3 is covered with another insulating resin except for the terminal portions, while the pattern film is When the surface 4 and the adhesive film 1 are bonded, the surface of the external connection pattern 3 is directly bonded to the wafer with an insulating adhesive. At this time, an opening is formed in the adhesive film 1.

Thereafter, as shown in FIG. 1C, the wafer 5 is placed on the pattern film 4 via an insulating adhesive 6.
Pasted in. The attached wafer 5 is diced and divided as shown in FIG.

Next, the wafer 5 is subjected to silicon etching to make it thinner and the dicing grooves are widened, as shown in FIG. At this time, the wiring leads of the chips of the wafer 5 exposed by the silicon etching are left. Thereafter, an insulating adhesive 6 is applied on the wafer 5 by a spin coater or the like, and the next wafer is coated.
5 without interposing a substrate such as a carrier.
Paste and laminate as shown.

Next, dicing of the wafer, silicon etching, and application of an insulating adhesive are performed in the same manner as described above.
This process is repeated to stack a desired number of wafers. In this embodiment, the wafers 5 are stacked in two stages as shown in FIG. 1H, but the number of stacked layers can be arbitrarily set to three, four, five, or the like.

After laminating the wafer 5 in the desired step as described above, an insulating adhesive is provided on the upper surface thereof, and a through-hole is formed on the dicing portion of the wafer laminated body 7 as shown in FIG.
Hole 8 is drilled. The drilling is performed by a drill, a laser, a chemical etching or the like. Although not shown in the drawing, a through hole is formed in order to form a signal line which is not common between chips in the wafer 5 of each wafer-stacked body 7.

Thereafter, a conductive metal 9, such as aluminum or copper, is applied to the inner wall of the through hole 8 as shown in FIG. It is provided by sputtering or plating.

When the conductive metal 9 is provided, the conductive metal 9 adheres also to the upper surface of the wafer-stacked body 7 and the like. Therefore, as shown in FIG. 10 is applied to the upper surface of the wafer-stacked body 7, exposed, developed and etched to remove the conductive metal 9 adhering other than the through-hole 8. As shown in FIG. 1 (l) after the removal, the conductive metal 9 covering the inner wall of the through-hole 8 forms a vertical wiring line. Note that the wiring lines may be provided only in necessary portions by the additive method. Further, a corrosion-resistant metal such as nickel plating may be coated on the aluminum.

Thereafter, the adhesive film 1 is peeled off from the wafer laminated body 7, and external connection terminals 11, for example, solder balls, bumps, lands or the like are formed on the lower surface of the pattern film 4 as shown in FIG. m).

Thereafter, if necessary, the adhesive holding film 1
2 is attached to the wafer stack 7 on the opposite side of the external connection terminals 11, and then the through-hole provided with the conductive metal 9 is attached.
The wafer-stacked body 7 is divided into individual parts by cutting the cutting positions 13 of the eight parts, and a stacked semiconductor device 14 is manufactured. FIG. 3 shows a stacked semiconductor device 14 in which four wafers 5 are stacked.

The stacked semiconductor device 14 manufactured in this manner is thin and small because the wafers 5 are stacked without interposing a substrate such as a carrier. Further, since the electrical connection of the chips in each wafer 5 is made by the conductive metal 9 provided on the inner surface of the through hole near the chip other than the dicing portion located at the outer periphery and the dicing portion, the connection of the connection is established. Excellent reliability. Further, the stacked semiconductor device 13 laminates the wafer via an insulating adhesive,
Since it is manufactured by dicing, perforating a through hole, and forming a conductive metal layer in the through hole, it is manufactured with high productivity without requiring a high level of skill.

In the above embodiment, the laminated wafer 5 was diced via the insulating adhesive 6, and then silicon etching was performed to reduce the thickness of the wafer 5 and widen the dicing grooves. Alternatively, if is previously thinned, a resist may be provided on the laminated wafer, then exposed, developed, and silicon etched to dice the wafer to a desired size.

[0021]

According to the present invention, a stacked semiconductor device is formed by laminating a plurality of wafers via an insulating adhesive without using a carrier, so that the thickness of the stacked semiconductor device can be reduced. Further, since the vertical wiring lines for electrically connecting the chip wiring leads in the wafers of each layer are provided on the outer periphery of the wafer-stacked body in which the wafers are stacked in a plurality of stages, the connection reliability is high, A stacked semiconductor device which is small and can be mounted at high density can be obtained.

Further, according to the production method of the present invention, as described above, there is an effect that the production can be performed with high productivity without requiring a high level of skill.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a manufacturing process of a stacked semiconductor device according to one embodiment of the present invention.

FIG. 2 is a view for explaining a manufacturing process of the stacked semiconductor device following FIG. 1;

FIG. 3 is a diagram showing a stacked semiconductor device according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Adhesive film 2 Ring 3 External connection pattern 4 Pattern film 5 Wafer 6 Insulating adhesive 7 Wafer laminated body 8 Through hole 9 Conductive metal 10 Resist 11 External connection terminal 12 Adhesion holding film 13 Cutting Position 14 Stacked semiconductor device

Claims (5)

[Claims] A plurality of wafers are stacked with an insulating adhesive interposed therebetween, and the wiring leads of the chips in each level of the wafer are electrically connected to the outer periphery and inside of the stacked body of the wafers. A stacked semiconductor device comprising a vertical wiring line for connection. 2. A method for manufacturing a stacked semiconductor device comprising a plurality of stacked wafers with an insulating layer interposed therebetween, wherein a pattern film having an external connection pattern formed thereon is attached to an adhesive film. A wafer is laminated on an insulating film via an insulating adhesive, the wafer is diced to a desired size, the diced wafer is silicon-etched to reduce the thickness, the distance between the dicing grooves is increased, and wiring leads are provided. The next wafer is laminated on the silicon-etched wafer via an insulating adhesive, the laminated wafer is diced, silicon-etched, and the wafer is laminated, dicing, silicon etching, and the like. By repeatedly applying the insulating adhesive, a desired multi-stage wafer-laminated body is formed, and the through-hole is formed by the dicing portion and A hole is formed near the chip other than the dicing portion, and a conductive metal is provided on the through-hole to form vertical wiring lines for electrically connecting the chips in the wafer of each layer. A method of manufacturing a stacked semiconductor device, wherein an external connection terminal is provided on an external connection pattern of the pattern film, and a dicing portion in which the vertical wiring line is formed is cut and divided. 3. A method of providing a conductive metal on the through hole of the wafer laminate by sputtering or plating, providing a resist coat on the conductive metal coating, and exposing the resist coat to light. 3. The method for manufacturing a stacked semiconductor device according to claim 2, wherein the conductive metal exposed other than through-hole is removed by developing and exposing the exposed conductive metal. 4. A method for manufacturing a stacked semiconductor device in which a plurality of wafers are stacked with an insulating layer interposed therebetween, wherein a pattern film having an external connection pattern formed thereon is attached to an adhesive film. A wafer is laminated on an insulating film via an insulating adhesive, a resist is provided on the wafer, and then exposed, developed, and silicon-etched to dice the wafer to a desired size and to perform wiring removal. The next wafer is laminated on the wafer via an insulating adhesive, a resist is provided on the wafer, exposure, development, dicing by silicon etching, and application of the insulating adhesive are repeated. To form a desired multi-layered wafer-laminated body, a through hole is formed in the vicinity of the chip other than the dicing portion and the dicing portion, and a conductive metal is provided on the through hole. Forming vertical wiring lines for electrically connecting chips in wafers of each layer, peeling off the adhesive film and providing external connection terminals on external connection patterns of the pattern film; A method for manufacturing a stacked semiconductor device, comprising cutting and dicing a dicing portion where a line is formed. 5. A method of providing a conductive metal on the through hole of the wafer laminate by sputtering or plating, providing a resist coat on the conductive metal coating, and exposing the resist coat to light. 6. The method for manufacturing a stacked semiconductor device according to claim 5, further comprising removing the conductive metal other than the through-hole by developing and developing the exposed conductive metal.