JP2001177047A - Method for manufacturing stacked semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a stacked semiconductor device with high quality by preventing the shape from being destroyed due to etching. SOLUTION: A pattern film 3 on which an outside connection pattern 2 is formed is laminated on a glass board 1, a wafer 5 is laminated through an insulating adhesive 7 on the pattern film, and the wafer is diced, and made thin by operating silicon etching. Also, the interval of the dicing groove is widened, and a wiring lead is allowed to remain. The lamination of the wafer through the insulating adhesive on the silicon etched wafer, the dicing, the silicon etching, and the application of the insulating adhesive is repeated so that a wafer laminate 7 having plural stages can be constituted. Then, a through-hole 8 is perforated at the dicing part and near the chip other than the dicing part, and conductive metal 9 is formed at the through-hole so that a vertical wiring line 10 on which the in-wafer chip in each hierarchy can be electrically connected can be formed. Then, a glass board is peeled, and an outside connecting terminal 12 is formed at the outside connection pattern, and the dicing part at which the vertical wiring line is formed is cut so that the stacked semiconductor device can be manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a stacked semiconductor device.

[0002]

2. Description of the Related Art As a semiconductor device, a stacked type in which a plurality of semiconductor chips are stacked for ultra-high-density mounting has been proposed.

A conventionally proposed stacked semiconductor device has a plurality of stacked carriers on which a semiconductor chip is mounted. A printed board, a multilayer board, or a film provided with a wiring pattern is used as the carrier, and the semiconductor chip is mounted on the carrier. And a plurality of stacked layers. Although the stacked semiconductor device has an increased mounting density, there is a problem that the stacked semiconductor devices are thick and difficult to reduce the thickness.

[0004]

As described above, the stacked semiconductor device does not meet the needs for thinning, and it is desired to reduce the thickness. Also, stacked semiconductor devices are formed by laminating semiconductor chips by wafer etching and stacking them.
There is a problem that the etching damages and breaks the adhesive film that sticks and supports the wafer.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a high quality stacked semiconductor device which can reduce the thickness of the stacked semiconductor device and does not lose its shape due to etching of a wafer for forming a semiconductor chip.

[0006]

SUMMARY OF THE INVENTION The gist of the present invention is to provide a method for manufacturing a stacked semiconductor device in which wafers are stacked in a plurality of stages with an insulating layer interposed therebetween, wherein a pattern film having an external connection pattern formed on a glass plate is laminated. Attaching, laminating a wafer on the pattern film via an insulating adhesive,
The wafer is diced to a desired size, the diced wafer is thinned by silicon etching, the spacing between dicing grooves is widened, and the wiring leads are left, and the following is performed on the silicon-etched wafer via an insulating adhesive. The wafers are laminated, the laminated wafers are diced, silicon etched, an insulating adhesive is applied, and the lamination, dicing, silicon etching and application of the insulating adhesive are repeatedly performed a desired number of times to obtain a desired number of steps. A vertical wiring line for forming a wafer laminate, forming a through hole near the dicing portion and near the chip other than the dicing portion, providing a conductive metal in the through hole, and electrically connecting the chips in the wafer of each layer. Is formed, and then the glass plate is peeled off and the outside of the pattern film is removed. An external connection terminal provided on the connection pattern, in the manufacturing method of the stacked semiconductor device characterized by dividing by cutting the dicing portion wiring line is formed of the vertical.

Another point is that in the silicon etching of the wafer, the wafer is diced to a desired size.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1A, reference numeral 1 denotes a glass plate, which is a support member for manufacturing a stacked semiconductor device. An external connection pattern 2 is provided on the lower surface of the glass plate 1 as shown in FIG. The pattern film 3 is stuck. Further, rings 4 are provided on both sides of the glass plate 1 for securing strength and for convenience of handling.

The pattern film 3 includes (c) in FIG.
Is adhered via an insulating adhesive 6. The wafer 5 is diced as shown in FIG. 1D and divided into three pieces in this embodiment. The number of divisions is not limited to three and can be changed arbitrarily.

Next, the wafer 5 is silicon-etched to make it thinner as shown in FIG. 1E, and the dicing groove is widened to increase the distance between the wafers 5. At this time, the wiring leads of the chips of the wafer 5 exposed by the silicon etching are left.

Thereafter, as shown in FIG. 1F, an insulating adhesive material 6 is applied on the wafer 5, and a second-stage wafer 5a is attached thereon.

Next, dicing, silicon etching, and application of an insulating adhesive are repeatedly performed on the wafer 5a in the same manner as described above, and a desired number of wafers 5 are stacked. As described above, the silicon etching is performed for each of the stacked wafers, but since the silicon substrate is supported by the glass plate 1, the supporting substrate supports the wafer 5 as it is without initial deformation, and the wafer 5 is a multilayered wafer. All are well shaped and thin. In this embodiment, two layers are stacked, but three layers are stacked.
A desired number of layers such as four layers can be laminated.

After laminating a desired number of wafers 5, an insulating adhesive 6 is applied to the upper surface of the wafer 5 to protect the uppermost wafer 5a. This is shown in FIG.

Next, as shown in FIG. 2 (i), through holes 8 are formed in the dicing locations of the wafer stack 7 by laser, drill, chemical etching or the like. Further, though not shown, through holes are formed in order to form signal lines that are not common between chips in the wafer 5 of the wafer stack 7.

Thereafter, as shown in FIG. 1 (j), a conductive metal 9, for example, aluminum or copper is provided on the inner wall of the through hole 8 by sputtering or plating, and the chips in the laminated wafers 5, 5a are electrically connected. The conductive metal 9 forms a vertical wiring line 10 on the inner wall of the through hole 8. Since the electrical connection is performed in this manner, the reliability of the connection is excellent.

When the conductive metal 9 is provided, it also adheres to the top and side surfaces of the wafer stack 7. In order to remove the excess, a resist 11 is applied to the top and side surfaces as shown in FIG. 7 (k), exposed, developed, and etched to remove the conductive metal adhered to portions other than the through holes 8. .
The wafer laminate 7 after the removal is shown in FIG.

The formation of the wiring line 10 is not limited to this embodiment, but can be formed by an additive method. When aluminum is used as the conductive metal 9, a corrosion-resistant metal such as nickel may be coated.

After that, the glass plate 1 is removed from the wafer laminated body 7, and external connection terminals 12, for example, solder balls, copper balls, bumps,
Alternatively, a land or the like is provided.

Thereafter, if necessary, a glass plate 1a or an adhesive holding film is adhered to the opposite side of the wafer laminated body 7 on which the external connection terminals 12 are provided, and then a through hole 8 provided with the conductive metal 9 is formed. Dicing is performed along the hole direction to divide the wafer stack 7 into individual stacks, and the stacked semiconductor device 13 is manufactured.

In the above embodiment, the laminated wafer 5 was diced with the insulating adhesive 6 interposed therebetween, followed by silicon etching to make the wafer 5 thinner and to increase the dicing interval. However, if the wafer 5 is thinned in advance, a resist is provided on the laminated wafer 5 via the insulating adhesive 6, exposed, developed, and silicon-etched to dice the wafer 5 to a desired size. Just do it. In this case, the productivity increases.

[0021]

As described above, in the manufacture of the stacked semiconductor device, the wafer 5 is thinned by silicon etching.
In addition, although the etching for widening the division interval after the dicing is performed for each lamination, in the present invention, since the glass plate 1 is supported, the glass plate 1 is supported in the initial posture without being affected by the etching because the glass plate 1 is supported. . Thus, the wafer 5
Is processed with good shape and good workability to obtain a stacked semiconductor device with excellent quality. Further, since the wafer 5 is laminated without interposing a substrate such as a carrier,
The manufactured stacked semiconductor device has effects such as reduction in thickness.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a manufacturing process of a stacked semiconductor device according to one embodiment of the present invention.

FIG. 2 is a view illustrating a manufacturing process of the stacked semiconductor device following FIG. 1;

FIG. 3 is a diagram showing a stacked semiconductor device according to one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass plate 2 External connection pattern 3 Pattern film 4 Ring 5 Wafer 6 Insulating adhesive 7 Wafer laminated body 8 Through hole 9 Conductive metal 10 Vertical wiring line 11 Resist 12 External connection terminal 13 Stacked semiconductor device

Claims (4)

[Claims] In a method of manufacturing a stacked semiconductor device in which a wafer is stacked in a plurality of stages with an insulating layer interposed, a pattern film having an external connection pattern formed thereon is attached to a glass plate and the wafer is insulated. Laminated through an adhesive, dicing the wafer to the desired size, thinning the diced wafer by silicon etching, widening the spacing between dicing grooves, and leaving the wiring leads insulated on the silicon-etched wafer. The next wafer is laminated via the conductive adhesive, the laminated wafer is diced, silicon etched, an insulating adhesive is applied, and the lamination of the wafer, dicing, silicon etching and application of the insulating adhesive are performed. Repeated a desired number of times to form a wafer stack of a plurality of stages, A through-hole is formed in the vicinity of the chip other than the chip portion and the dicing portion, and a conductive metal is provided in the through-hole to form a vertical wiring line for electrically connecting the chips in the wafer of each layer. A method for manufacturing a stacked semiconductor device, wherein the glass plate is peeled off, external connection terminals are provided on an external connection pattern of the pattern film, and a dicing portion where the vertical wiring lines are formed is cut and divided. 2. A method of providing a conductive metal in a through hole of the wafer laminated body is performed by sputtering or plating, a resist coat is provided on a coating of the conductive metal, and exposed and developed to remove the exposed conductive metal. 2. The method according to claim 1, wherein the conductive metal other than the through holes is removed by etching. 3. A method for manufacturing a stacked semiconductor device in which wafers are stacked in a plurality of stages with an insulating layer interposed therebetween, wherein a pattern film having an external connection pattern formed thereon is attached to a glass plate and the wafer is insulated. Laminating via an adhesive, providing a resist on the wafer,
Next, the wafer is exposed, developed, and silicon-etched to dice the wafer to a desired size, and the wiring leads are left, and the next wafer is laminated on the wafer via an insulating adhesive, and the resist on the wafer is resisted. , Exposure, development, dicing by silicon etching and application of an insulating adhesive are repeated a desired number of times to form a wafer stack of a desired number of stages, and a through hole is formed in the dicing portion and near the chip other than the dicing portion. Then, a conductive metal is provided in the through hole to form a vertical wiring line for electrically connecting the chips in the wafers of each layer, and the glass plate is peeled off to form an external connection terminal on an external connection pattern of the pattern film. Wherein the dicing portion on which the vertical wiring lines are formed is cut and divided. The method of production. 4. A method of providing a conductive metal in a through hole of the wafer laminate by sputtering or plating, providing a resist coat on the conductive metal coating, exposing and developing the exposed conductive metal, 4. The method according to claim 3, wherein the conductive metal other than the through holes is removed by etching.