JP2007067276A - Printed wiring board and method of manufacturing the same - Google Patents

Printed wiring board and method of manufacturing the same Download PDF

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JP2007067276A
JP2007067276A JP2005253570A JP2005253570A JP2007067276A JP 2007067276 A JP2007067276 A JP 2007067276A JP 2005253570 A JP2005253570 A JP 2005253570A JP 2005253570 A JP2005253570 A JP 2005253570A JP 2007067276 A JP2007067276 A JP 2007067276A
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copper foil
circuit pattern
substrate
plating
hole
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Tatsuya Hiuga
達也 日向
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Nippon Avionics Co Ltd
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Nippon Avionics Co Ltd
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<P>PROBLEM TO BE SOLVED: To provide a printed wiring board having a through-hole with a high aspect ratio in which the plating thickness of the inner wall of the through-hole is increased sufficiently, and having a fine circuit pattern in the outer layer. <P>SOLUTION: The board includes a fine circuit pattern 14 and a through-hole 12. The fine circuit pattern 14 is formed by a plating 62 on a copper foil 20 which is held on a temporary substrate 50 to allow delamination, and is exposed on the surface after being transferred to a main substrate 16 with the copper foil. In the through-hole 12, a pad 22 is formed on the copper foil 20. The pad 22 of the through-hole 12 is formed on the copper foil 20 that has been transferred to the main substrate 16 from the temporary substrate 50. The fine circuit pattern 14 is the one that has been formed on the copper foil 20 of the temporary substrate 50 by plating and transferred to the main substrate 16. Therefore, the fine circuit pattern 14 can be made sufficiently thin. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は、外層微細回路パターンとスルーホールとを有するプリント配線板とその製造方法とに関するものである。   The present invention relates to a printed wiring board having an outer fine circuit pattern and a through hole, and a method for manufacturing the same.

近年電子部品の高密度実装化が必要とされ、プリント配線板に形成する回路パターンの微細化と、スルーホールの高アスペクト比化とが求められている。ここにアスペクト比とは、スルーホールの内径(基板に加工した貫通孔の内径)dに対する深さlの比l/dである。   In recent years, high-density mounting of electronic components is required, and miniaturization of circuit patterns formed on printed wiring boards and high aspect ratios of through holes are required. Here, the aspect ratio is the ratio 1 / d of the depth l to the inner diameter (the inner diameter of the through hole processed in the substrate) d of the through hole.

特開2003−273488JP2003-273488

特許文献1には、基板表面の導体層が厚いと微細回路パターンが形成できないことから、表面導体層をエッチングと研磨により薄くしてから微細回路パターンを形成することが示されている。すなわちスルーホール内壁のめっき厚を十分な厚さ(30μm)にすると基板表面のめっき層も厚く(スルーホール内壁のめっき厚の約2倍、60μmになる。)なるため、スルーホールにペーストを充填して塞いだ後、表面導体層(めっき層)をエッチングと研磨により薄くするものである。例えばエッチングにより導体層を36μmにし、研磨によって28μmまで薄くする。その後で公知のパターン形成工程により微細回路パターンを形成するものである。   Patent Document 1 discloses that a fine circuit pattern cannot be formed if the conductor layer on the surface of the substrate is thick, so that the fine circuit pattern is formed after the surface conductor layer is thinned by etching and polishing. That is, if the plating thickness of the inner wall of the through hole is set to a sufficient thickness (30 μm), the plating layer on the substrate surface also becomes thick (about twice the plating thickness of the inner wall of the through hole, which is 60 μm). After closing, the surface conductor layer (plating layer) is thinned by etching and polishing. For example, the conductor layer is made 36 μm by etching and is thinned to 28 μm by polishing. Thereafter, a fine circuit pattern is formed by a known pattern forming process.

特許文献1に示された方法では、スルーホールの開口部に形成されるパッドがエッチングと研磨により薄くなるため、スルーホール内壁のめっき層とパッドとの接続部も薄くなり、この部分の強度が弱くなりクラック(亀裂)が発生し易くなる。このためプリント配線板の信頼性と耐久性が低下するという問題がある。   In the method disclosed in Patent Document 1, since the pad formed in the opening of the through hole is thinned by etching and polishing, the connecting portion between the plated layer on the inner wall of the through hole and the pad is also thinned. It becomes weak and it becomes easy to generate | occur | produce a crack (crack). For this reason, there exists a problem that the reliability and durability of a printed wiring board fall.

一方高アスペクト比のスルーホールでは、スルーホール内壁のめっき厚を十分に厚くすると表面のめっき層が過大に厚くなり、外層回路パターンの微細化が困難になる。   On the other hand, in the case of a high aspect ratio through-hole, if the plating thickness of the inner wall of the through-hole is made sufficiently thick, the surface plating layer becomes excessively thick and it becomes difficult to make the outer layer circuit pattern finer.

なおスルーホール内壁を銅めっきする際に、低電流密度で電解めっきをすることにより、基板表面のめっき層をスルーホール内壁のめっき層とほぼ同じ厚さにできることが知られている(特許文献1,段落0006参照)。しかしこの場合も表面導体層(めっき層)はスルーホール内壁のめっき層より薄くするのは不可能であり、このめっき層は基板表面の銅箔(12μm)の上に形成するため、合計厚さは(30+12=)42μm程度になり、十分に薄くすることはできなかった。   In addition, when copper plating the inner wall of a through hole, it is known that the plating layer on the surface of the substrate can be made substantially the same thickness as the plating layer of the inner wall of the through hole by performing electrolytic plating at a low current density (Patent Document 1). , Paragraph 0006). In this case, however, it is impossible to make the surface conductor layer (plating layer) thinner than the plating layer on the inner wall of the through hole. Since this plating layer is formed on the copper foil (12 μm) on the substrate surface, the total thickness is reduced. Was about (30 + 12 =) 42 μm and could not be made sufficiently thin.

この発明はこのような事情に鑑みなされたものであり、スルーホール内壁のめっき厚を十分に厚くした高アスペクト比のスルーホールと、外層微細回路パターンとを有するプリント配線板を提供することを第1の目的とする。
またこのプリント配線板の製造方法を提供することを第2の目的とする。
The present invention has been made in view of such circumstances, and it is a first object of the present invention to provide a printed wiring board having a through hole having a high aspect ratio in which the plating thickness of the inner wall of the through hole is sufficiently thick and an outer fine circuit pattern. 1 purpose.
A second object is to provide a method for manufacturing the printed wiring board.

この発明によれば第1の目的は、仮基板に剥離可能に保持された銅箔にめっきにより形成されこの銅箔と共に本基板に移された後表面に露出された微細回路パターンと、前記銅箔上にパッドを形成したスルーホールと、を備えることを特徴とするプリント配線板、により達成できる。   According to the present invention, a first object is to form a fine circuit pattern which is formed by plating on a copper foil releasably held on a temporary substrate and exposed to the substrate after being transferred to the substrate together with the copper foil, and the copper It can be achieved by a printed wiring board comprising a through hole having a pad formed on a foil.

また第2の目的は、外層微細回路パターンと、スルーホールとを有するプリント配線板の製造方法において、a.表面に銅箔を剥離可能に保持した仮基板を用意し、b.この仮基板の表面の銅箔にレジストを形成し、露光および現像により微細回路パターンに対応する溝を形成し、c.工程bで形成した微細回路パターンに対応する溝に、少なくとも仮基板の銅箔に接するめっき層を耐銅エッチング性とした金属導体をめっきし、d.工程bで形成したレジストを除去し、e.プリプレグを介して最終的な基板となる本基板を積層し、f.銅箔を本基板側に残して仮基板を剥がし、g.本基板にスルーホール孔を加工し、表面およびスルーホール孔の内壁に厚付け銅めっきを施し、h.エッチングにより少なくとも微細回路パターンを露出させる、以上の工程a〜hを備えるプリント配線板の製造方法、により達成される。   A second object is to provide a method for manufacturing a printed wiring board having an outer layer fine circuit pattern and a through hole. Providing a temporary substrate having a copper foil peelable on its surface; b. Forming a resist on the copper foil on the surface of the temporary substrate and forming grooves corresponding to the fine circuit pattern by exposure and development; c. A groove corresponding to the fine circuit pattern formed in step b is plated with a metal conductor having at least a plating layer in contact with the copper foil of the temporary substrate as a copper etch resistance; d. Removing the resist formed in step b, e. Laminating the final substrate through the prepreg, f. Peel off the temporary substrate leaving the copper foil on the substrate side, g. Processing through-hole holes in the substrate, and applying thick copper plating to the surface and inner walls of the through-hole holes; h. This is achieved by a method for producing a printed wiring board comprising the above steps a to h, wherein at least a fine circuit pattern is exposed by etching.

請求項1の発明によれば、スルーホールのパッドを仮基板から本基板に移した銅箔の上に形成しているので、スルーホール内壁のめっき層とパッドとの接続部のめっき厚さを十分に厚くすることができる。このためスルーホール内壁とパッドとの接続部の強度を増大させ、回路の信頼性と耐久性を向上させることができる。また表面の微細回路パターンは仮基板の銅箔にめっきで形成されたものを本基板に移したものであるから十分に薄くでき、線幅および線間隔を十分に小さくして配線密度を高めることができる。   According to the invention of claim 1, since the pad of the through hole is formed on the copper foil transferred from the temporary substrate to the main substrate, the plating thickness of the connecting portion between the plating layer on the inner wall of the through hole and the pad is set. It can be thick enough. For this reason, the strength of the connection portion between the inner wall of the through hole and the pad can be increased, and the reliability and durability of the circuit can be improved. In addition, the fine circuit pattern on the surface is the one formed by plating the copper foil of the temporary board to the main board, so it can be made sufficiently thin, and the line width and line spacing can be made sufficiently small to increase the wiring density. Can do.

請求項3の発明によれば、このプリント配線板の製造方法が得られる。また微細回路パターンは銅箔および厚付け銅めっき層とをエッチングで除去する(工程h)だけで、表面を研磨しないから、回路パターンの線間隔を狭くできる。   According to invention of Claim 3, the manufacturing method of this printed wiring board is obtained. Moreover, since the surface of the fine circuit pattern is not polished by merely removing the copper foil and the thick copper plating layer by etching (step h), the line spacing of the circuit pattern can be reduced.

本基板の表面(外層)には銅箔上にスルーホールおよびパッドと共に厚付け銅めっきにより形成されかつ微細回路パターンに接続された外層回路パターンを形成することができる(請求項2)。この場合には、外層回路パターンは銅箔と厚付け銅めっき層との積層により形成されることになるから、電気抵抗を十分に小さくできる。従ってこの外層回路パターンに微細回路パターンを接続しておくことにより、微細回路パターンの線断面積の微少化による直流電気抵抗の増大を抑制できる。すなわち微細回路パターンの電気抵抗が大きくなることによる不都合を十分に回避できる。   On the surface (outer layer) of the substrate, an outer layer circuit pattern formed by thick copper plating together with through holes and pads on the copper foil and connected to a fine circuit pattern can be formed. In this case, the outer layer circuit pattern is formed by laminating the copper foil and the thick copper plating layer, so that the electric resistance can be sufficiently reduced. Therefore, by connecting the fine circuit pattern to the outer layer circuit pattern, it is possible to suppress an increase in the DC electric resistance due to the miniaturization of the line sectional area of the fine circuit pattern. That is, it is possible to sufficiently avoid the inconvenience due to the increase in electrical resistance of the fine circuit pattern.

請求項3の発明において工程aで用いる仮基板は、銅箔と銅箔キャリヤとを剥離層を介して剥離可能に積層した銅箔積層体を絶縁板に積層したものが適する(請求項4)。ここに銅箔キャリヤは銅箔より十分に厚く(約70μm)、薄い銅箔(約9μm)を保護し支持するために薄い銅箔に積層された状態とした銅箔積層体として取り扱われる。通常薄い銅箔を基板に貼り、厚いキャリヤはその後で剥離するものである。この場合は本基板側に移す銅箔は厚い銅箔キャリヤであるが、この銅箔は工程hでエッチングにより少なくとも微細回路パターンを露出させるように銅めっきと共に除去するものであるから、薄い方が処理時間短縮の点で望ましい。このためには仮基板には銅箔キャリヤを密着させるように銅箔積層体を貼り付ける(積層する)のがよい(請求項5)。   The temporary substrate used in step a in the invention of claim 3 is suitably a laminate of a copper foil laminate in which a copper foil and a copper foil carrier are detachably laminated via a release layer on an insulating plate (invention 4). . Here, the copper foil carrier is sufficiently thicker (about 70 μm) than the copper foil, and is handled as a copper foil laminate that is laminated on the thin copper foil in order to protect and support the thin copper foil (about 9 μm). Usually a thin copper foil is applied to the substrate and the thick carrier is then peeled off. In this case, the copper foil transferred to the substrate is a thick copper foil carrier, but this copper foil is removed together with the copper plating so as to expose at least a fine circuit pattern by etching in step h. It is desirable in terms of shortening the processing time. For this purpose, a copper foil laminate is preferably attached (laminated) to the temporary substrate so that the copper foil carrier is in close contact.

工程cで微細回路パターンとなる金属導体のめっき層は、工程hで銅箔および銅めっきを除去する際に銅箔および銅めっきと共に除去されずに残るようにする必要がある。そのためには、少なくとも銅箔に接する面を銅エッチングで除去されない(耐銅エッチング性)金属、例えば金めっきとする。この場合この金めっきの上にニッケル、銅のめっきを重ねたものがよい(請求項6)。高価な金めっきの使用量が減るからである。   When the copper foil and the copper plating are removed in the step h, the metal conductor plating layer that becomes the fine circuit pattern in the step c needs to remain without being removed together with the copper foil and the copper plating. For that purpose, at least the surface in contact with the copper foil is made of a metal that is not removed by copper etching (copper etching resistance), for example, gold plating. In this case, it is preferable that nickel and copper are stacked on the gold plating. This is because the amount of expensive gold plating used is reduced.

工程hでは、スルーホールのパッドと、微細回路化が不要な通常の外層回路パターンとを残して銅箔および銅めっきを除去するようにすれば外層に通常の(微細回路でない)回路パターンを形成できる(請求項7)。   In step h, if the copper foil and the copper plating are removed leaving the through-hole pad and the normal outer layer circuit pattern that does not require fine circuit formation, a normal (non-fine circuit) circuit pattern is formed on the outer layer. (Claim 7).

図1〜6は本発明の異なる製造工程を順番に示す図である。図1は仮基板を示す図、図2はこの仮基板に微細回路パターンとなる金属導体のめっき層の形成工程を示す図、図3は本基板の積層工程を示す図、図4は仮基板を剥がしてスルーホール孔を加工する工程を示す図、図5はスルーホールめっき工程を示す図、図6は銅めっきおよび銅箔をエッチングで除去することにより微細回路パターン部分を露出させる工程を示す図である。図7は加工終了後の本基板の表面パターン例を示す平面図、図8はそのVIII-VIII線断面図、図9は工程流れ図である。   1-6 is a figure which shows the manufacturing process from which this invention differs in order. 1 is a diagram showing a temporary substrate, FIG. 2 is a diagram showing a process of forming a metal conductor plating layer to be a fine circuit pattern on the temporary substrate, FIG. 3 is a diagram showing a lamination process of the substrate, and FIG. 4 is a temporary substrate. FIG. 5 is a view showing a through-hole plating step, and FIG. 6 is a step showing exposing a fine circuit pattern portion by removing copper plating and copper foil by etching. FIG. FIG. 7 is a plan view showing an example of the surface pattern of the substrate after completion of processing, FIG. 8 is a sectional view taken along line VIII-VIII, and FIG. 9 is a process flow chart.

この発明に係るプリント配線板は図6〜8に示す構造を持つ。すなわちこのプリント配線板10には、高アスペクト比のスルーホール12と、微細回路パターン14とが形成されている。ここにスルーホール12は、例えば板厚が3.0mmの基板(本基板)16に穴径が0.3mmの貫通孔18を形成したもので、この場合貫通孔18のアスペクト比は10であるが、5以上、特に7以上とすることが望ましい。   The printed wiring board according to the present invention has a structure shown in FIGS. That is, the printed wiring board 10 is formed with a through hole 12 having a high aspect ratio and a fine circuit pattern 14. Here, the through hole 12 is formed by forming a through hole 18 having a hole diameter of 0.3 mm on a substrate (main substrate) 16 having a plate thickness of 3.0 mm, for example. In this case, the aspect ratio of the through hole 18 is 10. Is preferably 5 or more, particularly 7 or more.

貫通孔18の内壁面には30μmの銅めっきを行うと通常基板16の表面には約2倍の厚さ(60μm)のめっき層ができる。表面のめっき層が厚くなるとこのめっき層をエッチングして回路パターンを形成する場合に微細化が不可能になる。低電流密度で電解めっきをすることにより表面のめっき層をスルーホール内壁のめっき厚とほぼ同じにすることが可能であることも前記した通りであるが、この場合も表面のめっき厚さは約30μmであり、やはり回路パターンの微細化は困難である。   When copper plating of 30 μm is performed on the inner wall surface of the through hole 18, a plating layer having a thickness approximately twice (60 μm) can be formed on the surface of the normal substrate 16. When the plating layer on the surface becomes thick, it becomes impossible to make a fine pattern when the plating layer is etched to form a circuit pattern. As described above, it is possible to make the plating layer on the surface approximately the same as the plating thickness of the inner wall of the through hole by performing electrolytic plating at a low current density. In this case as well, the plating thickness of the surface is about It is 30 μm, and it is difficult to miniaturize the circuit pattern.

この発明では微細回路パターン14は、後記するように、仮基板に剥離可能に保持された銅箔20にめっきにより形成した微細回路パターン14を銅箔20と共に基板(本基板)16に移した後、表面に残る不用な銅箔20を除去することによって基板(本基板)16の表面に露出させたものである。またスルーホール12のパッド22は、本基板16に移した銅箔20上に形成したものである。   In the present invention, as will be described later, the fine circuit pattern 14 is transferred to the substrate (main substrate) 16 together with the copper foil 20 after the fine circuit pattern 14 formed by plating on the copper foil 20 which is releasably held on the temporary substrate is plated. The unnecessary copper foil 20 remaining on the surface is removed so as to be exposed on the surface of the substrate (main substrate) 16. The pad 22 of the through hole 12 is formed on the copper foil 20 transferred to the substrate 16.

次に図9に基づいて製造方法を説明する。まず図1に示す仮基板50を用意する(図9の工程a)。この仮基板50の表面には銅箔20が剥離可能に保持されている。この仮基板50は、例えば両面銅張り積層板の銅箔キャリヤ52を剥がさない状態のものを用いることができる。すなわち銅張り積層板は、銅箔20(厚さ約9μm)とこれを保護し支持するための銅箔キャリヤ52(厚さ約70μm)とを剥離層53によって剥離可能に接着した銅箔積層体54を接着した後、銅箔キャリヤ52だけを剥がしたものである。この場合仮基板50は、銅箔キャリヤ52を剥がさない状態で用いることができる。従ってこの場合には銅箔キャリヤ52が本発明の銅箔20となる。   Next, a manufacturing method is demonstrated based on FIG. First, a temporary substrate 50 shown in FIG. 1 is prepared (step a in FIG. 9). The copper foil 20 is detachably held on the surface of the temporary substrate 50. As the temporary substrate 50, for example, a double-sided copper-clad laminate in which the copper foil carrier 52 is not peeled off can be used. That is, the copper-clad laminate is a copper foil laminate in which the copper foil 20 (thickness of about 9 μm) and a copper foil carrier 52 (thickness of about 70 μm) for protecting and supporting the copper foil 20 are peeled off by the release layer 53. After bonding 54, only the copper foil carrier 52 is peeled off. In this case, the temporary substrate 50 can be used without peeling off the copper foil carrier 52. Therefore, in this case, the copper foil carrier 52 becomes the copper foil 20 of the present invention.

しかし後記するようにこの銅箔20はエッチングによって除去するものであるから、処理時間を短くするためには薄いものが望ましい。そこでここでは銅箔積層体54を表裏逆にして仮基板50に貼付け、薄い銅箔20が表面(下面)に露出するようにした。なおこの仮基板50の他の表面(上面)には薄い銅箔56を貼ってあるが、これは省いてもよい。   However, as will be described later, since the copper foil 20 is removed by etching, a thin one is desirable in order to shorten the processing time. Therefore, here, the copper foil laminate 54 is affixed to the temporary substrate 50 so that the thin copper foil 20 is exposed on the surface (lower surface). In addition, although the thin copper foil 56 is affixed on the other surface (upper surface) of this temporary board | substrate 50, this may be omitted.

このように用意した仮基板50の銅箔20には、ドライフィルムを貼ったりレジスト液を塗布することによってレジスト58を形成し、このレジスト58に露光・現像により微細回路パターンに対応する溝60を形成する(図9の工程b、図2)。   A resist 58 is formed on the copper foil 20 of the temporary substrate 50 thus prepared by applying a dry film or applying a resist solution, and the resist 58 is provided with a groove 60 corresponding to a fine circuit pattern by exposure and development. Form (step b in FIG. 9, FIG. 2).

この溝60には、金、ニッケル、銅の順にめっきを行う(図9の工程c)。このめっきで形成した金属導体62は後記するように(工程f参照)本基板16に移されて微細回路パターン14になる。なおこの金属導体62の銅箔20に接する面(この実施例では金めっき層)は、後記工程hで銅箔20をエッチングにより除去する際にエッチングされない性質(耐エッチング性)を持つものが望ましい。   The groove 60 is plated in the order of gold, nickel, and copper (step c in FIG. 9). The metal conductor 62 formed by this plating is transferred to the main substrate 16 to become the fine circuit pattern 14 as described later (see step f). The surface of the metal conductor 62 that is in contact with the copper foil 20 (in this embodiment, a gold plating layer) preferably has a property (etching resistance) that is not etched when the copper foil 20 is removed by etching in the later-described step h. .

次にレジスト58を除去する(工程d)。このため図3(A)に示すように、仮基板50の銅箔20に、微細回路パターン14となるめっき層である金属導体62が残る。   Next, the resist 58 is removed (step d). For this reason, as shown in FIG. 3A, the metal conductor 62, which is a plating layer that becomes the fine circuit pattern 14, remains on the copper foil 20 of the temporary substrate 50.

この仮基板50の銅箔20の面には、プリプレグ64を介して内層材66を積層し、熱圧着する(工程e、図3の(A)、(B))。ここに内層材66には適宜の内層回路パターン68、68が形成されている。これらプリプレグ64、内層材66の積層体は最終製品であるプリント配線板10の基板、すなわち本基板16となるものである。   An inner layer material 66 is laminated on the surface of the copper foil 20 of the temporary substrate 50 via a prepreg 64 and thermocompression bonded (step e, (A) and (B) in FIG. 3). Here, appropriate inner layer circuit patterns 68 and 68 are formed on the inner layer material 66. The laminated body of the prepreg 64 and the inner layer material 66 becomes the substrate of the printed wiring board 10 that is the final product, that is, the main substrate 16.

この仮基板50およびプリプレグ64、内層板66の積層体から、銅箔20を本基板16側に残して仮基板50を剥離する(工程f、図4参照)。銅箔20は銅箔キャリヤ52に剥離層53を介して剥離可能に積層されたものであるから、両者の接着面である剥離層53で容易に剥離可能である。   The temporary substrate 50 is peeled from the laminated body of the temporary substrate 50, the prepreg 64, and the inner layer plate 66, leaving the copper foil 20 on the main substrate 16 side (step f, see FIG. 4). Since the copper foil 20 is laminated on the copper foil carrier 52 through the release layer 53 so as to be peeled off, the copper foil 20 can be easily peeled off at the release layer 53 which is an adhesive surface between them.

このように仮基板50を剥離した本基板16にはスルーホール12となる貫通孔18を加工する(図4)。そしてこの貫通孔18の内壁面および本基板16の表面に厚付け銅めっき70を形成する(工程g、図5)。この銅めっき70は、低電流密度で行うことにより、表面のめっき厚と貫通孔18内壁のめっき厚との不均一を緩和することができる。   Thus, the through-hole 18 used as the through hole 12 is processed in this board | substrate 16 which peeled the temporary board | substrate 50 (FIG. 4). And thick copper plating 70 is formed in the inner wall surface of this through-hole 18, and the surface of this board | substrate 16 (process g, FIG. 5). By performing the copper plating 70 at a low current density, it is possible to alleviate unevenness between the plating thickness of the surface and the plating thickness of the inner wall of the through hole 18.

次に銅めっき70の表面に公知のフォトエッチングにより不用な銅めっき70およびその下地となっている銅箔20を除去する。すなわちスルーホール12のパッド22や他の外層回路パターン72(図7、8)をレジストで覆い、それら以外の領域の銅めっき70および銅箔20を銅エッチングにより除去する(工程h、図6)。   Next, the unnecessary copper plating 70 and the underlying copper foil 20 are removed from the surface of the copper plating 70 by known photoetching. That is, the pad 22 of the through-hole 12 and other outer layer circuit patterns 72 (FIGS. 7 and 8) are covered with a resist, and the copper plating 70 and the copper foil 20 in other regions are removed by copper etching (step h, FIG. 6). .

この結果金属導体62が本基板16の表面に埋め込まれた状態で露出する。すなわち微細回路パターン14が形成される。   As a result, the metal conductor 62 is exposed while being embedded in the surface of the substrate 16. That is, a fine circuit pattern 14 is formed.

表面に残す外層回路パターン72は、図7、8に示すように微細回路パターン14に接続することができる。すなわち金属導体62は銅箔20を介して外層回路パターン72に接続される。この外層回路パターン72は微細回路パターン14より十分厚く、その断面積も大きいので直流電気抵抗が小さくなる。このため微細回路パターン14は、配線密度が高くなる領域だけに形成することにより、電気抵抗が大きくなることによる不都合を避けることができる。   The outer layer circuit pattern 72 left on the surface can be connected to the fine circuit pattern 14 as shown in FIGS. That is, the metal conductor 62 is connected to the outer layer circuit pattern 72 via the copper foil 20. Since the outer layer circuit pattern 72 is sufficiently thicker than the fine circuit pattern 14 and has a large cross-sectional area, the DC electric resistance is reduced. For this reason, the fine circuit pattern 14 is formed only in the region where the wiring density is increased, thereby avoiding inconvenience due to the increase in electric resistance.

仮基板の構造を示す図Diagram showing the structure of the temporary substrate 金属導体の形成工程を示す図Diagram showing metal conductor formation process 本基板の積層工程を示す図Diagram showing the lamination process of this substrate スルーホールの貫通孔の加工工程を示す図The figure which shows the processing process of the through hole of the through hole 銅めっきの工程を示す図Diagram showing copper plating process 不用な銅めっきと銅箔の除去工程を示す図Diagram showing the removal process of unnecessary copper plating and copper foil プリント配線板の表面回路パターン例を示す図The figure which shows the example of the surface circuit pattern of the printed wiring board 図7におけるVIII-VIII線断面図VIII-VIII sectional view in FIG. 製造工程の流れ図Flow chart of manufacturing process

符号の説明Explanation of symbols

10 プリント配線板
12 スルーホール
14 微細回路パターン
16 本基板
18 スルーホールの貫通孔
20 銅箔
22 スルーホールのパッド
50 仮基板
52 銅箔キャリヤ
53 剥離層
54 銅箔積層体
58 レジスト
60 溝
62 金属導体
70 銅めっき(厚付け銅めっき)
72 外層回路パターン
DESCRIPTION OF SYMBOLS 10 Printed wiring board 12 Through hole 14 Fine circuit pattern 16 This board 18 Through hole of through hole 20 Copper foil 22 Pad of through hole 50 Temporary substrate 52 Copper foil carrier 53 Peeling layer 54 Copper foil laminated body 58 Resist 60 Groove 62 Metal conductor 70 Copper plating (thick copper plating)
72 Outer layer circuit pattern

Claims (7)

仮基板に剥離可能に保持された銅箔にめっきにより形成されこの銅箔と共に本基板に移された後表面に露出された微細回路パターンと、
前記銅箔上にパッドを形成したスルーホールと、
を備えることを特徴とするプリント配線板。
A fine circuit pattern exposed on the surface after being formed by plating on the copper foil releasably held on the temporary substrate and transferred to the substrate together with the copper foil,
A through hole in which a pad is formed on the copper foil;
A printed wiring board comprising:
外層には銅箔上にスルーホールおよびパッドと共に厚付け銅めっきで形成されかつ微細回路パターンに接続された外層回路パターンが形成されている請求項1のプリント配線板。   2. The printed wiring board according to claim 1, wherein an outer layer circuit pattern formed by thick copper plating together with through holes and pads and connected to a fine circuit pattern is formed on the copper foil on the outer layer. 外層微細回路パターンと、スルーホールとを有するプリント配線板の製造方法において、
a.表面に銅箔を剥離可能に保持した仮基板を用意し、
b.この仮基板の表面の銅箔にレジストを形成し、露光および現像により微細回路パターンに対応する溝を形成し、
c.工程bで形成した微細回路パターンに対応する溝に、少なくとも仮基板の銅箔に接するめっき層を耐銅エッチング性とした金属導体をめっきし、
d.工程bで形成したレジストを除去し、
e.プリプレグを介して最終的な基板となる本基板を積層し、
f.銅箔を本基板側に残して仮基板を剥がし、
g.本基板にスルーホール孔を加工し、表面およびスルーホール孔の内壁に厚付け銅めっきを施し、
h.エッチングにより少なくとも微細回路パターンを露出させる、
以上の工程a〜hを備えるプリント配線板の製造方法。
In the method of manufacturing a printed wiring board having an outer layer fine circuit pattern and a through hole,
a. Prepare a temporary substrate that holds the copper foil peelable on the surface,
b. Form a resist on the copper foil on the surface of this temporary substrate, form grooves corresponding to the fine circuit pattern by exposure and development,
c. In a groove corresponding to the fine circuit pattern formed in step b, a metal conductor having a copper layer etching resistance at least on a plating layer in contact with the copper foil of the temporary substrate is plated,
d. Removing the resist formed in step b;
e. Laminate this substrate as the final substrate through the prepreg,
f. Remove the temporary substrate, leaving the copper foil on the main substrate side,
g. Process through-hole holes in this board, apply thick copper plating to the surface and inner walls of the through-hole holes,
h. At least a fine circuit pattern is exposed by etching,
A manufacturing method of a printed wiring board provided with the above process ah.
工程aの仮基板は、銅箔と銅箔キャリヤとを剥離可能に積層した銅箔積層体を絶縁板に積層したものである請求項3のプリント配線板の製造方法。   4. The method of manufacturing a printed wiring board according to claim 3, wherein the temporary substrate in step a is obtained by laminating a copper foil laminate in which a copper foil and a copper foil carrier are releasably laminated on an insulating plate. 銅箔積層体は銅箔キャリヤを絶縁板に密着させて積層されている請求項4のプリント配線板の製造方法。   The method for producing a printed wiring board according to claim 4, wherein the copper foil laminate is laminated with a copper foil carrier adhered to an insulating plate. 工程cの金属導体は、仮基板の表面の銅箔側から順に金、ニッケル、銅のめっきを積層したものである請求項3のプリント配線板の製造方法。   The method of manufacturing a printed wiring board according to claim 3, wherein the metal conductor in step c is obtained by laminating gold, nickel, and copper plating in order from the copper foil side of the surface of the temporary substrate. 工程hでは、スルーホールパッドと、微細回路化が不要な外層回路パターンとを残して銅めっきおよび銅箔を除去する請求項3のプリント配線板の製造方法。   4. The method of manufacturing a printed wiring board according to claim 3, wherein in step h, the copper plating and the copper foil are removed while leaving the through-hole pad and the outer layer circuit pattern that does not require fine circuit formation.
JP2005253570A 2005-09-01 2005-09-01 Printed wiring board and method of manufacturing the same Pending JP2007067276A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2012133638A1 (en) * 2011-03-30 2014-07-28 三井金属鉱業株式会社 Multilayer printed wiring board manufacturing method and multilayer printed wiring board obtained by the manufacturing method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02159789A (en) * 1988-12-14 1990-06-19 Meiko Denshi Kogyo Kk Manufacture of printed wiring board
JPH06152105A (en) * 1991-03-22 1994-05-31 Meikoo:Kk Manufacture of printed wiring board
JPH0883959A (en) * 1994-09-12 1996-03-26 Nippon Avionics Co Ltd Horizontal two-side printed board and its manufacture
JP2003092461A (en) * 2001-09-17 2003-03-28 Nippon Avionics Co Ltd Method for manufacturing printed wiring board
JP2005197648A (en) * 2003-12-09 2005-07-21 Shinko Electric Ind Co Ltd Method for manufacturing a circuit board wired by electroplating

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02159789A (en) * 1988-12-14 1990-06-19 Meiko Denshi Kogyo Kk Manufacture of printed wiring board
JPH06152105A (en) * 1991-03-22 1994-05-31 Meikoo:Kk Manufacture of printed wiring board
JPH0883959A (en) * 1994-09-12 1996-03-26 Nippon Avionics Co Ltd Horizontal two-side printed board and its manufacture
JP2003092461A (en) * 2001-09-17 2003-03-28 Nippon Avionics Co Ltd Method for manufacturing printed wiring board
JP2005197648A (en) * 2003-12-09 2005-07-21 Shinko Electric Ind Co Ltd Method for manufacturing a circuit board wired by electroplating

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2012133638A1 (en) * 2011-03-30 2014-07-28 三井金属鉱業株式会社 Multilayer printed wiring board manufacturing method and multilayer printed wiring board obtained by the manufacturing method
JP6093694B2 (en) * 2011-03-30 2017-03-08 三井金属鉱業株式会社 Manufacturing method of multilayer printed wiring board

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