JP2007165513A - Method of manufacturing multilayered wiring board for semiconductor device, and method of manufacturing semiconductor device - Google Patents

Method of manufacturing multilayered wiring board for semiconductor device, and method of manufacturing semiconductor device Download PDF

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JP2007165513A
JP2007165513A JP2005358692A JP2005358692A JP2007165513A JP 2007165513 A JP2007165513 A JP 2007165513A JP 2005358692 A JP2005358692 A JP 2005358692A JP 2005358692 A JP2005358692 A JP 2005358692A JP 2007165513 A JP2007165513 A JP 2007165513A
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metal foil
wiring board
multilayer wiring
manufacturing
semiconductor device
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Masahiro Kyozuka
正宏 経塚
Shigeji Muramatsu
茂次 村松
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayered wiring board for a semiconductor device by which external connection terminals can be accurately formed in a multilayered wiring board made by using a detachable metal foil. <P>SOLUTION: In manufacturing the multilayered wiring board for a semiconductor device, a detachable metal foil is used which is made by bonding a first metal foil 10a thicker than the projecting height of bumps 20 as the external connection terminals, and a second metal foil 10b thinner than the first metal foil 10a together via an adhesive layer so that the metal foils can be detached. A substrate is bonded to the second metal foil 10b side to form a support substrate. Concave portions 18 for bumps which are formed in the first metal foil 10a are filled with plating to form the bumps 20, and a conductor pattern 22 connected to the bumps 20 is formed on the surface of the first metal foil 10a. Thereafter, a multilayered wiring board 30 including the bumps 20 and the conductor pattern 22 is formed on the first metal foil 10a. Then, after separating the first metal foil 10a and the second metal foil 10b, the first metal foil 10 bonded to the multilayered wiring board 30 is removed by etching to expose the bumps 20 and 20, etc. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体装置用の多層配線基板の製造方法及び半導体装置の製造方法に関し、更に詳細には一面側に外部接続端子としてのバンプが形成されていると共に、他面側が半導体素子を搭載する搭載面に形成された半導体装置用の多層配線基板の製造方法及び半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a multilayer wiring board for a semiconductor device and a method for manufacturing a semiconductor device. More specifically, a bump is formed as an external connection terminal on one side, and a semiconductor element is mounted on the other side. The present invention relates to a method for manufacturing a multilayer wiring board for a semiconductor device formed on a surface and a method for manufacturing a semiconductor device.

半導体装置の小型化及び薄化に伴い、半導体装置用の多層配線基板も小型化及び薄化が要請されている。かかる要請に応えるべく、下記特許文献１には、図６及び図７に示す半導体装置用の多層配線基板の製造方法が提案されている。
この多層配線基板の製造方法では、先ず、図６に示す様に、プリプレグ１００から成る樹脂基板の両面に剥離性金属箔としてのキャリア付銅箔１０２が接合された支持基板１０４を形成する。このキャリア付銅箔１０２は、厚さが１〜５μｍの極薄銅箔１０２ａと厚さが１８〜７５μｍのキャリア銅箔１０２ｂとが剥離可能に接着層（図示せず）を介して接着されており、キャリア銅箔１０２ｂ側がプリプレグ１００に接合されている。
かかる支持基板１０４の極薄銅箔１０２ａ，１０２ａの各表面上には、公知のアディティブ法やセミアディティブ法等によって多層配線基板１１２，１１２を形成する［図７（ａ）］。この多層配線基板１１２は、極薄銅箔１０２ａ上に形成された導体パターン１０６，１０６・・上に、樹脂層１０８，１０８を介して導体パターン１０６，１０６・・が積層されていると共に、樹脂層１０８，１０８を貫通して積層された導体パターン１０６，１０６を電気的に接続するヴィア１１０が形成されている。
次いで、図７（ｂ）に示す様に、支持基板１０４を構成するキャリア付銅箔１０２のキャリア銅箔１０２ｂ及びプリプレグ１００を極薄銅箔１０２ａから剥離することによって、極薄銅箔１０２ａが一面側に接合された多層配線基板１１２を得ることができる［図６（ｃ）］。
その後、この極薄銅箔１０２ａをエッチングによって除去することにより、外部接続端子を設けるパッドが露出した多層配線基板１１２を得ることができる［図７（ｄ）］。
特開２００５−１０１１３７号公報 As semiconductor devices are miniaturized and thinned, multilayer wiring boards for semiconductor devices are also required to be miniaturized and thinned. In order to meet such a demand, Patent Document 1 below proposes a method of manufacturing a multilayer wiring board for a semiconductor device shown in FIGS.
In this multilayer wiring board manufacturing method, first, as shown in FIG. 6, a support substrate 104 is formed in which a carrier-attached copper foil 102 as a peelable metal foil is bonded to both surfaces of a resin substrate made of a prepreg 100. This copper foil with carrier 102 is bonded to an ultrathin copper foil 102a having a thickness of 1 to 5 μm and a carrier copper foil 102b having a thickness of 18 to 75 μm through an adhesive layer (not shown) so as to be peelable. The carrier copper foil 102 b side is bonded to the prepreg 100.
On each surface of the ultrathin copper foils 102a and 102a of the support substrate 104, multilayer wiring boards 112 and 112 are formed by a known additive method, semi-additive method, or the like [FIG. 7A]. In this multilayer wiring board 112, conductor patterns 106, 106... Are laminated on conductor patterns 106, 106... Formed on ultrathin copper foil 102 a via resin layers 108, 108. A via 110 is formed to electrically connect the conductive patterns 106 and 106 stacked through the layers 108 and 108.
Next, as shown in FIG. 7B, the carrier copper foil 102 b and the prepreg 100 of the carrier-attached copper foil 102 constituting the support substrate 104 are peeled from the ultrathin copper foil 102 a, so that the ultrathin copper foil 102 a becomes one surface. A multilayer wiring board 112 bonded to the side can be obtained [FIG. 6 (c)].
Thereafter, by removing the ultrathin copper foil 102a by etching, a multilayer wiring board 112 with exposed pads for providing external connection terminals can be obtained [FIG. 7D].
JP 2005-101137 A

図６及び図７に示す半導体装置用の多層配線基板の製造方法で得られた多層配線基板１１２では、その一面側に露出したパッドにはんだバンプ等の外部接続端子を設けることによって、実装可能な多層配線基板１１２を得ることができる。
しかし、本発明者等の検討によれば、極薄銅箔１０２ａが一面側に接合された多層配線基板１１２をプリプレグ１００から剥離したとき、多層配線基板１１２に潜在していた歪が顕在化して発生した「うねり」等に因り、多層配線基板１１２の一面側に露出したパッドにはんだバンプ等の外部接続端子を精度よく装着できないことが判明した。
一方、図６及び図７に示す半導体装置用の多層配線基板の製造方法では、多層配線基板１１２の一面側に接合された極薄銅箔１０２ａのエッチングでは、そのエッチング時間が極めて短時間であるため、他の部材に与えるエッチングに因る損傷を可及的に少なくできる。
そこで、本発明の課題は、剥離性金属箔を用いて得た多層配線基板に精度よく外部接続端子を具備する半導体装置用の多層配線基板の製造方法及び半導体装置の製造方法を提供することにある。 The multilayer wiring board 112 obtained by the method for manufacturing a multilayer wiring board for a semiconductor device shown in FIGS. 6 and 7 can be mounted by providing external connection terminals such as solder bumps on pads exposed on one surface side. A multilayer wiring board 112 can be obtained.
However, according to the study by the present inventors, when the multilayer wiring board 112 with the ultrathin copper foil 102a bonded to one surface side is peeled off from the prepreg 100, the strain that is latent in the multilayer wiring board 112 becomes obvious. It has been found that external connection terminals such as solder bumps cannot be accurately attached to the pads exposed on one side of the multilayer wiring board 112 due to the generated “swells”.
On the other hand, in the method of manufacturing a multilayer wiring board for a semiconductor device shown in FIGS. 6 and 7, the etching time is extremely short in etching of the ultrathin copper foil 102a bonded to one surface side of the multilayer wiring board 112. Therefore, damage caused by etching on other members can be reduced as much as possible.
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a multilayer wiring board for a semiconductor device and a method for manufacturing a semiconductor device in which a multilayer wiring board obtained using a peelable metal foil is provided with an external connection terminal with high accuracy. is there.

本発明者等は、前記課題を解決するには、剥離性金属箔を含む支持基板から多層配線基板を剥離する前に外部接続端子を形成しておくことが有利であると考え検討した結果、本発明に到達した。
すなわち、本発明は、一面側に外部接続端子としてのバンプが形成されていると共に、他面側が半導体素子を搭載する搭載面に形成された半導体装置用の多層配線基板を製造する際に、該外部接続端子としてのバンプの突出高さよりも厚い第１金属箔とこの第１金属箔よりも薄い第２金属箔とが剥離可能に接着層を介して接着されている剥離性金属箔を用い、前記第２金属箔側に強力担持体としての基板を接合して成る支持基板を形成し、前記支持基板を構成する第１金属箔内に形成したバンプ用凹部内に、めっきによりバンプを形成すると共に、前記バンプに接続された導体パターンを第１金属箔の表面に形成した後、前記バンプ及び導体パターンを含む多層配線基板を前記第１金属箔上に形成し、次いで、前記第１金属箔と第２金属箔とを剥離した後、前記多層配線基板に接合された第１金属箔をエッチングによって除去し、前記バンプを露出することを特徴とする半導体装置用の多層配線基板の製造方法にある。
また、本発明は、前記半導体装置用の多層配線基板の製造方法で得られた多層配線基板の一面側に半導体素子を搭載することを特徴とする半導体装置の製造方法でもある。 In order to solve the above problems, the present inventors have considered and considered that it is advantageous to form external connection terminals before peeling the multilayer wiring board from the support board containing the peelable metal foil. The present invention has been reached.
That is, when manufacturing a multilayer wiring board for a semiconductor device in which bumps as external connection terminals are formed on one side and the other side is formed on a mounting surface on which a semiconductor element is mounted, Using a peelable metal foil in which a first metal foil that is thicker than the protruding height of a bump as an external connection terminal and a second metal foil that is thinner than the first metal foil are releasably bonded via an adhesive layer, A support substrate is formed by bonding a substrate as a strong carrier on the second metal foil side, and bumps are formed by plating in the bump recesses formed in the first metal foil constituting the support substrate. A conductive pattern connected to the bump is formed on the surface of the first metal foil, and then a multilayer wiring board including the bump and the conductive pattern is formed on the first metal foil, and then the first metal foil. And the second metal foil After stripping, the is removed by etching the first metal foil bonded to the multilayer wiring board, in a method for manufacturing a multilayer wiring board for a semiconductor device, which comprises exposing the bumps.
The present invention is also a method for manufacturing a semiconductor device, wherein a semiconductor element is mounted on one side of the multilayer wiring substrate obtained by the method for manufacturing a multilayer wiring substrate for a semiconductor device.

かかる本発明において、第１金属箔内及び表面に形成したバンプ及び導体パターンと第１金属箔との境界面に、前記第１金属箔をエッチングして除去する際に、前記エッチングによって除去されない金属から成る金属層を形成することによって、第１金属箔を安心してエッチングできる。
また、第１金属箔に形成するバンプ用凹部の深さを、前記第１金属箔の厚さの８０％以下とすることによって、形成されたバンプ用凹部が第１金属箔を貫通している事態を防止できる。
更に、剥離性金属箔として、厚さが２０〜５０μｍの第１金属箔と厚さが３〜５μｍの第２金属箔とが剥離可能に接着層を介して接着されている剥離性金属箔を好適に用いることができ、絶縁層及び強力担持体としての基板としては、絶縁樹脂層及び樹脂基板を好適に用いることができる。 In the present invention, when the first metal foil is etched and removed from the bumps and conductor patterns formed in and on the surface of the first metal foil and the first metal foil is removed by etching, the metal is not removed by the etching. By forming the metal layer made of the first metal foil, the first metal foil can be etched safely.
Further, by setting the depth of the bump recess formed in the first metal foil to 80% or less of the thickness of the first metal foil, the formed bump recess penetrates the first metal foil. The situation can be prevented.
Further, as the peelable metal foil, a peelable metal foil in which a first metal foil having a thickness of 20 to 50 μm and a second metal foil having a thickness of 3 to 5 μm are bonded to each other through an adhesive layer so as to be peelable. An insulating resin layer and a resin substrate can be preferably used as the insulating layer and the substrate as the strong carrier.

本発明によれば、支持基板を構成する剥離性金属箔の第２金属箔よりも厚い第１金属箔内に形成したバンプ用凹部内に外部接続端子としてのバンプを形成すると共に、このバンプに接続された導体パターンを第１金属箔の表面に形成した後、バンプ及び導体パターンを含む多層配線基板を第１金属箔の表面上に形成する。
この様に、支持基板に接合された状態の多層配線基板に外部接続端子としてのバンプが形成されているため、第１金属箔と第２金属箔とを剥離したとき、第１金属箔が接合された多層配線基板にうねり等が発生しても、第１金属箔をエッチングにより除去することによって、外部接続端子としてのバンプが精度よく形成された多層配線基板を得ることができる。
更に、第１金属箔を多層配線基板からエッチングによって除去する際にも、このエッチングの時間は短時間で済むため、多層配線基板の全体に与えるエッチングの影響を可及的に少なくできる。
その結果、半導体素子を搭載して半導体装置に好適に用いることのできる半導体装置用の多層配線基板を得ることができる。 According to the present invention, the bump as the external connection terminal is formed in the concave portion for bump formed in the first metal foil thicker than the second metal foil of the peelable metal foil constituting the support substrate. After the connected conductor pattern is formed on the surface of the first metal foil, a multilayer wiring board including bumps and the conductor pattern is formed on the surface of the first metal foil.
In this way, since the bumps as the external connection terminals are formed on the multilayer wiring substrate bonded to the support substrate, the first metal foil is bonded when the first metal foil and the second metal foil are peeled off. Even if waviness or the like occurs in the multilayer wiring board, the multilayer wiring board on which bumps as external connection terminals are formed with high precision can be obtained by removing the first metal foil by etching.
Further, when the first metal foil is removed from the multilayer wiring board by etching, the etching time is short, and the influence of etching on the entire multilayer wiring board can be minimized.
As a result, it is possible to obtain a multilayer wiring substrate for a semiconductor device that can be suitably used for a semiconductor device by mounting a semiconductor element.

本発明に係る半導体装置用の多層配線基板の製造方法についての一例を、図１〜図５に基いて説明する。
先ず、図１（ａ）に示す様に、強力担持体としての樹脂基板１２の一面側に剥離性金属箔１０を接合して支持基板１４を形成する［図１（ｂ）］。この剥離性金属箔１０と樹脂基板１２との接合は、例えば樹脂基板１２として、ガラス繊維等の補強繊維で補強されたエポキシ樹脂等の半硬化状態の熱硬化性樹脂から成る樹脂基板１２（Ｂステージ樹脂基板１２）を用い、Ｂステージ樹脂基板１２の一面側に剥離性金属箔１０を積層して熱圧着することによって接合できる。
また、剥離性金属箔１０としては、図４に示す様に、多層配線基板に形成する予定の外部接続端子としてのバンプの突出高さよりも厚い第１金属箔１０ａと第１金属箔１０ａよりも薄い第２金属箔１０ｂとが剥離可能に接着層１０ｃを介して接着されている剥離性金属箔１０を用いる。かかる剥離性金属箔１０の第２金属箔１０ｂ側に樹脂基板１２を接合する。
この剥離性金属箔１０としては、市販されている剥離性金属箔或いは特開２００５−２６２５０６号公報で提案されている剥離性金属箔を用いることができる。特に、厚さが２０〜５０μｍの第１金属箔１０ａと厚さが３〜５μｍの第２金属箔１０ｂとが剥離可能に接着層１０ｃを介して接着されている剥離性金属箔を好適に用いることができる。この第１金属箔１０ａ及び第２金属箔１０ｂとしては銅箔が好適である。 An example of a method for manufacturing a multilayer wiring board for a semiconductor device according to the present invention will be described with reference to FIGS.
First, as shown in FIG. 1A, a peelable metal foil 10 is bonded to one surface side of a resin substrate 12 as a strong carrier to form a support substrate 14 [FIG. 1B]. The releasable metal foil 10 and the resin substrate 12 are joined by, for example, a resin substrate 12 (B) made of a semi-cured thermosetting resin such as an epoxy resin reinforced with a reinforcing fiber such as a glass fiber. The stage resin substrate 12) can be used for bonding by laminating the peelable metal foil 10 on one side of the B stage resin substrate 12 and thermocompression bonding.
Further, as shown in FIG. 4, the peelable metal foil 10 is thicker than the first metal foil 10a and the first metal foil 10a which are thicker than the protruding height of the bumps as external connection terminals to be formed on the multilayer wiring board. The peelable metal foil 10 is used in which the thin second metal foil 10b is detachably bonded via an adhesive layer 10c. The resin substrate 12 is bonded to the second metal foil 10 b side of the peelable metal foil 10.
As this peelable metal foil 10, a commercially available peelable metal foil or a peelable metal foil proposed in Japanese Patent Application Laid-Open No. 2005-262506 can be used. In particular, a peelable metal foil in which a first metal foil 10a having a thickness of 20 to 50 μm and a second metal foil 10b having a thickness of 3 to 5 μm are detachably bonded via an adhesive layer 10c is preferably used. be able to. A copper foil is suitable as the first metal foil 10a and the second metal foil 10b.

剥離性金属箔１０と樹脂基板１２とが接合された支持基板１４の第１金属箔１０ａの表面を、図１（ｂ）に示す様に、ドライフィルム１６によって部分的に被覆し、エッチングを施す部分の面を露出する。
この第１金属箔１０ａの表面が露出した部分にエッチングを施し、図１（ｃ）に示す様に、バンプ用凹部１８，１８・・を形成する。図１（ｃ）では、ドライフィルム１６を除去した状態を示す。このエッチングでは、形成されたバンプ用凹部１８の深さを、第１金属箔１０ａを貫通する事態とならないように調整する。バンプ用凹部１８が第１金属箔１０ａを貫通すると、第１金属箔１０ａと第２金属箔１０ｂとを接着する接着層１０ｃがエッチングされて、第１金属箔１０ａと第２金属箔１０ｂとが剥離するおそれがある。このため、バンプ用凹部１８の深さを、第１金属箔１０ａの厚さの８０％以下とすることが好ましい。第１金属箔１０ａに所定深さのバンプ用凹部１８をエッチングによって形成するには、予めエッチング時間とバンプ用凹部１８の深さとの関係を測定しておくことが好ましい。 As shown in FIG. 1B, the surface of the first metal foil 10a of the support substrate 14 to which the peelable metal foil 10 and the resin substrate 12 are bonded is partially covered with a dry film 16 and etched. Expose the surface of the part.
Etching is performed on the exposed portion of the surface of the first metal foil 10a to form bump recesses 18, 18,... As shown in FIG. FIG. 1C shows a state where the dry film 16 is removed. In this etching, the depth of the formed bump recess 18 is adjusted so as not to penetrate the first metal foil 10a. When the bump recess 18 penetrates the first metal foil 10a, the adhesive layer 10c that bonds the first metal foil 10a and the second metal foil 10b is etched, and the first metal foil 10a and the second metal foil 10b are etched. There is a risk of peeling. For this reason, it is preferable that the depth of the recess 18 for bumps is 80% or less of the thickness of the first metal foil 10a. In order to form the bump recesses 18 having a predetermined depth in the first metal foil 10a by etching, it is preferable to measure the relationship between the etching time and the depth of the bump recesses 18 in advance.

第１金属箔１０ａに形成したバンプ用凹部１８，１８・・内には、図１（ｄ）に示す様に、ニッケルや銅等の金属から成るバンプ２０を形成すると共に、第１金属箔１０ａの表面には、バンプ２０に接続されたニッケルや銅等の金属から成る導体パターン２２を形成する。
かかるバンプ２０及び導体パターン２２には、第１金属箔１０ａとの境界面に、図５に示す様に、後述する第１金属箔１０ａをエッチングする際に、エッチングされない金属から成る金属層２１を形成する。この金属層２１としては、金から成る金属層とすることが好ましい。
図５に示す金属層２１、バンプ２０及び導体パターン２２を形成するには、先ず、図１（ｃ）に示す第１金属箔１０ａの表面上に、バンプ２０及び導体パターン２２を形成する部分の第１金属箔１０ａの表面のみが露出するように、ドライフィルムを貼着する。
次いで、露出した第１金属箔１０ａの表面に無電解金めっきによって金から成る金属層２１を形成した後、第１金属箔１０ａを給電層とする電解ニッケルめっき又は電解銅めっきにより、バンプ２０及び導体パターン２２を形成する。その後、ドライフィルムを剥離する。 As shown in FIG. 1 (d), bumps 20 made of metal such as nickel or copper are formed in the bump recesses 18, 18,... Formed on the first metal foil 10a, and the first metal foil 10a. A conductive pattern 22 made of a metal such as nickel or copper connected to the bumps 20 is formed on the surface.
The bump 20 and the conductor pattern 22 are provided with a metal layer 21 made of a metal that is not etched when the first metal foil 10a, which will be described later, is etched, as shown in FIG. 5, on the boundary surface with the first metal foil 10a. Form. The metal layer 21 is preferably a metal layer made of gold.
In order to form the metal layer 21, the bump 20 and the conductor pattern 22 shown in FIG. 5, first, on the surface of the first metal foil 10a shown in FIG. A dry film is stuck so that only the surface of the first metal foil 10a is exposed.
Next, after the metal layer 21 made of gold is formed on the exposed surface of the first metal foil 10a by electroless gold plating, the bump 20 and the electrolytic copper plating using the first metal foil 10a as a power feeding layer are performed. Conductive pattern 22 is formed. Thereafter, the dry film is peeled off.

この様にして第１金属箔１０ａに形成したバンプ２０及び導体パターン２２上には、公知のアディティブ法やセミアディティブ法等によって、図１（ｅ）に示す様に、バンプ２０及び導体パターン２２を含む多層配線基板３０を第１金属箔１０ａの表面上に形成する。この多層配線基板３０は、絶縁樹脂層２４を介して所定の導体パターン２２，２２・・を積層すると共に、絶縁層２４を貫通して導体パターン２２，２２間を電気的に接続するヴィア２６を形成することによって、第１金属箔１０ａの表面上に形成できる
図１（ｅ）に示す支持基板１４と多層配線基板３０とは、支持基板１４を形成する剥離性金属箔１０の第１金属箔１０ａと第２金属箔１０ｂとを剥離することにより、図２に示す様に、第１金属箔１０ａ及び多層配線基板３０から成る部分と、第２金属箔１０及び樹脂基板１２から成る部分とに分離できる。 As shown in FIG. 1E, the bumps 20 and the conductor patterns 22 are formed on the bumps 20 and the conductor patterns 22 formed on the first metal foil 10a in this way by a known additive method or semi-additive method. A multilayer wiring board 30 including the same is formed on the surface of the first metal foil 10a. The multilayer wiring board 30 has predetermined conductor patterns 22, 22... Laminated via an insulating resin layer 24, and vias 26 that penetrate the insulating layer 24 and electrically connect the conductor patterns 22, 22. The support substrate 14 and the multilayer wiring substrate 30 shown in FIG. 1E can be formed on the surface of the first metal foil 10a by forming the first metal foil of the peelable metal foil 10 forming the support substrate 14. 10a and the second metal foil 10b are separated into a portion composed of the first metal foil 10a and the multilayer wiring board 30 and a portion composed of the second metal foil 10 and the resin substrate 12, as shown in FIG. Can be separated.

分離された多層配線基板３０に接合されている第１金属箔１０ａをエッチングして除去することによって、図３に示す様に、一面側にバンプ２０，２０・・が突出する多層配線基板３０を得ることができる。この第１金属箔１０ａのエッチングの際に、このエッチングによってエッチングされない金属から成る金属層２１をバンプ２０及び導体パターン２２との境界面に形成しておくことによって、バンプ２０及び導体パターン２２がエッチングされることなく第１金属箔１０ａをエッチングできる。
得られた多層配線基板３０の他面側に、図３に示す様に、半導体素子３２を搭載することによって、半導体装置を得ることができる。
以上の説明では、樹脂基板１２の一面側に剥離性金属箔１０を接合して支持基板１４を形成していたが、樹脂基板１２の両面側の各々に剥離性金属箔１０を接合して支持基板１４を形成してもよい。この場合、樹脂基板１２の両面側の各々に多層配線基板３０，３０を形成した後、各剥離性金属箔１０の第１金属箔１０ａと第２金属箔１０ｂとを剥離し、第１金属箔１０ａが接合された多層配線基板３０，３０を得ることができる。その後は、各多層配線基板３０に接合されている第１金属箔１０ａをエッチングで除去することによって、図３に示す多層配線基板３０を得ることができる。 By removing the first metal foil 10a joined to the separated multilayer wiring board 30 by etching, the multilayer wiring board 30 with bumps 20, 20,. Obtainable. When the first metal foil 10a is etched, a metal layer 21 made of a metal that is not etched by this etching is formed on the boundary surface between the bump 20 and the conductor pattern 22, so that the bump 20 and the conductor pattern 22 are etched. The first metal foil 10a can be etched without being done.
A semiconductor device can be obtained by mounting a semiconductor element 32 on the other side of the obtained multilayer wiring board 30 as shown in FIG.
In the above description, the peelable metal foil 10 is bonded to one surface side of the resin substrate 12 to form the support substrate 14. However, the peelable metal foil 10 is bonded to and supported on each of the both surface sides of the resin substrate 12. The substrate 14 may be formed. In this case, after forming the multilayer wiring boards 30 and 30 on each of the both surface sides of the resin substrate 12, the first metal foil 10a and the second metal foil 10b of each peelable metal foil 10 are peeled off to form the first metal foil. Multilayer wiring boards 30 and 30 to which 10a is bonded can be obtained. Thereafter, the first metal foil 10a bonded to each multilayer wiring board 30 is removed by etching, whereby the multilayer wiring board 30 shown in FIG. 3 can be obtained.

本発明に係る多層配線基板の製造方法の一例を説明する部分工程図である。It is a partial process figure explaining an example of the manufacturing method of the multilayer wiring board concerning the present invention. 多層配線基板３０及び第１金属箔１０ａの部分と、第２金属箔１０ｂ及び樹脂基板１２の部分とが分離された状態を説明する部分断面図である。It is a fragmentary sectional view explaining the state from which the part of the multilayer wiring board 30 and the 1st metal foil 10a, and the part of the 2nd metal foil 10b and the resin substrate 12 were isolate | separated. 多層配線基板３０に接合された第１金属箔１０ａを除去した状態を説明する部分断面図である。4 is a partial cross-sectional view illustrating a state where a first metal foil 10a bonded to a multilayer wiring board 30 is removed. FIG. 図１に示す剥離性金属箔１０を説明する部分断面図である。It is a fragmentary sectional view explaining the peelable metal foil 10 shown in FIG. 図１（ｄ）の工程で形成されるバンプ２０及び導体パターン２２の構造を説明する部分断面図である。It is a fragmentary sectional view explaining the structure of the bump 20 and the conductor pattern 22 formed at the process of FIG.1 (d). 従来の多層配線基板を製造する製造工程の一部を説明する説明図である。It is explanatory drawing explaining a part of manufacturing process which manufactures the conventional multilayer wiring board. 図６に示す従来の多層配線基板を製造する製造工程の残りの部分を説明する説明図である。It is explanatory drawing explaining the remaining part of the manufacturing process which manufactures the conventional multilayer wiring board shown in FIG.

符号の説明Explanation of symbols

１０ 剥離性金属箔
１０ａ 第１金属箔
１０ｂ 第２金属箔
１０ｃ 接着層
１２ 樹脂基板
１４ 支持基板
１６ ドライフィルム
１８ バンプ用凹部
２０ バンプ
２０ バンプ
２１ 金属層
２２ 導体パターン
２４ 絶縁層
２６ ヴィア
３０ 多層配線基板 DESCRIPTION OF SYMBOLS 10 Peelable metal foil 10a 1st metal foil 10b 2nd metal foil 10c Adhesive layer 12 Resin substrate 14 Support substrate 16 Dry film 18 Bump recessed part 20 Bump 20 Bump 21 Metal layer 22 Conductive pattern 24 Insulating layer 26 Via 30 Multilayer wiring board

Claims (6)

一面側に外部接続端子としてのバンプが形成されていると共に、他面側が半導体素子を搭載する搭載面に形成された半導体装置用の多層配線基板を製造する際に、
該外部接続端子としてのバンプの突出高さよりも厚い第１金属箔とこの第１金属箔よりも薄い第２金属箔とが剥離可能に接着層を介して接着されている剥離性金属箔を用い、前記第２金属箔側に強力担持体としての基板を接合して成る支持基板を形成し、
前記支持基板を構成する第１金属箔内に形成したバンプ用凹部内に、めっきによりバンプを形成すると共に、前記バンプに接続された導体パターンを第１金属箔の表面に形成した後、前記バンプ及び導体パターンを含む多層配線基板を前記第１金属箔上に形成し、
次いで、前記第１金属箔と第２金属箔とを剥離した後、前記多層配線基板に接合された第１金属箔をエッチングによって除去し、前記バンプを露出することを特徴とする半導体装置用の多層配線基板の製造方法。 When manufacturing a multilayer wiring board for a semiconductor device in which bumps as external connection terminals are formed on one side and the other side is formed on a mounting surface on which a semiconductor element is mounted,
A peelable metal foil in which a first metal foil that is thicker than the protruding height of a bump as the external connection terminal and a second metal foil that is thinner than the first metal foil are detachably bonded via an adhesive layer is used. Forming a support substrate formed by bonding a substrate as a strong carrier to the second metal foil side;
The bumps are formed by plating in the bump recesses formed in the first metal foil constituting the support substrate, and a conductor pattern connected to the bumps is formed on the surface of the first metal foil. And a multilayer wiring board including a conductor pattern is formed on the first metal foil,
Next, after peeling off the first metal foil and the second metal foil, the first metal foil bonded to the multilayer wiring board is removed by etching to expose the bumps. A method for manufacturing a multilayer wiring board. 第１金属箔内及び表面に形成したバンプ及び導体パターンと第１金属箔との境界面に、前記第１金属箔をエッチングして除去する際に、前記エッチングによって除去されない金属から成る金属層を形成する請求項１記載の半導体装置用の多層配線基板の製造方法。   A metal layer made of a metal that is not removed by the etching when the first metal foil is removed by etching on the boundary surface between the first metal foil and the bump and conductor pattern formed in and on the surface of the first metal foil. The method of manufacturing a multilayer wiring board for a semiconductor device according to claim 1 to be formed. 第１金属箔に形成するバンプ用凹部の深さを、前記第１金属箔の厚さの８０％以下とする請求項１又は請求項２記載の半導体装置用の多層配線基板の製造方法。   The method for manufacturing a multilayer wiring board for a semiconductor device according to claim 1 or 2, wherein a depth of the concave portion for bump formed in the first metal foil is 80% or less of a thickness of the first metal foil. 剥離性金属箔として、厚さが２０〜５０μｍの第１金属箔と厚さが３〜５μｍの第２金属箔とが剥離可能に接着層を介して接着されている剥離性金属箔を用いる請求項１〜３のいずれか一項記載の半導体装置用の多層配線基板の製造方法。   As the peelable metal foil, a releasable metal foil in which a first metal foil having a thickness of 20 to 50 μm and a second metal foil having a thickness of 3 to 5 μm are detachably bonded via an adhesive layer is used. The manufacturing method of the multilayer wiring board for semiconductor devices as described in any one of claim | item 1 -3. 絶縁層及び強力担持体としての基板として、絶縁樹脂層及び樹脂基板を用いる請求項１〜４のいずれか一項記載の半導体装置用の多層配線基板の製造方法。   The manufacturing method of the multilayer wiring board for semiconductor devices as described in any one of Claims 1-4 which uses an insulating resin layer and a resin substrate as a board | substrate as an insulating layer and a strong support body. 請求項１記載の半導体装置用の多層配線基板の製造方法によって得た多層配線基板の一面側に、半導体素子を搭載することを特徴とする半導体装置の製造方法。
A method for manufacturing a semiconductor device, comprising: mounting a semiconductor element on one side of the multilayer wiring substrate obtained by the method for manufacturing a multilayer wiring substrate for a semiconductor device according to claim 1.
JP2005358692A 2005-12-13 2005-12-13 Method of manufacturing multilayered wiring board for semiconductor device, and method of manufacturing semiconductor device Pending JP2007165513A (en)

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JP2010135474A (en) * 2008-12-03 2010-06-17 Ngk Spark Plug Co Ltd Multilayer wiring substrate and method for manufacturing same
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JP2012099808A (en) * 2010-11-04 2012-05-24 Samsung Electro-Mechanics Co Ltd Manufacturing method of circuit board
US8394225B2 (en) 2008-10-16 2013-03-12 Shinko Electric Industries Co., Ltd. Method of manufacturing wiring substrate
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US9585261B2 (en) 2011-03-30 2017-02-28 Mitsui Mining & Smelting Co., Ltd. Manufacturing method of multilayer printed wiring board
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US8394225B2 (en) 2008-10-16 2013-03-12 Shinko Electric Industries Co., Ltd. Method of manufacturing wiring substrate
JP2010135474A (en) * 2008-12-03 2010-06-17 Ngk Spark Plug Co Ltd Multilayer wiring substrate and method for manufacturing same
JP2010135721A (en) * 2008-12-08 2010-06-17 Samsung Electro-Mechanics Co Ltd Printed circuit board comprising metal bump and method of manufacturing the same
JP2010135720A (en) * 2008-12-08 2010-06-17 Samsung Electro-Mechanics Co Ltd Printed circuit board comprising metal bump and method of manufacturing the same
US9021693B2 (en) 2008-12-08 2015-05-05 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing printed circuit board with metal bump
US8207450B2 (en) 2008-12-08 2012-06-26 Samsung Electro-Mechanics Co., Ltd. Printed circuit board comprising metal bumps integrated with connection pads
KR20100114845A (en) * 2009-04-16 2010-10-26 신꼬오덴기 고교 가부시키가이샤 Wiring substrate having columnar protruding part
KR101709629B1 (en) * 2009-04-16 2017-02-23 신꼬오덴기 고교 가부시키가이샤 Method for manufacturing wiring substrate having columnar protruding part
JP2012099808A (en) * 2010-11-04 2012-05-24 Samsung Electro-Mechanics Co Ltd Manufacturing method of circuit board
US9585261B2 (en) 2011-03-30 2017-02-28 Mitsui Mining & Smelting Co., Ltd. Manufacturing method of multilayer printed wiring board
WO2016107649A1 (en) 2014-12-30 2016-07-07 Circuit Foil Luxembourg Peelable copper foils, manufacturing method of coreless substrate, and coreless substrate obtained by the manufacturing method
KR20190086358A (en) 2018-01-12 2019-07-22 신꼬오덴기 고교 가부시키가이샤 Substrate-with-support and method of manufacturing substrate-with-support
US10586758B2 (en) 2018-01-12 2020-03-10 Shinko Electric Industries Co., Ltd. Substrate-with-support

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