JPS6484737A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make some differences in heights arise from signal wires and decrease capacity between distributing wires to achieve high integration of circuits without enlarging wiring intervals on the plane, by arranging a plurality of signal wires which are formed by the second metallic wiring layer and the first wiring layer which is of no-potential and is formed at a lower part of optional signal wires. CONSTITUTION:At a semiconductor integrated circuit device equipped with the first wiring layer and the second metallic wiring layer located on the upper layer of the first wiring layer through an insulating film, signal wires 1a-1c which are formed at the second metallic wiring layer and the first wiring layer 6 which is located at a lower part of the foregoing signal wire 1b and is formed along the extended direction of the signal wire 1b are arranged. Neither of electrodes are connected to the first wiring layer 6 electrically; besides, the first wiring layer is arranged so that is layer 6 is not in existence at lower parts of the signal wires 1a and 1c which are adjacent to the signal wire 1b. For example, no-potential polysilicon 6 is formed on a field oxide film 4 and then, using aluminum 1b, signal wiring is formed on polysilicon 6 through the first and second layer films 3 and 2. Subsequently, being adjacent to signal wiring, aluminum wiring 1a and 1c are formed.