JPS64737B2 - - Google Patents

Info

Publication number
JPS64737B2
JPS64737B2 JP20229983A JP20229983A JPS64737B2 JP S64737 B2 JPS64737 B2 JP S64737B2 JP 20229983 A JP20229983 A JP 20229983A JP 20229983 A JP20229983 A JP 20229983A JP S64737 B2 JPS64737 B2 JP S64737B2
Authority
JP
Japan
Prior art keywords
message
input
central processing
output control
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP20229983A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6095666A (ja
Inventor
Seiichi Sugaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20229983A priority Critical patent/JPS6095666A/ja
Publication of JPS6095666A publication Critical patent/JPS6095666A/ja
Publication of JPS64737B2 publication Critical patent/JPS64737B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
JP20229983A 1983-10-28 1983-10-28 インタフエ−ス制御方法 Granted JPS6095666A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20229983A JPS6095666A (ja) 1983-10-28 1983-10-28 インタフエ−ス制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20229983A JPS6095666A (ja) 1983-10-28 1983-10-28 インタフエ−ス制御方法

Publications (2)

Publication Number Publication Date
JPS6095666A JPS6095666A (ja) 1985-05-29
JPS64737B2 true JPS64737B2 (enrdf_load_stackoverflow) 1989-01-09

Family

ID=16455241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20229983A Granted JPS6095666A (ja) 1983-10-28 1983-10-28 インタフエ−ス制御方法

Country Status (1)

Country Link
JP (1) JPS6095666A (enrdf_load_stackoverflow)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594733B2 (ja) * 1975-11-10 1984-01-31 日本電気株式会社 キヨウツウバスセイギヨカイロ
JPS56159750A (en) * 1980-05-14 1981-12-09 Toshiba Corp Bus control system

Also Published As

Publication number Publication date
JPS6095666A (ja) 1985-05-29

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