JPS6473767A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6473767A
JPS6473767A JP23131187A JP23131187A JPS6473767A JP S6473767 A JPS6473767 A JP S6473767A JP 23131187 A JP23131187 A JP 23131187A JP 23131187 A JP23131187 A JP 23131187A JP S6473767 A JPS6473767 A JP S6473767A
Authority
JP
Japan
Prior art keywords
film
base
poly
self
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23131187A
Other languages
Japanese (ja)
Inventor
Hiroyuki Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP23131187A priority Critical patent/JPS6473767A/en
Publication of JPS6473767A publication Critical patent/JPS6473767A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To make base resistance and base-collector capacity to be small for producing a high-density high-speed device by forming base and emitter regions with one mask matching using a self-alignment technology after forming collector region in a bipolar transistor. CONSTITUTION:An N-type Si substrate 1 is separated by an oxide film 2 as collector, poly Si3 and Si3N4 film 4 are superposed, a resist mask 5 is provided on it, dry etching is performed, and then an opening 6 is produced at the substrate 1. A mask 5 is removed and it is covered with a CVD-SiO2 film 7. A dry etching with high anisotropy is applied and CVD-SiO2 films 7a and 7b are left on the side surface of the opening 6 in self-alignment manner. A B-added poly Si 8 and a photoresist 9 are superposed on it. When the flat surface is etched and Si3N4 film 4 is exposed, only the film 7a is separated from the poly Si3 and the B-added poly Si 8a is left in self-alignment manner. A SiO2 film 10 and P<+> layer 11 are formed by heat oxidation and the Si3N4 film 4 is removed and B is added to the poly Si3 for diffusion to produce an active base 12 and an emitter 13. With this configuration, the base resistor and base collector capacity can be minimized.
JP23131187A 1987-09-16 1987-09-16 Manufacture of semiconductor device Pending JPS6473767A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23131187A JPS6473767A (en) 1987-09-16 1987-09-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23131187A JPS6473767A (en) 1987-09-16 1987-09-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6473767A true JPS6473767A (en) 1989-03-20

Family

ID=16921639

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23131187A Pending JPS6473767A (en) 1987-09-16 1987-09-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6473767A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100274604B1 (en) * 1997-01-21 2001-01-15 윤종용 Method for fabricating semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100274604B1 (en) * 1997-01-21 2001-01-15 윤종용 Method for fabricating semiconductor device

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