JPS6468864A - Parallel data processing system - Google Patents
Parallel data processing systemInfo
- Publication number
- JPS6468864A JPS6468864A JP22536287A JP22536287A JPS6468864A JP S6468864 A JPS6468864 A JP S6468864A JP 22536287 A JP22536287 A JP 22536287A JP 22536287 A JP22536287 A JP 22536287A JP S6468864 A JPS6468864 A JP S6468864A
- Authority
- JP
- Japan
- Prior art keywords
- busses
- bus
- data processing
- plural
- request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To increase the data processing speed of plural processors by issuing a bus use request to all of plural busses at the time of using busses by plural processing parts and using one of busses, whose use is permitted, to automatically transfer data. CONSTITUTION:When only one of busses 3A and 3B can be used when a data processing part 1 issues an internal bus request to both of busses 3A and 3B, this bus is used to transfer data. When the use permission signal is outputted from both of busses 3A and 3B when the data processing part 1 issues the internal bus request to both of busses 3A and 3B, the bus 3A is preferentially used by a preferential use determining circuit 8. An unused bus is always used in this manner, and the efficiency of bus is twice as high as that of a single busses. Thus, the data processing speed is increased.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22536287A JPS6468864A (en) | 1987-09-10 | 1987-09-10 | Parallel data processing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22536287A JPS6468864A (en) | 1987-09-10 | 1987-09-10 | Parallel data processing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6468864A true JPS6468864A (en) | 1989-03-14 |
Family
ID=16828154
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22536287A Pending JPS6468864A (en) | 1987-09-10 | 1987-09-10 | Parallel data processing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6468864A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56114063A (en) * | 1980-02-14 | 1981-09-08 | Mitsubishi Electric Corp | Multiprocessor |
-
1987
- 1987-09-10 JP JP22536287A patent/JPS6468864A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56114063A (en) * | 1980-02-14 | 1981-09-08 | Mitsubishi Electric Corp | Multiprocessor |
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